WO2016070463A1 - 一种半导体器件及其制作方法 - Google Patents

一种半导体器件及其制作方法 Download PDF

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Publication number
WO2016070463A1
WO2016070463A1 PCT/CN2014/091422 CN2014091422W WO2016070463A1 WO 2016070463 A1 WO2016070463 A1 WO 2016070463A1 CN 2014091422 W CN2014091422 W CN 2014091422W WO 2016070463 A1 WO2016070463 A1 WO 2016070463A1
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semiconductor device
active region
source
active
region
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PCT/CN2014/091422
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English (en)
French (fr)
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张乃千
刘飞航
裴轶
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苏州捷芯威半导体有限公司
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Priority to JP2017500047A priority Critical patent/JP6434609B2/ja
Publication of WO2016070463A1 publication Critical patent/WO2016070463A1/zh
Priority to US15/388,817 priority patent/US10361271B2/en

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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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    • H01L29/0692—Surface layout
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method of fabricating the same.
  • Gallium nitride semiconductor devices have significant advantages such as large band gap, high electron mobility, high breakdown field strength, high temperature resistance, etc., and are suitable for manufacturing high temperature, high voltage, high frequency and high power electronic devices, and have broad application prospects.
  • FIG. 1 is a top plan view showing a prior art gallium nitride semiconductor device.
  • the GaN semiconductor device includes an active region a and an inactive region b, and the active region a is a closed region.
  • the region other than the source region a is the passive region b, and the source electrode 11, the drain electrode 12, and the gate electrode 13 located in the active region a are repeatedly arranged in the device width direction to constitute an integral interdigitated structure, and the entire semiconductor device has a rectangular shape.
  • the plurality of repeatedly arranged drain electrodes 12 are connected together by a drain interconnection metal 14 located in the inactive region, and the plurality of repeatedly arranged gate electrodes 13 are connected together by a gate interconnection metal 131, and the semiconductor device is passed through a lead pad 15 receives the signal from the outside, but because the power density of the GaN semiconductor device is very high, its thermal density is also high, resulting in a very large amount of heat generated by the GaN semiconductor device during operation, if the heat cannot be dissipated in time. , which will cause the internal temperature of the GaN semiconductor device to rise, affecting the stability and reliability of the device, and limiting the further improvement of the output power of the GaN semiconductor device.
  • FIG. 2 is a schematic top view of a gallium nitride semiconductor device after increasing the heat dissipation area in the prior art, and the GaN semiconductor device shown in FIG. 2 increases the distance between the gate electrodes 13 (Gate to Gate space), by increasing the width of the entire GaN semiconductor device to increase the heat dissipation area and improving heat dissipation, but this will make the entire GaN semiconductor device wide, so that the GaN semiconductor device has a large aspect ratio, The subsequent process is more difficult (such as cutting and packaging), the yield is reduced, the performance is reduced (the gate resistance is increased or the RF signal phase is not synchronized), and the heat in the central region of the GaN semiconductor device cannot be timely distributed. When it comes out, the center temperature is still high, the edge temperature is low, and the temperature distribution is still uneven.
  • the present invention provides a semiconductor device and a method of fabricating the same, wherein the plurality of active region cells are staggered in the length direction of the semiconductor device by disposing the active region as a plurality of active region cells.
  • the plurality of active area cells are staggered in the width direction of the semiconductor device, since the amount of heat generated in each active area unit is small, and can be dissipated through the surrounding passive area in time, thereby reducing the internal temperature of the semiconductor device.
  • the uniform temperature distribution inside the semiconductor device is uniform, and the reliability of the semiconductor device is improved.
  • an embodiment of the present invention provides a semiconductor device, the semiconductor device including:
  • An active region and a passive region including a plurality of active region cells staggered in a length direction of the semiconductor device, and the plurality of active region cells In the half
  • the conductor devices are staggered in the width direction.
  • any two adjacent active area units overlap or do not overlap in the length direction of the semiconductor device, and any two adjacent active area units are crossed in the width direction of the semiconductor device Stacked or not overlapping.
  • the front surface of the semiconductor device includes a source stage, a gate and a drain located in the active region, and sources, gates and drains in the active region are distributed in the active region unit of the active region Also included are drain interconnect metals, gate interconnect metals, and/or source interconnect metals located in the passive region.
  • drains in the active regions are connected together by drain interconnect metals located in the active regions, the gates in the active regions being connected together by gate interconnect metals located in the inactive regions.
  • a ground electrode is disposed on a back surface of the semiconductor device
  • the semiconductor device further includes: a first via hole penetrating the semiconductor device between the source-level interconnect metal and the ground electrode, and/or a through-between the source level and the ground electrode a second via hole of the semiconductor device;
  • Each of the source electrodes is electrically connected to the ground electrode through the source interconnection metal and the first via hole;
  • the source is electrically connected to the ground electrode through the second through hole;
  • the source is connected to the source interconnect metal through an air bridge, the air bridge is bridged over the gate interconnect metal, the source passes through the air bridge, the source level interconnect metal and The first via hole is electrically connected to the ground electrode.
  • the material of the semiconductor device is gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, Any combination of one or more of gallium arsenide, silicon carbide, diamond, sapphire or silicon.
  • an embodiment of the present invention provides a method of fabricating a semiconductor device, the method comprising:
  • an active region including a plurality of active region cells, the plurality of active region cells staggered in a length direction on the semiconductor device, and the plurality of active regions
  • the cell units are staggered in the width direction of the semiconductor device.
  • the method further includes:
  • a drain interconnect metal, a gate interconnect metal, and/or a source interconnect metal are formed in a passive region of the front surface of the semiconductor device.
  • drains in the active regions are connected together by drain interconnect metals located in the active regions, the gates in the active regions being connected together by gate interconnect metals located in the inactive regions.
  • an active region and an inactive region of the semiconductor device are formed using a mesa etching process, an ion implantation process, and/or an oxidation isolation process.
  • the present invention sets the active region as a plurality of active region cells staggered in the length direction of the semiconductor device, and the plurality of active region cells are in the semiconductor device
  • the width direction is staggered.
  • the invention increases the overall length of the semiconductor device and increases the heat dissipation area of the semiconductor device. Since the heat generated in each active area unit is small and can be dissipated through the surrounding passive area in time, the heat is accelerated.
  • the emission reduces the internal temperature of the semiconductor device, makes the internal temperature distribution of the semiconductor device uniform, and on the other hand increases the overall length of the semiconductor device, and the width of the semiconductor device does not increase, thereby reducing the width and length of the entire semiconductor device. Compared, the subsequent process difficulty (such as cutting and packaging) is reduced, the device yield is improved, and the influence of the aspect ratio on the device performance is improved.
  • FIG. 1 is a top plan view showing a prior art gallium nitride semiconductor device
  • FIG. 2 is a top plan view showing a gallium nitride semiconductor device after increasing a heat dissipation area in the prior art
  • 3A-3D are top plan views of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 4 and FIG. 5A to FIG. 5C are schematic plan views showing a semiconductor device according to Embodiment 2 of the present invention.
  • 6A-6E are schematic top views of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 is a flow chart showing a method of fabricating a semiconductor device according to Embodiment 4 of the present invention.
  • 3A-3D are top plan views of a semiconductor device according to a first embodiment of the present invention.
  • the semiconductor device D1 includes an active area a and an inactive area b.
  • the region a includes a plurality of active region cells (eg, a1 and a2) staggered in the length direction of the semiconductor device, and the plurality of active region cells are in the semiconductor The devices are staggered in the width direction.
  • the length direction of the semiconductor device D1 is designated as the X direction
  • the width direction of the semiconductor device D1 is designated as the Y direction, wherein the X direction is perpendicular to the Y direction.
  • the area outside the active area a is an inactive area, and there is a two-dimensional electron gas, electron or hole under the active area a, which is a working area of the semiconductor device, and the underside of the passive area b is engraved through the mesa
  • the etch process (MESA etch), the ion implantation process, and/or the oxidative isolation process eliminate or isolate the two-dimensional electron gas, electrons or holes underneath it, not the internal working area of the semiconductor device, and may be in the passive region b.
  • a plurality of traces are arranged to connect the source, gate or drain in the plurality of active region cells in the active region a to form a large semiconductor device.
  • any two adjacent active area units of the plurality of active area units overlap in the length direction of the semiconductor device D1 (eg, FIG. 3A) or not Stacks (eg, FIG. 3B, FIG. 3C, and FIG. 3D), and any two adjacent active area cells overlap in the width direction of the semiconductor device D1 (eg, FIG. 3A) or do not overlap (eg, Figure 3B, Figure 3C and Figure 3D).
  • the material of the semiconductor device D1 may be gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, Any combination of one or more materials of gallium arsenide, silicon carbide, diamond, sapphire or silicon, since the thermal conductivity of the silicon carbide material is high, a silicon carbide material is preferred, so that the active region of the semiconductor device The heat generated in a can be laterally transmitted to the passive area b where there is no heat source in time, which accelerates the heat dissipation and lowers the internal temperature of the device.
  • each active area unit in the active region of the semiconductor device may be various, for example, each active region
  • the cell may include a source, a gate and/or a drain, and may include only a single gate, a source and a drain, or may include a plurality of repeatedly arranged gates, source and drain electrodes, and multiple gates.
  • the source and drain electrodes may be distributed in an interdigitated shape or the like, and therefore, the present embodiment should not be construed as limiting the semiconductor structure of the present invention.
  • FIGS. 3A to 3D are only schematic representations of two active devices located in the active region a. a region unit, the active region of the semiconductor device may include, but does not have to include, two active region units (a1 and a2). This embodiment is only a preferred embodiment, and is not in the active region. The number of active area cells is defined, and therefore, the schematic structure of the semiconductor device shown in FIGS. 3A to 3D should not be limited as an embodiment of the present invention.
  • a semiconductor device by arranging a plurality of active area cells staggered in a length direction of the semiconductor device, and staggering a plurality of active area cells in a width direction of the semiconductor device, On the one hand, the heat dissipation area of the semiconductor device is increased, the heat dissipation in the active region is accelerated, the internal temperature of the semiconductor device is lowered, the internal temperature distribution of the semiconductor device is uniform, and on the other hand, the aspect ratio of the semiconductor device can be improved. To improve the yield of semiconductor devices.
  • the semiconductor device D2 includes an active region and an inactive region b, and the region outside the active region is abs. a source region b, the active region including a plurality of active region cells (eg, a1, a2, a3, and a4) staggered in a length direction of the semiconductor device, A plurality of active area cells are staggered in the width direction of the semiconductor device.
  • a source region b the active region including a plurality of active region cells (eg, a1, a2, a3, and a4) staggered in a length direction of the semiconductor device.
  • a plurality of active area cells are staggered in the width direction of the semiconductor device.
  • the active region of the semiconductor device D2 includes a plurality of active region cells (eg, a1, a2, a3, and a4), and in the width direction of the semiconductor device, a plurality of active region cells (eg, a1, a2, a3, and A4) staggered, and adjacent two active area units (for example, a1 and a2, a2 and a3, a3, and a4) are staggered with each other in the width direction of the semiconductor device, and the plurality of the semiconductor device are longitudinally oriented
  • the active area cells (eg, a1, a2, a3, and a4) are staggered, that is, the plurality of active area cells are divided into at least two columns in the length direction of the semiconductor device (for example, a1 and a2 are different in the length direction of the semiconductor device)
  • the two columns) and the adjacent two active area units are arranged to be staggered with each other in the longitudinal direction of the semiconductor device, thereby increasing the length of the semiconductor device, but the
  • the front surface of the semiconductor device D2 may further include a source 11, a drain 12 and a gate 13 in the active region, and further include a drain interconnection metal 14 in the inactive region b, A gate interconnect metal 131 in which the source 11, the gate 13 and the drain 12 are distributed within the active region unit.
  • the source 11 and the drain 12 are ohmic contact electrodes. Further, the drains 12 in the active region are connected together through the drain interconnect metal 14 and the gates in the active region are gated through the gate interconnect metal 131. The poles 13 are connected together to form an overall large size device so that the semiconductor device can output a large amount of power.
  • the drain interconnect metal 14 and the gate interconnect metal 131 may further include a lead pad (PAD) 15 to transmit an external signal to the semiconductor through the lead PAD 15
  • PAD lead pad
  • the body device D2 the material of the lead PAD 15 may be metal, and the length of the electrical connection between the lead PAD 15 and the gate 13 or the drain 12 is preferably equal, that is, the signal reaching the gate 13 or the drain 12 is preferably equi-phase. of.
  • the source of the semiconductor device D2 can be connected through different interconnection manners. Specifically, please refer to FIG. 5A to FIG. 5C, and FIG. 5A to FIG. Top view of the device.
  • a drain interconnection metal 14, a gate interconnection metal 131, and a source interconnection metal 111 are disposed in the passive region b.
  • the back surface of the semiconductor device D2 is provided with a ground electrode (not shown).
  • the semiconductor device D2 further includes a first via hole 16 penetrating the semiconductor device D2 between the source interconnection metal 111 and the ground electrode, each source 11 interconnecting the metal 111 and the first through the source The through hole 16 is electrically connected to the ground electrode.
  • a back surface of the semiconductor device is provided with a ground electrode (not shown), and the semiconductor device D2 further includes a second through the semiconductor device D2 between the source 11 and the ground electrode.
  • the through hole 17 is electrically connected to the ground electrode through the second through hole 17 .
  • the source 11 of the semiconductor device D2 is connected to the source interconnection metal 111 through an air bridge 112.
  • the air bridge 112 is connected across the gate interconnection metal 131, the source.
  • the interconnect metal 111 is electrically connected to the ground electrode through the air bridge 112, the source interconnect metal 111, and the first via hole 16.
  • All of the semiconductor device active region units may include, but do not necessarily include, three source electrodes 11, four gate electrodes 13 and two drain electrodes 12.
  • the number of active region cells in the semiconductor device may be Including but not necessarily including four, this embodiment is only a preferred embodiment, and does not have the number of source 11, gate 13 and drain 12 in each active cell and the active region included in the active region. The number of units is limited.
  • Figure 4 and Figures 5A-5C just cite one and a half The form of the conductor device structure and wiring is not representative of such a structure, and therefore, the schematic structure of the semiconductor device shown in Fig. 4 and Figs. 5A to 5C should not be construed as limiting the embodiment of the invention.
  • the semiconductor device provided by the embodiment of the invention increases the heat dissipation area of the semiconductor device on the one hand, can accelerate the heat dissipation, reduce the internal temperature of the semiconductor device, improve the uniformity of the temperature distribution inside the semiconductor device, and improve the semiconductor on the other hand.
  • the aspect ratio of the device reduces the subsequent process difficulty (such as cutting and packaging), improves the yield of the semiconductor device, and further increases the device size and increases the output power while ensuring the performance and reliability of the semiconductor device.
  • Embodiment 3 of the present invention is based on the above embodiment, and Embodiment 3 of the present invention will be described below with reference to FIGS. 6A-6E.
  • the active region of the semiconductor device D3 includes a plurality of active region cells (eg, a1, a2, a3, and a4), each of which includes a source 11 therein. a gate electrode 13 and a drain electrode 12, the source electrode 11, the gate electrode 13 and the drain electrode 12 forming a local interdigitated structure in the active region unit, and any two adjacent active region cells in the semiconductor device There is no overlap in the length direction and the width direction. Specifically, any two adjacent active area units are completely staggered in the length direction of the semiconductor device, and are partially staggered in the width direction of the semiconductor device (eg, a1 and a2).
  • active region cells eg, a1, a2, a3, and a4
  • the advantage of such processing is that the distance between adjacent two active area units in the width direction of the semiconductor device can be reduced, so that the area of the inactive area b can be slightly in the case where the heat generated by the semiconductor device is not very large. Smaller, the area of the active area of the semiconductor device is larger than the area of the inactive area b, thereby saving the entire semiconductor device area and increasing the yield of the entire wafer material.
  • any two adjacent regions in the active region of the semiconductor device D3 The active area cells overlap in the length direction of the semiconductor device, and any two adjacent active area cells overlap in the width direction of the semiconductor device (eg, a1 and a2), wherein one active area unit
  • the source 11 in the middle overlaps with the source 11 in the other active area unit.
  • FIG. 6B can also reduce the area of the passive region b of the semiconductor device, thereby enabling the yield of the wafer material to be improved.
  • any two adjacent active area units in the active region of the semiconductor device D3 do not overlap in the width direction and the length direction of the semiconductor device, specifically The adjacent two active area cells are completely shifted in the width direction of the semiconductor device, and any two adjacent active area cells are partially shifted in the length direction of the semiconductor device (e.g., a1 and a2).
  • any two adjacent active area units in the semiconductor device D3 shown in FIG. 6D do not overlap in the width direction and the length direction of the semiconductor device, and specifically, any two adjacent ones have
  • the source cell unit is completely staggered in the width direction of the semiconductor device, and any two adjacent active cell units are also completely shifted in the length direction of the semiconductor device (eg, a1 and a2) such that the area of the passive region b of the semiconductor device Greater than the area of the active area.
  • the heat generated by the semiconductor device is very large, the area of the passive region b can be further increased, and the heat generated in the active region can be laterally transmitted to the passive region where there is no heat source in time, thereby accelerating heat dissipation and reducing The internal temperature of the semiconductor device.
  • the plurality of active area units of the semiconductor device may be any combination of two adjacent active area units in the semiconductor device shown in FIG. 6A to FIG. 6D, and this embodiment is only a preferred implementation. For example, it is not intended to limit the invention.
  • the number of active area units in the length direction and the width direction of the semiconductor device is not limited, for example, as shown in FIG. 6E, a plurality of active area units (a1). A2, a3, a4, and a5) are staggered in the width direction of the semiconductor device D3, in the longitudinal direction of the semiconductor device D3, a plurality of active region cells are staggered, and a plurality of active region cells are arranged in three columns, Making the length of the semiconductor device D3 longer, introduced in the length direction of the semiconductor device D3 The area of the passive region b is larger, the heat dissipation effect is better, the temperature uniformity inside the semiconductor device is further improved, and the aspect ratio of the semiconductor device is further reduced.
  • the semiconductor device provided by the embodiment of the present invention can flexibly change the area of the active area and the area of the inactive area by changing the manner in which the plurality of active area units are staggered in the longitudinal direction and the width direction of the semiconductor device, respectively. Flexible change of the aspect ratio of semiconductor devices.
  • FIG. 7 is a flow chart showing a method of fabricating a semiconductor device according to a fourth embodiment of the present invention. The method for fabricating the semiconductor device is used to fabricate the semiconductor device described in the embodiment of the present invention. :
  • Step S1 forming an active region including a plurality of active region cells, the plurality of active region cells staggered in a length direction on the semiconductor device, and the plurality of active region cells
  • the active area cells are staggered in the width direction of the semiconductor device.
  • Two-dimensional electron gas, electrons or holes exist under the active region, which is a working region of the semiconductor device, and the underlying region is subjected to a mesa etching process (MESA etch), an ion implantation process and/or an oxidation isolation process. Eliminating the two-dimensional electron gas, electrons or holes underneath it, not the internal working area of the semiconductor device, some traces can be arranged in the passive region to connect the components in the active region to form a large Semiconductor device.
  • MEA etch mesa etching process
  • the area of the active area may be equal to the area of the passive area, and the area of the active area may also be smaller than the area of the passive area, and the area of the active area may also be larger than the passive area. Area.
  • the active region and the inactive region of the semiconductor device may be formed using a mesa etching process, an ion implantation process, and/or an oxidation isolation process.
  • the manufacturing method of the semiconductor device may further include:
  • Step S2 forming a source, a gate, and a drain in an active region of a front surface of the semiconductor device, wherein sources, gates, and drains in the active region are distributed in an active region of the active region Within the zone unit.
  • Step S3 forming a drain interconnect metal, a gate interconnect metal, and/or a source interconnect metal in a passive region of the front surface of the semiconductor device.
  • the drains in the active region are connected together by a drain interconnect metal located in the active region, and the gates in the active region pass through a gate interconnect metal located in the passive region. connected.
  • a lead PAD may be formed on the drain interconnection metal or the gate interconnection line to input a signal into the semiconductor device through the lead PAD.
  • a ground electrode may be formed on the back surface of the semiconductor device.
  • source interconnection metals are formed in the inactive region, each source is connected to the inactive region through the source interconnection metal, and a semiconductor penetrating through the semiconductor device is formed between the source interconnection metal and the ground electrode a first via hole, each of the source electrodes being electrically connected to the ground electrode through the source interconnection metal and the first via hole.
  • a second via hole penetrating the semiconductor device may be formed between a source of the active region of the semiconductor device and the ground electrode, thereby passing the source through the second via hole and The ground electrode is electrically connected.
  • an air bridge may be formed in the passive region, the air bridge spanning over the gate interconnect metal, the source passing through the air bridge, the source level interconnect metal, and the first The through hole is electrically connected to the ground electrode.
  • a method of fabricating a semiconductor device by forming an active region and an inactive region on a semiconductor device, the active region including a plurality of active region cells, wherein the plurality of active region cells are
  • the staggered arrangement of the semiconductor devices in the length direction and the width direction increases the overall length of the semiconductor device on the one hand, and increases the heat dissipation area of the semiconductor device due to the generation in each local active area unit.
  • the heat is small and can be dissipated through the surrounding passive area in time, thereby accelerating the heat dissipation, reducing the internal temperature of the semiconductor device, making the internal temperature distribution of the semiconductor device uniform, and increasing the overall length of the semiconductor device.
  • the width of the semiconductor device is not increased, thereby reducing the aspect ratio of the entire semiconductor device, reducing the subsequent process difficulty (such as cutting and packaging), improving the device yield, and improving the aspect ratio to the device performance. Impact.
  • the present invention discloses a semiconductor device including an active region and an inactive region, the active region including a plurality of active region cells, and the plurality of active region cells in the The semiconductor devices are staggered in the longitudinal direction, and the plurality of active region cells are staggered in the width direction of the semiconductor device.
  • the invention increases the overall length of the semiconductor device, increases the heat dissipation area of the semiconductor device, accelerates the heat dissipation, makes the internal temperature distribution of the semiconductor device uniform, reduces the width-to-length ratio of the entire semiconductor device, and reduces the aspect ratio. Increase the impact on device performance and reduce the difficulty of subsequent processes.

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Abstract

一种半导体器件及其制作方法，所述半导体器件包括有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件的长度方向上交错排列，所述多个有源区单元在所述半导体器件的宽度方向上交错排列。该半导体器件增加了整体长度，增大了散热面积，加快了热量的散发，使得半导体器件的内部温度分布均匀；减小了整个半导体器件的宽长比，减轻了宽长比增大对器件性能的影响，并且还能降低后续工艺难度。

Description

一种半导体器件及其制作方法
本专利申请要求于2014年11月6日提交的、申请号为2014106191820、申请人为苏州捷芯威半导体有限公司、发明名称为“一种半导体器件及其制作方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法。
背景技术
氮化镓半导体器件具有禁带宽度大、电子迁移率高、击穿场强高、耐高温等显著优点，适合制作高温、高压、高频和大功率的电子器件，具有广阔的应用前景。
请参见图1，图1示出了现有技术中氮化镓半导体器件的俯视示意图，所示氮化镓半导体器件包括有源区a和无源区b，有源区a为封闭区域，有源区a之外的区域为无源区b，位于有源区a内的源极11、漏极12和栅极13在器件宽度方向上重复排列组成整体插指状结构，整个半导体器件呈长方形，重复排列的多个漏极12通过位于无源区内的漏极互联金属14连接在一起，重复排列的多个栅极13通过栅极互连金属131连接在一起，半导体器件通过引线衬垫15接收来自外部的信号，但是由于氮化镓半导体器件的功率密度非常高，因此其热密度也很高，导致氮化镓半导体器件在工作过程产生的热量非常大，如果这些热量不能及时散发出去，就会造成氮化镓半导体器件内部温度升高，影响器件的稳定性和可靠性，同时限制了氮化镓半导体器件输出功率的进一步提升， 此外，现有技术中的氮化镓半导体器件绝大部分区域都是有源区a，氮化镓半导体器件中心区域的热量无法通过横向路径及时传导出去，而纵向路径导热能力又会达到饱和，最终造成氮化镓半导体器件中心区域温度较高，边缘温度较低，即温度分布不均匀，使得氮化镓半导体器件特性退化并且可靠性降低。
请参见图2，图2示出了现有技术中增加散热面积后的氮化镓半导体器件的俯视示意图，图2所示的氮化镓半导体器件增加了栅极13之间的距离(Gate to gate space)，通过拉大整个氮化镓半导体器件的宽度来增加散热面积，改善散热，但是这样会使整个氮化镓半导体器件很宽，使得氮化镓半导体器件宽长比会很大，从而造成后续工艺难度增大(如切割和封装等)、成品率下降、性能降低(栅电阻增大或射频信号相位不同步)等，并且这种氮化镓半导体器件中心区域的热量还是不能及时散发出来，中心温度仍然较高，边缘温度较低，温度分布仍然不均匀。
发明内容
有鉴于此，本发明提出了一种半导体器件及其制作方法，通过将有源区设置为多个有源区单元，所述多个有源区单元在半导体器件的长度方向上交错排列，所述多个有源区单元在半导体器件的宽度方向上交错排列，由于每个有源区单元内产生的热量较小，并且可以及时通过周围的无源区散发出去，从而降低半导体器件的内部温度，使得半导体器件内部温度分布均匀，提高半导体器件的可靠性。
第一方面，本发明实施例提供了一种半导体器件，所述半导体器件包括：
有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件的长度方向上交错排列，以及所述多个有源区单元在所述半 导体器件的宽度方向上交错排列。
进一步地，任意两个相邻的有源区单元在所述半导体器件的长度方向上交叠或不交叠，以及任意两个相邻的有源区单元在所述半导体器件的宽度方向上交叠或不交叠。
进一步地，
所述半导体器件的正面包括位于有源区内的源级、栅极和漏极，所述有源区内的源极、栅极和漏极分布在所述有源区的有源区单元内；还包括位于无源区内的漏级互联金属、栅极互联金属和/或源级互联金属。
进一步地，
所述有源区内的漏极通过位于无源区内的漏极互联金属连接在一起，所述有源区内的栅极通过位于无源区内的栅极互连金属连接在一起。
进一步地，
所述半导体器件的背面设置有接地电极；
所述半导体器件还包括：位于所述源级互联金属和所述接地电极间的贯穿所述半导体器件的第一通孔，和/或位于所述源级和所述接地电极间的贯穿所述半导体器件的第二通孔；
每个所述源极通过所述源极互联金属和所述第一通孔与所述接地电极电性连接；或者
所述源极通过所述第二通孔与所述接地电极电性连接；或者
所述源极通过空气桥与源极互联金属连接在一起，所述空气桥跨接在所述栅极互连金属上方，所述源极通过所述空气桥、所述源级互联金属和所述第一通孔与所述接地电极电性连接。
进一步地，所述半导体器件的材料为氮化镓、铝镓氮、铟镓氮、铝铟镓氮、 砷化镓、碳化硅、金刚石、蓝宝石或硅中的一种或多种任意组合。
第二方面，本发明实施例提供了一种半导体器件的制作方法，所述方法包括：
形成有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件上的长度方向上交错排列，以及所述多个有源区单元在所述半导体器件的宽度方向上交错排列。
进一步地，所述方法还包括：
在所述半导体器件的正面的有源区内形成源极、栅极和漏极，所述有源区内的源极、栅极和漏极分布在所述有源区的有源区单元内；
在所述半导体器件的正面的无源区内形成漏极互联金属、栅极互联金属和/或源极互联金属。
进一步地，
所述有源区内的漏极通过位于无源区内的漏极互联金属连接在一起，所述有源区内的栅极通过位于无源区内的栅极互连金属连接在一起。
进一步地，利用台面刻蚀工艺、离子注入工艺和/或氧化隔离工艺形成所述半导体器件的有源区和无源区。
本发明通过将有源区设置为多个有源区单元，所述多个有源区单元在所述半导体器件的长度方向上交错排列，以及所述多个有源区单元在所述半导体器件的宽度方向上交错排列。本发明一方面增加了半导体器件的整体长度，增大了半导体器件的散热面积，由于每个有源区单元内产生的热量较小，并且可以及时通过周围的无源区散发出去，加快了热量的散发，降低了半导体器件的内部温度，使得半导体器件的内部温度分布均匀，另一方面增加了半导体器件的整体长度，而半导体器件的宽度没有增加，从而减小了整个半导体器件的宽长 比，降低了后续工艺难度(如切割和封装等)，提高了器件成品率，改善了宽长比增大对器件性能的影响。
在阅读具体实施方式并且在查看附图之后，本领域的技术人员将认识到另外的特征和优点。
附图说明
现将参照附图解释示例。附图用于说明基本原理，使得仅图示了理解基本原理所必需的方面。附图并非依比例绘制。在附图中相同的附图标记表示相似的特征。
图1示出了现有技术中氮化镓半导体器件的俯视示意图；
图2示出了现有技术中增加散热面积后的氮化镓半导体器件的俯视示意图；
图3A-图3D示出了本发明实施例一提供的半导体器件的俯视示意图；
图4以及图5A-图5C示出了本发明实施例二提供的半导体器件的俯视示意图；
图6A-图6E示出了本发明实施例三提供的半导体器件的俯视示意图；
图7示出了本发明实施例四提供的半导体器件制作方法的流程图。
具体实施方式
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。诸如“下面”、“下方”、“在...下”、“低”、“上方”、“在...上”、“高”等的空间关系术语用于使描述方便，以解释一个元件相对于第二元件的定位，表示除了与图中示出的那些取向不同的取向以外，这些术语旨在涵盖器件的不同取向。另外，例如“一个元件在另一个元件上/下”可以表示两个元件直接接触，也可以表示 两个元件之间还具有其他元件。此外，诸如“第一”、“第二”等的术语也用于描述各个元件、区、部分等，并且不应被当作限制。类似的术语在描述通篇中表示类似的元件。
实施例一
图3A-图3D示出了本发明实施例一提供的半导体器件的俯视示意图，请参见图3A-图3D，所述半导体器件D1包括：有源区a和无源区b，所述有源区a包括多个有源区单元(如：a1和a2)，所述多个有源区单元在所述半导体器件的长度方向上交错排列，以及所述多个有源区单元在所述半导体器件的宽度方向上交错排列。
在本实施例中，所述半导体器件D1的长度方向被指定为X方向，所述半导体器件D1的宽度方向被指定为Y方向，其中，X方向与Y方向垂直。
所述有源区a之外的区域为无源区，所述有源区a下方存在二维电子气、电子或空穴，是半导体器件的工作区域，所述无源区b下方通过台面刻蚀工艺(MESA etch)、离子注入工艺和/或氧化隔离工艺后消除或隔离掉了位于其下的二维电子气、电子或空穴，不是半导体器件的内部工作区域，可以在无源区b布置一些走线，以便将位于有源区a内多个有源区单元中的源极、栅极或漏极连接起来，从而形成一个大的半导体器件。
进一步地，所述多个有源区单元(如：a1和a2)中任意两个相邻的有源区单元在所述半导体器件D1的长度方向上交叠(如：图3A)或不交叠(如：图3B、图3C和图3D)，以及任意两个相邻的有源区单元在所述半导体器件D1的宽度方向上交叠(如：图3A)或不交叠(如：图3B、图3C和图3D)。
所述半导体器件D1的材料可以为氮化镓、铝镓氮、铟镓氮、铝铟镓氮、 砷化镓、碳化硅、金刚石、蓝宝石或硅中的一种材料或多种材料的任意组合，由于碳化硅材料的导热率较高，因此优选碳化硅材料，使得所述半导体器件的有源区a内产生的热量可以及时横向传导至周围没有发热源的无源区b，加快了热量的散发，降低了器件内部温度。
还需要说明的是，本实施例只是示意性的描述了所述半导体器件，由于所述半导体器件的有源区内每个有源区单元的结构可以是很多种，例如：每个有源区单元内可以包含源极、栅极和/或漏极，可以只包含单个的栅极、源级和漏极，也可以包含多个重复排列的栅极、源级和漏极，多个栅极、源级和漏极可以呈叉指状等形状分布，因此，不应以本实施例作为对本发明半导体结构的限定。
需要说明的是，此处所描述的半导体器件仅仅用于解释本发明，而非对本发明的限定，图3A-图3D只是示意性的示出了位于所述有源区a内的两个有源区单元，所述半导体器件的所述有源区内可以包含但并非一定要包含2个有源区单元(a1和a2)，本实施例只是一个优选实施例，并不对所述有源区内有源区单元的数目进行限定，因此，不应以图3A-图3D所示的半导体器件的示意性结构作为对本发明实施例的限定。
本发明实施例提供的半导体器件，通过将多个有源区单元设置为在所述半导体器件的长度方向上交错排列，以及多个有源区单元在所述半导体器件的宽度方向上交错排列，一方面增大了半导体器件的散热面积，加快了有源区内热量的散发，降低了半导体器件的内部温度，使得半导体器件的内部温度分布均匀，另一方面，能够改善半导体器件的宽长比，提高半导体器件的成品率。
实施例二
图4示出了本发明实施例二提供的半导体器件的俯视示意图，请参见图4，所述半导体器件D2包括：有源区和无源区b，所述有源区之外的区域为无源区b，所述有源区包括多个有源区单元(如：a1、a2、a3和a4)，所述多个有源区单元在所述半导体器件的长度方向上交错排列，所述多个有源区单元在所述半导体器件的宽度方向上交错排列。
所述半导体器件D2的有源区包括多个有源区单元(如：a1、a2、a3和a4)，在半导体器件的宽度方向，多个有源区单元(如：a1、a2、a3和a4)交错排列，并且相邻两个有源区单元(例如：a1和a2、a2和a3、a3和a4)在半导体器件的宽度方向相互错开排列，在半导体器件的长度方向，所述多个有源区单元(如：a1、a2、a3和a4)交错排列，即多个有源区单元在半导体器件的长度方向分成至少两列(例如：a1和a2在半导体器件的长度方向上位于不同的两列)，并且相邻两个有源区单元在半导体器件的长度方向相互错开排列，从而增加了半导体器件的长度，但是半导体器件的宽度没有发生变化。
优选的，所述半导体器件D2的正面还可包括位于所述有源区内的源极11、漏极12和栅极13，还包括位于所述无源区b内的漏极互联金属14、栅极互联金属131，所述有源区内的源极11、栅极13和漏极12分布在所述有源区单元内。
所述源极11和漏极12为欧姆接触电极，进一步的，通过漏极互联金属14将有源区内的漏极12连接在一起，通过栅极互连金属131将有源区内的栅极13连接在一起，从而形成一个整体大尺寸器件，使得半导体器件可以输出很大的功率。
在本实施例中，所述漏极互联金属14和所述栅极互连金属131上还可以包括引线衬垫(PAD)15，从而通过所述引线PAD 15将外部信号传输到所述半导 体器件D2，引线PAD 15的材料可以为金属，所述引线PAD 15与栅极13或漏极12的电连接长度最好相等，即到达栅极13或漏极12的信号最好是等相位的。
优选的，在本实施例中，所述半导体器件D2的源极可以通过不同的互联方式进行连接，具体地，请参见图5A-图5C，图5A-图5C是本发明实施例二提供半导体器件的俯视图。
请参见图5A，所述无源区b内设置有漏极互联金属14、栅极互联金属131和源极互联金属111，所述半导体器件D2的背面设置有接地电极(图未示)，所述半导体器件D2还包括位于所述源极互联金属111和所述接地电极间的贯穿所述半导体器件D2的第一通孔16，每一个源极11通过源极互联金属111和所述第一通孔16与所述接地电极电性连接。
请参见图5B，所述半导体器件的背面设置有接地电极(图未示)，所述半导体器件D2还包括位于所述源极11和所述接地电极间的贯穿所述半导体器件D2的第二通孔17，所述源极11通过所述第二通孔17与所述接地电极电性连接。
请参见图5C，所述半导体器件D2的源极11通过空气桥112与源极互联金属111连接在一起，所述空气桥112跨接在所述栅极互连金属131上方，所述源极互联金属111通过所述空气桥112、所述源极互联金属111和第一通孔16与所述接地电极电性连接。
本领域技术人员可以理解，此处所描述的半导体器件仅仅用于解释本发明，而非对本发明的限定。所有的半导体器件的有源区单元内可以包含但并非一定要包含3个源极11、4个栅极13和2个漏极12，同理，所述半导体器件内有源区单元的数目可以包含但并非一定要包含4个，本实施例只是一个优选实施例，并不对每个有源区单元内源极11、栅极13和漏极12的数目以及有源区所包含的有源区单元的数目进行限定。或者，图4以及图5A-图5C只是举出了一种半 导体器件结构和布线的形式，并不代表只能是该种结构，因此，不应以图4以及图5A-图5C所示的半导体器件的示意性结构作为对本发明实施例的限定。
本发明实施例提供的半导体器件，一方面增大了半导体器件的散热面积，既能够加快热量的散发，降低半导体器件的内部温度，提高半导体器件内部温度分布的均匀性；另一方面能够改善半导体器件的宽长比，降低后续工艺难度(如切割和封装等)，提高半导体器件成品率，并且在保证半导体器件性能和可靠性的基础上可以更进一步增大器件尺寸，提高输出功率。
实施例三
图6A-图6E示出了本发明实施例三提供的半导体器件的俯视示意图，本发明实施例三以上述实施例为基础，下面结合图6A-图6E对本发明的实施例三进行描述。
请参见图6A，在图6A中，所述半导体器件D3的有源区包括多个有源区单元(如：a1、a2、a3和a4)，每个有源区单元内包括源极11、栅极13和漏极12，所述源极11、栅极13和漏极12在所述有源区单元内形成局部叉指状结构，任意相邻的两个有源区单元在半导体器件的长度方向上及宽度方向上均不交叠，具体为任意相邻的两个有源区单元在半导体器件的长度方向完全错开，在所述半导体器件的宽度方向上部分错开(如：a1和a2)，这样处理的好处在于，能够减小相邻两个有源区单元在半导体器件宽度方向上的距离，从而在半导体器件产生的热量不是非常大的情况下，无源区b的面积可以稍微小一些，使得半导体器件有源区的面积大于无源区b的面积，从而节省整个半导体器件面积，提高整个晶圆材料的产量。
请参见图6B，在图6B中，所述半导体器件D3的有源区内任意相邻两个 有源区单元在所述半导体器件的长度方向上交叠，任意相邻两个有源区单元在所述半导体器件的宽度方向上交叠(如：a1和a2)，其中一个有源区单元中的源极11与另一个有源区单元中的源极11对应交叠在一起。图6B也能够减小半导体器件无源区b的面积，从而能够提高晶圆材料的产量。
请参见图6C，在图6C中，所述半导体器件D3的有源区内任意两个相邻有源区单元在所述半导体器件的宽度方向上及长度方向上均不交叠，具体为任意相邻的两个有源区单元在半导体器件的宽度方向完全错开，任意两个相邻有源区单元在所述半导体器件的长度方向上部分错开(如：a1和a2)。
请参见图6D，图6D所示的半导体器件D3中任意两个相邻有源区单元在所述半导体器件的宽度方向上及长度方向上均不交叠，具体为任意相邻的两个有源区单元在半导体器件的宽度方向上完全错开，任意两个相邻有源区单元在所述半导体器件的长度方向也完全错开(如：a1和a2)，使得半导体器件无源区b的面积大于有源区的面积。如果半导体器件产生的热量非常大，可以将无源区b面积进一步增大，能够将有源区内产生的热量及时横向传导至周围没有发热源的无源区中，加快了热量的散发，降低了半导体器件内部温度。
需要说明的是，所述半导体器件的多个有源区单元可以是上述图6A-图6D中所示半导体器件中的相邻两个有源区单元的任意组合，本实施例只是一个优选实施例，并不用于限制本发明。
还需要说明的是，在本发明实施例中，在半导体器件的长度方向和宽度方向上有源区单元的数目不做限定，例如：如图6E所示，多个有源区单元(a1、a2、a3、a4和a5)在半导体器件D3的宽度方向上交错排列，在所述半导体器件D3的长度方向，多个有源区单元交错排列，且多个有源区单元分成3列排列，使得所述半导体器件D3的长度更长，在半导体器件D3的长度方向上引入 的无源区b域面积更大，散热效果更好，半导体器件内部温度均匀性进一步提高，半导体器件宽长比进一步减小。
本发明实施例提供的半导体器件，通过分别改变多个有源区单元在半导体器件长度方向上以及宽度方向上交错排列的方式，能够灵活改变有源区的面积和无源区的面积，且能够灵活改变半导体器件的宽长比。
实施例四
图7示出了本发明实施例四提供的半导体器件制作方法的流程图，该半导体器件的制作方法用于制作本发明实施例中所述的半导体器件，所述半导体器件的制作方法详述如下：
步骤S1、形成有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件上的长度方向上交错排列，以及所述多个有源区单元在所述半导体器件的宽度方向上交错排列。
所述有源区下方存在二维电子气、电子或空穴，是半导体器件的工作区域，所述无源区下方通过台面刻蚀工艺(MESA etch)、离子注入工艺和/或氧化隔离工艺后消除掉了位于其下的二维电子气、电子或空穴，不是半导体器件的内部工作区域，可以在无源区布置一些走线，以便将位于有源区的元件连接起来，从而形成一个大的半导体器件。
所述有源区的面积可以等于所述无源区的面积，所述有源区的面积也可以小于所述无源区的面积，所述有源区的面积还可以大于所述无源区的面积。
可以利用台面刻蚀工艺、离子注入工艺和/或氧化隔离工艺形成所述半导体器件的有源区和无源区。
优选的，所述半导体器件的制作方法还可以包括：
步骤S2、在所述半导体器件的正面的有源区内形成源极、栅极和漏极，所述有源区内的源极、栅极和漏极分布在所述有源区的有源区单元内。
步骤S3、在所述半导体器件的正面的无源区内形成漏极互联金属、栅极互联金属和/或源极互联金属。
在本步骤中，所述有源区内的漏极通过位于无源区内的漏极互联金属连接在一起，所述有源区内的栅极通过位于无源区内的栅极互连金属连接在一起。
进一步的，还可以在所述漏极互联金属或所述栅极互联线上形成引线PAD，以通过所述引线PAD将信号输入到所述半导体器件中。
进一步的，还可以在所述半导体器件背面形成接地电极。
进一步的，在无源区内形成源极互联金属，每一个源极通过源极互联金属连接至无源区，在所述源极互联金属和所述接地电极之间形成贯穿所述半导体器件的第一通孔，每个所述源极通过所述源极互联金属和所述第一通孔与所述接地电极电性连接。
或者，可以在所述半导体器件的有源区内的源极和所述接地电极之间形成贯穿所述半导体器件的第二通孔，从而将所述源极通过所述第二通孔与所述接地电极电性连接。
或者，可以在无源区内形成空气桥，所述空气桥跨接在所述栅极互连金属的上方，所述源极通过所述空气桥、所述源级互联金属和所述第一通孔与所述接地电极电性连接。
本发明实施例提供的半导体器件的制作方法，通过在半导体器件上形成有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件的长度方向上及宽度方向上交错排列，一方面增加了半导体器件的整体长度，增大了半导体器件的散热面积，由于每个局部有源区单元内产生的 热量较小，并且可以及时通过周围的无源区散发出去，从而加快了热量的散发，降低了半导体器件的内部温度，使得半导体器件的内部温度分布均匀，另一方面增加了半导体器件的整体长度，而半导体器件的宽度没有增加，从而减小了整个半导体器件的宽长比，降低了后续工艺难度(如切割和封装等)，提高了器件成品率，改善了宽长比增大对器件性能的影响。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
本发明公开了一种半导体器件及其制作方法，所述半导体器件包括有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件的长度方向上交错排列，所述多个有源区单元在所述半导体器件的宽度方向上交错排列。本发明增加了半导体器件的整体长度，增大了半导体器件的散热面积，加快了热量的散发，使得半导体器件的内部温度分布均匀；减小了整个半导体器件的宽长比，减轻了宽长比增大对器件性能的影响，并且还能降低后续工艺难度。

Claims (10)

  1. 一种半导体器件，其特征在于，所述半导体器件包括：
    有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件的长度方向上交错排列，以及所述多个有源区单元在所述半导体器件的宽度方向上交错排列。
  2. 根据权利要求1所述的半导体器件，其特征在于，任意两个相邻的有源区单元在所述半导体器件的长度方向上交叠或不交叠，以及任意两个相邻的有源区单元在所述半导体器件的宽度方向上交叠或不交叠。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，
    所述半导体器件的正面包括位于有源区内的源级、栅极和漏极，所述有源区内的源极、栅极和漏极分布在所述有源区的有源区单元内；还包括位于无源区内的漏级互联金属、栅极互联金属和/或源级互联金属。
  4. 根据权利要求3所述的半导体器件，其特征在于，
    所述有源区内的漏极通过位于无源区内的漏极互联金属连接在一起，所述有源区内的栅极通过位于无源区内的栅极互连金属连接在一起。
  5. 根据权利要求3所述的半导体器件，其特征在于，
    所述半导体器件的背面设置有接地电极；
    所述半导体器件还包括：位于所述源级互联金属和所述接地电极间的贯穿所述半导体器件的第一通孔，和/或位于所述源级和所述接地电极间的贯穿所述半导体器件的第二通孔；
    每个所述源极通过所述源极互联金属和所述第一通孔与所述接地电极电性连接；或者
    所述源极通过所述第二通孔与所述接地电极电性连接；或者
    所述源极通过空气桥与源极互联金属连接在一起，所述空气桥跨接在所述栅极互连金属上方，所述源极通过所述空气桥、所述源级互联金属和所述第一通孔与所述接地电极电性连接。
  6. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件的材料为氮化镓、铝镓氮、铟镓氮、铝铟镓氮、砷化镓、碳化硅、金刚石、蓝宝石或硅中的一种或多种任意组合。
  7. 一种半导体器件的制作方法，其特征在于，所述方法包括：
    形成有源区和无源区，所述有源区包括多个有源区单元，所述多个有源区单元在所述半导体器件上的长度方向上交错排列，以及所述多个有源区单元在所述半导体器件的宽度方向上交错排列。
  8. 根据权利要求7所述的半导体器件的制作方法，其特征在于，所述方法还包括：
    在所述半导体器件的正面的有源区内形成源极、栅极和漏极，所述有源区内的源极、栅极和漏极分布在所述有源区的有源区单元内；
    在所述半导体器件的正面的无源区内形成漏极互联金属、栅极互联金属和/或源极互联金属。
  9. 根据权利要求8所述的半导体器件的制作方法，其特征在于，
    所述有源区内的漏极通过位于无源区内的漏极互联金属连接在一起，所述有源区内的栅极通过位于无源区内的栅极互连金属连接在一起。
  10. 根据权利要求8所述的半导体器件的制作方法，其特征在于，利用台面刻蚀工艺、离子注入工艺和/或氧化隔离工艺形成所述半导体器件的有源区和无源区。
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