WO2008114317A1 - 半導体メモリ - Google Patents

半導体メモリ Download PDF

Info

Publication number
WO2008114317A1
WO2008114317A1 PCT/JP2007/000258 JP2007000258W WO2008114317A1 WO 2008114317 A1 WO2008114317 A1 WO 2008114317A1 JP 2007000258 W JP2007000258 W JP 2007000258W WO 2008114317 A1 WO2008114317 A1 WO 2008114317A1
Authority
WO
WIPO (PCT)
Prior art keywords
dmc2
dmc1
memory cells
arranged around
prevented
Prior art date
Application number
PCT/JP2007/000258
Other languages
English (en)
French (fr)
Inventor
Koji Shimosako
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to KR1020097015127A priority Critical patent/KR101098706B1/ko
Priority to JP2009504910A priority patent/JP5083309B2/ja
Priority to PCT/JP2007/000258 priority patent/WO2008114317A1/ja
Publication of WO2008114317A1 publication Critical patent/WO2008114317A1/ja
Priority to US12/560,170 priority patent/US7978555B2/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　ダミーメモリセルＤＭＣ１、ＤＭＣ２は、マトリックスの外周部に位置するリアルメモリセルＭＣの外側に配置される。第１コンタクトは、半導体基板上に積層される２つの配線層間を接続し、各メモリセルＭＣ、ＤＭＣ１、ＤＭＣ２の周囲に配置され、隣接するメモリセルＭＣ、ＤＭＣ１、ＤＭＣ２に共有される。ダミーメモリセルＤＭＣ１、ＤＭＣ２に配置される第１コンタクトの数は、リアルメモリセルＭＣに配置される第１コンタクトの数より少なく設定される。このため、製造条件のばらつきによりウエル領域が正常に形成されない場合にも、ダミーメモリセルＤＭＣ１、ＤＭＣ２に異常な電源電流が流れることを防止でき、ラッチアップが発生することを防止できる。
PCT/JP2007/000258 2007-03-19 2007-03-19 半導体メモリ WO2008114317A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020097015127A KR101098706B1 (ko) 2007-03-19 2007-03-19 반도체 메모리
JP2009504910A JP5083309B2 (ja) 2007-03-19 2007-03-19 半導体メモリ
PCT/JP2007/000258 WO2008114317A1 (ja) 2007-03-19 2007-03-19 半導体メモリ
US12/560,170 US7978555B2 (en) 2007-03-19 2009-09-15 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000258 WO2008114317A1 (ja) 2007-03-19 2007-03-19 半導体メモリ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/560,170 Continuation US7978555B2 (en) 2007-03-19 2009-09-15 Semiconductor memory

Publications (1)

Publication Number Publication Date
WO2008114317A1 true WO2008114317A1 (ja) 2008-09-25

Family

ID=39765438

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000258 WO2008114317A1 (ja) 2007-03-19 2007-03-19 半導体メモリ

Country Status (4)

Country Link
US (1) US7978555B2 (ja)
JP (1) JP5083309B2 (ja)
KR (1) KR101098706B1 (ja)
WO (1) WO2008114317A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164864A (ja) * 2011-02-08 2012-08-30 Rohm Co Ltd 半導体記憶装置
WO2014141485A1 (ja) * 2013-03-15 2014-09-18 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置の製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110146619B (zh) * 2019-06-11 2021-08-24 无锡微色谱生物科技有限公司 果蔬中四种杀菌剂的高通量检测方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10150163A (ja) * 1996-11-19 1998-06-02 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JP2000031306A (ja) * 1998-06-18 2000-01-28 Samsung Electron Co Ltd 不揮発性メモリ装置
JP2003323792A (ja) * 2002-04-30 2003-11-14 Mitsubishi Electric Corp 半導体記憶装置
JP2004071118A (ja) * 2002-08-09 2004-03-04 Renesas Technology Corp スタティック型半導体記憶装置
JP2005333084A (ja) * 2004-05-21 2005-12-02 Nec Electronics Corp 半導体記憶装置
JP2006209837A (ja) * 2005-01-26 2006-08-10 Nec Electronics Corp スタティック半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214559A (ja) 1985-03-20 1986-09-24 Hitachi Ltd 半導体集積回路装置
JP3169920B2 (ja) * 1998-12-22 2001-05-28 日本電気アイシーマイコンシステム株式会社 半導体記憶装置、その装置製造方法
DE19907921C1 (de) * 1999-02-24 2000-09-28 Siemens Ag Halbleiterspeicheranordnung mit Dummy-Bauelementen auf durchgehenden Diffusionsgebieten
CA2299991A1 (en) 2000-03-03 2001-09-03 Mosaid Technologies Incorporated A memory cell for embedded memories
KR100388223B1 (ko) 2000-11-08 2003-06-19 주식회사 하이닉스반도체 반도체장치의 비트라인 콘택 레이아웃

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10150163A (ja) * 1996-11-19 1998-06-02 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JP2000031306A (ja) * 1998-06-18 2000-01-28 Samsung Electron Co Ltd 不揮発性メモリ装置
JP2003323792A (ja) * 2002-04-30 2003-11-14 Mitsubishi Electric Corp 半導体記憶装置
JP2004071118A (ja) * 2002-08-09 2004-03-04 Renesas Technology Corp スタティック型半導体記憶装置
JP2005333084A (ja) * 2004-05-21 2005-12-02 Nec Electronics Corp 半導体記憶装置
JP2006209837A (ja) * 2005-01-26 2006-08-10 Nec Electronics Corp スタティック半導体記憶装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164864A (ja) * 2011-02-08 2012-08-30 Rohm Co Ltd 半導体記憶装置
WO2014141485A1 (ja) * 2013-03-15 2014-09-18 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置の製造方法
US9111794B2 (en) 2013-03-15 2015-08-18 Unisantis Electronics Singapore Pte. Ltd. Method for producing a semiconductor device having SGTS

Also Published As

Publication number Publication date
KR101098706B1 (ko) 2011-12-23
JP5083309B2 (ja) 2012-11-28
US20100008120A1 (en) 2010-01-14
US7978555B2 (en) 2011-07-12
JPWO2008114317A1 (ja) 2010-06-24
KR20090104042A (ko) 2009-10-05

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