FR2967810B1 - Procede de fabrication d'un circuit integre protege contre l'ingenierie inverse - Google Patents
Procede de fabrication d'un circuit integre protege contre l'ingenierie inverseInfo
- Publication number
- FR2967810B1 FR2967810B1 FR1004497A FR1004497A FR2967810B1 FR 2967810 B1 FR2967810 B1 FR 2967810B1 FR 1004497 A FR1004497 A FR 1004497A FR 1004497 A FR1004497 A FR 1004497A FR 2967810 B1 FR2967810 B1 FR 2967810B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- layout
- cell
- reverse engineering
- against reverse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1004497A FR2967810B1 (fr) | 2010-11-18 | 2010-11-18 | Procede de fabrication d'un circuit integre protege contre l'ingenierie inverse |
US13/299,267 US8434046B2 (en) | 2010-11-18 | 2011-11-17 | Method of fabricating an integrated circuit protected against reverse engineering |
CN201110379373.0A CN102467603B (zh) | 2010-11-18 | 2011-11-18 | 制造受保护免于反向工程的集成电路的方法 |
CN2011204716099U CN202352676U (zh) | 2010-11-18 | 2011-11-18 | 在半导体芯片上的集成电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1004497A FR2967810B1 (fr) | 2010-11-18 | 2010-11-18 | Procede de fabrication d'un circuit integre protege contre l'ingenierie inverse |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2967810A1 FR2967810A1 (fr) | 2012-05-25 |
FR2967810B1 true FR2967810B1 (fr) | 2012-12-21 |
Family
ID=44280736
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1004497A Expired - Fee Related FR2967810B1 (fr) | 2010-11-18 | 2010-11-18 | Procede de fabrication d'un circuit integre protege contre l'ingenierie inverse |
Country Status (3)
Country | Link |
---|---|
US (1) | US8434046B2 (fr) |
CN (2) | CN202352676U (fr) |
FR (1) | FR2967810B1 (fr) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8856704B2 (en) * | 2010-11-22 | 2014-10-07 | Industry-University Cooperation Foundation Hanyang University | Layout library of flip-flop circuit |
US9218511B2 (en) | 2011-06-07 | 2015-12-22 | Verisiti, Inc. | Semiconductor device having features to prevent reverse engineering |
US8975748B1 (en) | 2011-06-07 | 2015-03-10 | Secure Silicon Layer, Inc. | Semiconductor device having features to prevent reverse engineering |
US9287879B2 (en) | 2011-06-07 | 2016-03-15 | Verisiti, Inc. | Semiconductor device having features to prevent reverse engineering |
US8539409B1 (en) * | 2011-07-08 | 2013-09-17 | Lattice Semiconductor Corporation | Simultaneous development of complementary IC families |
US9318607B2 (en) * | 2013-07-12 | 2016-04-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9831230B2 (en) | 2013-08-13 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell layout, semiconductor device having engineering change order (ECO) cells and method |
US9337156B2 (en) * | 2014-04-09 | 2016-05-10 | Infineon Technologies Ag | Method for manufacturing a digital circuit and digital circuit |
US9431353B2 (en) * | 2014-04-09 | 2016-08-30 | Infineon Technologies Ag | Method for manufacturing a digital circuit and digital circuit |
US9431398B2 (en) | 2014-04-28 | 2016-08-30 | Infineon Technologies Ag | Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering |
US9984191B2 (en) | 2014-08-29 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company | Cell layout and structure |
US10445453B2 (en) * | 2015-04-08 | 2019-10-15 | Mediatek Inc. | Cell layout utilizing boundary cell with mixed poly pitch within integrated circuit |
US9496872B1 (en) * | 2015-07-17 | 2016-11-15 | Infineon Technologies Ag | Method for manufacturing a digital circuit and digital circuit |
US9548737B1 (en) | 2015-07-17 | 2017-01-17 | Infineon Technologies Ag | Method for manufacturing a digital circuit and digital circuit |
US10521538B2 (en) * | 2016-04-27 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and system for integrated circuit design with on-chip variation and spatial correlation |
GB201609781D0 (en) * | 2016-06-03 | 2016-07-20 | Irdeto Bv | Secured chip |
CN110895647A (zh) * | 2018-08-22 | 2020-03-20 | 北京芯愿景软件技术股份有限公司 | 一种增加集成电路逆向工程难度的方法及芯片 |
DE102019123555B4 (de) | 2019-09-03 | 2022-12-01 | Infineon Technologies Ag | Physisch obfuskierter schaltkreis |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5764533A (en) * | 1995-08-01 | 1998-06-09 | Sun Microsystems, Inc. | Apparatus and methods for generating cell layouts |
US5783846A (en) * | 1995-09-22 | 1998-07-21 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
US6031982A (en) * | 1996-11-15 | 2000-02-29 | Samsung Electronics Co., Ltd. | Layout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networks |
CN1151552C (zh) * | 1997-03-11 | 2004-05-26 | 三菱电机株式会社 | 利用单元库方式进行布局设计的半导体集成电路装置 |
US7360193B1 (en) * | 2004-09-21 | 2008-04-15 | Golden Gate Technology, Inc. | Method for circuit block placement and circuit block arrangement based on switching activity |
US7966596B2 (en) * | 2008-08-27 | 2011-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Place-and-route layout method with same footprint cells |
US8418091B2 (en) * | 2009-02-24 | 2013-04-09 | Syphermedia International, Inc. | Method and apparatus for camouflaging a standard cell based integrated circuit |
-
2010
- 2010-11-18 FR FR1004497A patent/FR2967810B1/fr not_active Expired - Fee Related
-
2011
- 2011-11-17 US US13/299,267 patent/US8434046B2/en active Active
- 2011-11-18 CN CN2011204716099U patent/CN202352676U/zh not_active Expired - Lifetime
- 2011-11-18 CN CN201110379373.0A patent/CN102467603B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
FR2967810A1 (fr) | 2012-05-25 |
CN202352676U (zh) | 2012-07-25 |
CN102467603A (zh) | 2012-05-23 |
US20120131533A1 (en) | 2012-05-24 |
US8434046B2 (en) | 2013-04-30 |
CN102467603B (zh) | 2016-06-29 |
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Legal Events
Date | Code | Title | Description |
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PLFP | Fee payment |
Year of fee payment: 6 |
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PLFP | Fee payment |
Year of fee payment: 7 |
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PLFP | Fee payment |
Year of fee payment: 8 |
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PLFP | Fee payment |
Year of fee payment: 9 |
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PLFP | Fee payment |
Year of fee payment: 10 |
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PLFP | Fee payment |
Year of fee payment: 11 |
|
ST | Notification of lapse |
Effective date: 20220705 |