CN104620383B - 反熔丝器件 - Google Patents
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Abstract
电可编程栅极氧化物反熔丝器件包括具有反熔丝链接的反熔丝孔,该反熔丝链接包括之间有电介质层的诸金属和/或半导体电极。电介质层可以是层间电介质(ILD)、金属间电介质(IMD)或蚀刻停止层。反熔丝器件可以包括半导体基板,该半导体基板具有设置在该基板表面上的导电栅极(例如,高K金属栅极),以及设置在该导电栅极上的电介质层。堆叠触点被设置在电介质层上,并且栅极触点被设置在栅极的暴露部分上。
Description
技术领域
本公开一般涉及反熔丝器件。更具体地,本公开涉及电可编程反熔丝器件,并且还涉及制造该电可编程反熔丝器件的方法。
背景
可编程链接是为了激活或停用所选择的电节点而在所选择的电节点处被断开或创建的电互连。可以由用户在集成电路被制造并封装之后执行对所选择的电互连的激活/停用。所激活和停用的电互连的组合代表对用户希望存储的数据进行表示的数字位模式。
近年来,已经开发出称作反熔丝链接的另一类可编程链接用于在集成电路应用中使用。替代如可熔丝链接一样导致开路的编程机制,反熔丝电路中的编程机制创建短路或相对低阻抗的链接。反熔丝链接由在导电材料之间具有电介质或绝缘材料的两个导体和/或半导体材料构成。在编程期间,通过施加预定电压,在导电材料之间所选择的点处的电介质被击穿,由此将导体或半导体材料电连接到一起。
反熔丝器件可以被集成到具有围绕超薄电介质(诸如栅极氧化物)构成的数据存储元件的半导体存储器单元中。通过对电介质施压到击穿(软击穿或硬击穿)以设置存储器单元的漏电流水平可以实现反熔丝器件。通过对由单元汲取的电流进行感测来读取存储器单元。
对安全计算渐增的需求正驱使使用反熔丝器件来提供只读存储器单元的近期增长。具体地,数字安全应用例如指定大量经加密的、可编程只读存储器单元。遗憾地,标准的反熔丝制造一般指定在反熔丝形成期间或之后使用数个掩模、沉积或刻蚀步骤,由此增加了集成电路的制造复杂度和成本。
概述
根据本公开的一个方面,描述了栅极氧化物反熔丝器件。栅极氧化物反熔丝器件包括半导体基板,该半导体基板具有设置在基板表面上的栅极。栅极氧化物反熔丝器件还可以包括设置在栅极上的电介质层。栅极氧化物反熔丝器件还可以包括设置在电介质层上的堆叠触点。栅极氧化物反熔丝器件还可以包括设置在栅极上的栅极触点。
根据本公开的另一个方面,描述了栅极氧化物反熔丝器件制造方法。该方法包括在半导体基板上形成导电栅极。该方法还可以包括在导电栅极上沉积电介质层。该方法进一步包括暴露导电栅极的一部分。该方法还可以包括在导电栅极的被暴露的部分上制造栅极触点。该方法进一步包括在电介质层上形成堆叠触点。
根据本公开的一个方面,描述了栅极氧化物反熔丝器件。栅极氧化物反熔丝器件包括半导体基板。栅极氧化物反熔丝器件还可以包括设置在基板表面上的导电栅极。栅极氧化物反熔丝器件还可以包括设置在导电栅极上用于绝缘的装置。栅极氧化物反熔丝器件可以进一步包括设置在导电栅极上用于导电的第一装置。该栅极氧化物反熔丝器件还可以包括设置在绝缘装置上用于导电的第二装置。
这已较宽泛地勾勒出本公开的特征和技术优势以便下面的详细描述可以被更好地理解。本发明的其他特征和优点将在下文描述。本领域技术人员应该领会,本发明可容易地被用作改动或设计用于实施与本发明相同的目的的其他结构的基础。本领域技术人员还应认识到,这样的等效构造并不脱离所附权利要求中所阐述的本发明的教导。被认为是本发明的特性的新颖特征在其组织和操作方法两方面连同进一步的目的和优点在结合附图来考虑以下描述时将被更好地理解。然而要清楚理解的是,提供每一幅附图均仅用于解说和描述目的,且无意作为对本发明的限定的定义。
附图简述
本公开的特征、本质和优点将因以下结合附图阐述的具体描述而变得更加明显。
图1解说了根据从其实现反熔丝器件的当前工艺技术制造的逻辑结构。
图2是用与用于形成图1的逻辑结构的工艺相兼容的工艺来制造的反熔丝配置的示例。
图3是根据本公开的一个方面的反熔丝器件的示例。
图4是诸如图3中所示的反熔丝器件的示例性图案的俯视图。
图5解说了根据本公开一方面的用于实现反熔丝器件的方法。
图6示出其中可有利地采用本公开的实施例的示例性无线通信系统。
图7是解说根据本公开一方面的用于半导体组件的电路、版图以及逻辑设计的设计工作站的框图。
详细描述
以下结合附图阐述的详细描述旨在作为各种配置的描述,而无意表示可实践本文中所描述的概念的仅有的配置。本详细描述包括具体细节以便提供对各种概念的透彻理解。然而,对于本领域技术人员将显而易见的是,没有这些具体细节也可实践这些概念。在一些实例中,以框图形式示出众所周知的结构和组件以避免湮没此类概念。
本公开的一个方面描述了电可编程栅极氧化物反熔丝器件,以及制造该反熔丝器件的方法。反熔丝器件可以包括具有反熔丝链接的反熔丝孔,该反熔丝链接包括之间有蚀刻停止层的诸金属和/或半导体电极。蚀刻停止层可以是被实现成两个电极间的电介质层的层间电介质(ILD)或金属间电介质(IMD)。在一个配置中,反熔丝器件包括半导体基板,该半导体基板具有设置在该基板表面上的导电栅极(例如,高K金属栅极),以及设置在该导电栅极上的电介质层。堆叠触点被设置在电介质层上,并且栅极触点被设置在栅极的暴露部分上。支持高K金属栅极(HKMG)实现的当前工艺技术使得能够制造反熔丝器件而无需附加的掩模或附加的层。
图1解说可以用现有工艺技术实现的逻辑结构100。逻辑结构100制造在其中可以形成有源区的半导体基板102上。源极区104和漏极区106可以形成在有源区中。导电栅极(例如,高K金属栅极(HKMG))108以及一组有源(氧化物扩散(OD))触点110和112形成在半导体基板102上。多晶硅(栅极)触点114直接耦合至导电栅极108。有源触点110和112分别耦合至源极 区104和漏极区106。一组堆叠触点116和118分别耦合至一组有源触点110和112。
如图1中所示,该组堆叠触点116和118分别形成在该组有源触点110和112上而没有居间层。逻辑结构100还包括用于耦合至电器件或电路(诸如导电堆叠的其他层)的导电层(例如,m1金属层)120、122和124。导电层120、122和124可被配置成接收被指定为VSS和VDD的电源电压。导电层120和122可以分别经由通孔126和128分别耦合至堆叠触点116和118。导电层124可以经由通孔130耦合至栅极(例如,多晶硅)触点114。
蚀刻停止层(例如,光阻层)132可以设置在逻辑结构100中。蚀刻停止层132可以包括形成在导电层108上的光阻图案以实现栅极图案。可以通过使用光阻图案作为蚀刻掩模来蚀刻导电栅极108,来形成设置在半导体基板102的有源区上的栅极图案。在所得到的配置中,因为蚀刻停止层132在制造导电栅极的同时被蚀刻掉,故而在导电栅极108(例如,高K金属栅极)和栅极触点114之间没有蚀刻停止层132。另外,因为在有源触点110和112上沉积触点116和118之前蚀刻停止层132的一部分被蚀刻掉,故而蚀刻停止层132不会将堆叠触点116和118与有源触点110和112分开。
使用用于制造逻辑结构100的掩模和工艺可以无附加成本地实现反熔丝器件。反熔丝器件可以包括与导电元件(例如,导电栅极108和堆叠触点116/118)之间的电介质材料的反熔丝链接。在编程期间,导电元件之间的电介质材料被从导电层(例如,导电层120和/或122)施加到堆叠触点116和/或118的预定编程电压所衍生出的电流击穿。
图2是基于创建图1的逻辑结构的工艺的反熔丝配置150的示例。该反熔丝配置150包括来自图1的逻辑结构100的栅极(例如,多晶硅)触点114、堆叠触点116、蚀刻停止层132和导电栅极108。在图2所示的配置中,蚀刻停止层132充当堆叠触点116和导电栅极108之间的电介质材料(例如,氮化层)。例如,电介质132可以包括栅极电介质材料(诸如层间电介质或金属间电介质)。在一个配置中,蚀刻停止层132可具有约10埃的厚度。栅极触点114可以直接形成在导电栅极108上。另外,堆叠触点116邻近栅极触点114。
如图2中所示,堆叠触点116在导电栅极108上的区域内被设置在蚀刻停 止层132上,从而使蚀刻停止层132设置在两个电极(堆叠触点(上电极)116和导电栅极(下电极)108)之间以形成反熔丝配置150。导电栅极108在半导体基板102上。栅极触点114可以耦合至导电栅极108以促成到外部电器件(诸如反相器或存储器单元)的连接。例如,栅极触点114可以配置成读取反熔丝器件的输出。
通过在栅极触点114上以及在导电栅极108和堆叠触点116之间施加不同的电压,来编程反熔丝器件。电压应当足以击穿电介质层132以致导电栅极108和堆叠触点116电连通。也即,电流密度在反熔丝器件的小区域内耗散功率,这击穿了导电栅极108和堆叠触点116之间的电介质层132。电介质层132的击穿形成堆叠触点(上电极)116和导电栅极108(下电极)之间的导电链接。
在图3中解说了根据本公开的一个方面的图2的反熔丝配置中的更多的元件。代表性地,反熔丝器件300包括作为下电极的导电栅极(例如,HKMG)108、栅极触点114、通孔126和130、电介质层(例如,蚀刻停止层)132以及作为上电极的堆叠触点116。栅极触点114和堆叠触点116可以被耦合至其他电子器件(例如,电压源VSS、VDD、导电元件,等等)。如图3中所示,栅极触点114和堆叠触点116可以通过通孔126和130从导电栅极108接收电压或向其传送电压。在本公开的一个方面中,导电栅极108被实现为阴极,而堆叠触点116被实现为反熔丝器件300的阳极。相反地,导电栅极108或者堆叠触点116可以被实现为阳极或阴极。
可以使用现有制造工艺形成导电栅极108、栅极触点114、通孔126和130、堆叠触点116和电介质层132而无附加的掩模或附加的层。例如,反熔丝器件的一些方面可以使用惯常的化学气相沉积(CVD)技术、等离子体增强CVD(PECVD)技术等来形成。在一个配置中,反熔丝器件300被实现在基板102的浅沟槽隔离区301的顶上,以减少由电流泄漏引起的半导体基板102中的有源器件(未示出)的击穿。
在图4中解说了图3的反熔丝器件的示例性版图。代表性地,反熔丝图案可以被实现在堆叠触点116和导电栅极108的包括左上部(TL)、左下部(BL)、右上部(TR)和右下部(BR)的重叠区域中。版图包括全部都在基板102的浅沟槽隔离区301上的堆叠触点(上电极)116和导电栅极108(下电极), 以及通孔126、130。尽管给配置被示出为设置在浅沟槽隔离区上,但是本公开不受限于此。表1中解说了堆叠触点116和导电栅极108在(TL)、左下部(BL)、右上部(TR)、右下部(BR)位置处的示例性宽度。
图案 | 导电栅极宽度 | 堆叠触点宽度 |
TL | 36 | 40 |
TR | 70 | 40 |
BL | 36 | 50 |
BR | 70 | 50 |
表1
图5解说了根据本公开一个方面的用于实现反熔丝器件的方法500。该方法包括在框502在半导体基板的表面上沉积栅极层。在框504,栅极层被图案化以形成导电栅极。在图3中所示的配置中,导电栅极108是在半导体基板102中的浅沟槽隔离区301上形成的高k金属栅极(HKMG)。在框506,在导电栅极上沉积电介质层。例如,如图3中所示,电介质层132形成在导电栅极108上。
在框508,例如通过蚀刻或某个其他金属去除处理来暴露导电栅极108的一部分。在框510,第一接触膜被沉积在导电栅极108被暴露的部分上。在框512,第一接触膜被图案化以形成栅极触点。例如,图3解说直接形成在导电栅极108上的栅极触点114。在框514,第二接触膜被沉积在电介质层上,并且在框516,第二接触膜被图案化以形成堆叠触点。例如,如图3中所示,堆叠触点116被形成在电介质层132上并且与导电栅极108分开。在此配置中,堆叠触点116作为上电极操作而导电栅极108作为下电极操作,其中电介质层132将上电极(堆叠触点116)和下电极(导电栅极108)分开。
在一个配置中,器件包括设置在导电栅极上用于绝缘的装置。在本公开的一个方面,该绝缘装置可以是被配置成执行由绝缘装置所述的功能的电介质层132。该器件还可以包括设置在导电栅极上用于导电的第一装置。在本公开的一个方面,该第一导电装置可以是配置成执行由第一导电装置所述的功能的栅 极触点114。该器件还可以包括设置在绝缘装置上用于导电的第二装置。在本公开的一个方面,该第二导电装置可以是配置成执行由第二导电装置所述的功能的堆叠触点116和/或堆叠触点118。在另一方面,前述装置可以是配置成执行由前述装置所述的功能的任何器件。
图6示出其中可有利地采用本公开的实施例的示例性无线通信系统。出于解说目的,图6示出了三个远程单元620、630和650以及两个基站640。将认识到,无线通信系统可具有多得多的远程单元和基站。远程单元620、630和650包括反熔丝器件625A、625B、625C。图6示出从基站640到远程单元620、630、和650的前向链路信号680,以及从远程单元620、630、和650到基站640的反向链路信号690。
在图6中,远程单元620被示为移动电话,远程单元630被示为便携式计算机,而远程单元650被示为无线本地环路系统中的位置固定的远程单元。例如,远程单元可以是蜂窝电话、手持式个人通信系统(PCS)单元、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、便携式数据单元(诸如个人数据助理)或者位置固定的数据单元(诸如仪表读数装备)。尽管图6示出了可采用根据本公开的教导的反熔丝器件625A、625B、625C的远程单元,但本公开不限于所示出的这些示例性单元。例如,根据本公开的诸方面的反熔丝器件可被合适地用在任何设备中。
图7是解说用于半导体组件(诸如以上公开的反熔丝器件)的电路、版图以及逻辑设计的设计工作站的框图。设计工作站700包括硬盘701,该硬盘1101包含操作系统软件、支持文件以及设计软件,诸如Cadence或OrCAD。设计工作站700还包括促成对电路710或半导体组件712(诸如反熔丝器件)的设计的显示器702。提供存储介质704以用于有形地存储电路设计710或半导体组件712。电路设计710或半导体组件712可以文件格式(诸如GDSII或GERBER)存储在存储介质704上。存储介质704可以是CD-ROM、DVD、硬盘、闪存、或其他合适的设备。此外,设计工作站7800包括用于从存储介质703接受输入或将输出写入存储介质704的驱动装置703。
存储介质704上记录的数据可指定逻辑电路配置、用于光刻掩模的图案数据、或者用于串写工具(诸如电子束光刻)的掩模图案数据。该数据可进一步 包括与逻辑仿真相关联的逻辑验证数据,诸如时序图或网电路。在存储介质704上提供数据通过减少了用于设计半导体晶片的工艺数目来促成对电路设计710或半导体组件712的设计。
尽管已阐述了特定电路系统,但是本领域技术人员应当领会,并非所有所公开的电路系统都是实践所公开的实施例所必需的。此外,某些众所周知的电路未被描述,以便保持专注于本公开。
本文中所描述的方法体系取决于应用可藉由各种手段来实现。例如,这些方法体系可在硬件、固件、软件或其任何组合中实现。对于硬件实现,这些处理单元可以在一个或多个专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理器件(DSPD)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、处理器、控制器、微控制器、微处理器、电子器件、设计成执行本文中所描述功能的其他电子单元或其组合内实现。
对于固件和/或软件实现,这些方法体系可以用执行本文所描述功能的模块(例如,规程、函数等等)来实现。有形地体现指令的任何机器或计算机可读介质可用于实现本文中所描述的方法体系。例如,软件代码可被存储在存储器中并由处理器执行。当由处理器执行时,执行中的软件代码生成实现本文所呈现的教导的不同方面的各种方法体系和功能性的操作环境。存储器可以实现在处理器内部或处理器外部。如本文所使用的,术语存储器摂是指任何类型的长期、短期、易失性、非易失性、或其他存储器,且并不限于任何特定类型的存储器或特定数目的存储器、或记忆存储在其上的介质类型。
存储有定义本文所述方法体系和功能的软件代码的机器或计算机可读介质包括物理计算机存储介质。存储介质可以是能被计算机访问的任何可用介质。作为示例而非限制,这些计算机可读介质可包括RAM、ROM、EEPROM、CD-ROM或其它光盘存储、磁盘存储或其它磁存储设备、或可被用来存储指令或数据结构形式的期望程序代码且可被计算机访问的任何其它介质。如本文所用的盘(disk)和/或碟(disc)包括压缩碟(CD)、激光碟、光碟、数字多用碟(DVD)、软盘和蓝光碟,其中盘(disk)常常磁性地再现数据而碟(disc)用激光来光学地再现数据。上述的组合也应被包括在计算机可读介质的范围内。
除了存储在计算机可读介质上,指令和/或数据还可作为包括在通信装置中的传输介质上的信号来提供。例如,通信装置可包括具有指示指令和数据的信号的收发机。指令和数据被配置成致使一个或多个处理器实现权利要求中所述的功能。
尽管已详细描述了本教导及其优点,但是应当理解,能在本文中作出各种改变、替代和变更而不会脱离如由所附权利要求所定义的本教导的技术。而且,本申请的范围并非旨在被限定于说明书中所描述的过程、机器、制造、物质组成、装置、方法和步骤的特定方面。因为本领域普通技术人员将容易地从本公开领会到,根据本教导,可以利用现存或今后开发的与本文所描述的相应方面执行基本相同的功能或达成基本相同的结果的过程、机器、制造、物质组成、装置、方法或步骤。因此,所附权利要求旨在将这样的过程、机器、制造、物质组成、装置、方法或步骤包括在其范围内。
Claims (16)
1.一种栅极氧化物反熔丝器件,包括:
半导体基板;
在所述基板的表面上的栅极;
在所述栅极上的电介质层;
在所述电介质层的与所述栅极相对的表面上的堆叠触点,所述电介质层在所述堆叠触点和所述栅极之间;以及
在所述栅极上的栅极触点。
2.如权利要求1所述的栅极氧化物反熔丝器件,其特征在于,所述栅极包括高K金属栅极。
3.如权利要求2所述的栅极氧化物反熔丝器件,其特征在于,所述高K金属栅极设置在所述基板的浅沟槽隔离区上。
4.如权利要求1所述的栅极氧化物反熔丝器件,其特征在于,所述电介质层包括氮化硅。
5.如权利要求1所述的栅极氧化物反熔丝器件,其特征在于,进一步包括形成在所述堆叠触点上的通孔。
6.如权利要求1所述的栅极氧化物反熔丝器件,其特征在于,进一步包括形成在所述栅极触点上的通孔。
7.如权利要求1所述的栅极氧化物反熔丝器件,其特征在于,所述栅极氧化物反熔丝器件被集成到蜂窝电话、手持式个人通信系统(PCS)单元、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、便携式数据单元和/或固定位置数据单元中。
8.一种栅极氧化物反熔丝器件,包括:
半导体基板;
在所述半导体基板的表面上的导电栅极;
在所述导电栅极上用于绝缘的装置;
在所述绝缘装置的与所述导电栅极相对的表面上用于导电的第一装置,所述绝缘装置在用于导电的所述第一装置和所述导电栅极之间;以及
在所述导电栅极上用于导电的第二装置。
9.如权利要求8所述的栅极氧化物反熔丝器件,其特征在于,进一步包括形成在用于导电的所述第二装置上用于互连各层的装置。
10.如权利要求8所述的栅极氧化物反熔丝器件,其特征在于,进一步包括形成在用于导电的所述第一装置上用于互连各层的装置。
11.如权利要求8所述的栅极氧化物反熔丝器件,其特征在于,所述栅极氧化物反熔丝器件被集成到蜂窝电话、手持式个人通信系统(PCS)单元、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、便携式数据单元和/或固定位置数据单元中。
12.一种栅极氧化物反熔丝器件制造方法,包括:
在半导体基板的表面上形成导电栅极;
在所述导电栅极上直接沉积电介质层;
暴露所述导电栅极的一部分;
在所述电介质层的与所述导电栅极相对的表面上形成堆叠触点,所述电介质层在所述堆叠触点和所述导电栅极之间;以及
在所述导电栅极的被暴露部分上形成栅极触点。
13.如权利要求12所述的方法,其特征在于,形成导电栅极进一步包括在所述半导体基板的浅沟槽隔离区上形成导电栅极。
14.如权利要求12所述的方法,其特征在于,进一步包括在所述堆叠触点上形成通孔。
15.如权利要求12所述的方法,其特征在于,进一步包括在所述栅极触点上形成通孔。
16.如权利要求12所述的方法,其特征在于,进一步包括将所述栅极氧化物反熔丝器件集成到蜂窝电话、手持式个人通信系统(PCS)单元、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、便携式数据单元和/或固定位置数据单元中。
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Publication number | Priority date | Publication date | Assignee | Title |
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US9502424B2 (en) | 2012-06-29 | 2016-11-22 | Qualcomm Incorporated | Integrated circuit device featuring an antifuse and method of making same |
US9842802B2 (en) | 2012-06-29 | 2017-12-12 | Qualcomm Incorporated | Integrated circuit device featuring an antifuse and method of making same |
KR102212151B1 (ko) * | 2014-02-11 | 2021-02-04 | 인텔 코포레이션 | 안티퓨즈 구조, 안티퓨즈 비트 셀 구조, 안티퓨즈 구조를 제조하는 방법 및 모놀리식 안티퓨즈 비트 셀을 형성하는 방법 |
WO2015148944A1 (en) * | 2014-03-27 | 2015-10-01 | Qualcomm Incorporated | Integrated circuit device featuring an antifuse and method of making same |
US9496270B2 (en) | 2014-05-30 | 2016-11-15 | Qualcomm Incorporated | High density single-transistor antifuse memory cell |
WO2016209242A1 (en) * | 2015-06-25 | 2016-12-29 | Intel Corporation | Controlled modification of antifuse programming voltage |
US10332840B2 (en) * | 2017-03-21 | 2019-06-25 | Macronix International Co., Ltd. | Semiconductor device with physically unclonable function (PUF) and apparatus including the same |
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102160178A (zh) * | 2008-09-19 | 2011-08-17 | 株式会社半导体能源研究所 | 半导体器件 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823181A (en) | 1986-05-09 | 1989-04-18 | Actel Corporation | Programmable low impedance anti-fuse element |
US5550404A (en) | 1993-05-20 | 1996-08-27 | Actel Corporation | Electrically programmable antifuse having stair aperture |
US6069064A (en) | 1996-08-26 | 2000-05-30 | Micron Technology, Inc. | Method for forming a junctionless antifuse |
US6509624B1 (en) | 2000-09-29 | 2003-01-21 | International Business Machines Corporation | Semiconductor fuses and antifuses in vertical DRAMS |
US7087975B2 (en) * | 2000-12-28 | 2006-08-08 | Infineon Technologies Ag | Area efficient stacking of antifuses in semiconductor device |
US6683365B1 (en) | 2002-08-01 | 2004-01-27 | Micron Technology, Inc. | Edge intensive antifuse device structure |
KR100878496B1 (ko) | 2002-12-30 | 2009-01-13 | 주식회사 하이닉스반도체 | 반도체 장치 및 그 제조방법 |
KR100937647B1 (ko) | 2002-12-30 | 2010-01-19 | 동부일렉트로닉스 주식회사 | 프로그램이 가능한 커패시터 및 이의 제조 방법 |
US7323761B2 (en) | 2004-11-12 | 2008-01-29 | International Business Machines Corporation | Antifuse structure having an integrated heating element |
US20080029844A1 (en) * | 2006-08-03 | 2008-02-07 | Adkisson James W | Anti-fuse structure optionally integrated with guard ring structure |
JP2008227049A (ja) | 2007-03-12 | 2008-09-25 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7741697B2 (en) | 2007-04-17 | 2010-06-22 | Applied Intellectual Properties Co., Ltd. | Semiconductor device structure for anti-fuse |
US8004060B2 (en) | 2007-11-29 | 2011-08-23 | International Business Machines Corporation | Metal gate compatible electrical antifuse |
JP2009206490A (ja) * | 2008-01-30 | 2009-09-10 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8101471B2 (en) | 2008-12-30 | 2012-01-24 | Intel Corporation | Method of forming programmable anti-fuse element |
US8237457B2 (en) | 2009-07-15 | 2012-08-07 | International Business Machines Corporation | Replacement-gate-compatible programmable electrical antifuse |
US20110108926A1 (en) | 2009-11-12 | 2011-05-12 | National Semiconductor Corporation | Gated anti-fuse in CMOS process |
US8530283B2 (en) | 2011-09-14 | 2013-09-10 | Semiconductor Components Industries, Llc | Process for forming an electronic device including a nonvolatile memory structure having an antifuse component |
-
2012
- 2012-09-13 US US13/613,008 patent/US8975724B2/en active Active
-
2013
- 2013-09-13 CN CN201380047302.8A patent/CN104620383B/zh active Active
- 2013-09-13 WO PCT/US2013/059798 patent/WO2014043566A1/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102160178A (zh) * | 2008-09-19 | 2011-08-17 | 株式会社半导体能源研究所 | 半导体器件 |
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US8975724B2 (en) | 2015-03-10 |
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