CN102782842B - 提供通孔布置的系统及方法 - Google Patents

提供通孔布置的系统及方法 Download PDF

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Publication number
CN102782842B
CN102782842B CN201180012655.5A CN201180012655A CN102782842B CN 102782842 B CN102782842 B CN 102782842B CN 201180012655 A CN201180012655 A CN 201180012655A CN 102782842 B CN102782842 B CN 102782842B
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semiconductor chip
array
hole
contact
chip
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CN102782842A (zh
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顾时群
马修·迈克尔·诺瓦克
杜罗达米·J·里斯克
托马斯·R·汤姆斯
乌尔米·雷
徐钟元
阿尔温德·钱德拉舍卡朗
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Qualcomm Inc
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Qualcomm Inc
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Abstract

一种半导体芯片(402)包括电触点(412、413)阵列及多个通孔(416、417)，所述多个通孔将所述半导体芯片中的至少一个电路耦合到所述电触点阵列。所述电触点阵列中的所述电触点中的第一者(412)耦合到N个通孔(416)，且所述电触点阵列中的所述电触点中的第二者(413)耦合到M个通孔(417a、417b)。M及N为具有不同值的正整数。

Description

提供通孔布置的系统及方法
技术领域
本发明大体上涉及半导体电路中的特征布置，且更具体地说，涉及通孔布置。
背景技术
图1为示范性常规芯片封装100的说明。芯片封装100包括安装于逻辑芯片102的顶部上的宽输入/输出(I/O)存储器芯片101。使用(例如)粘接剂将芯片101及102安装到封装衬底104上。逻辑芯片102使用线接合105与在衬底102上的触点(未图示)电连通。
芯片101与102经展示为使用球状栅格阵列103、106而彼此电耦合。具体地说，存储器芯片101包括球状栅格阵列103(从侧面展示)，且逻辑芯片102包括球状栅格阵列106(也从侧面展示)。相应的球状栅格阵列103及106彼此对准，且彼此之间进行接触以使得芯片101与102连通。
图2为用于存储器芯片101(图1)的常规示范性布局的说明。所述存储器自身经划分成八个组201-208。宽I/O接口(例如，图1的103)经划分成四个通道211-214。相应组201-208中的每一者由一个通道服务，且通道211-214中的每一者服务所述组中的两者。
例如通道211-214等通道可以多种形状及大小中的任一者来出现。球状栅格阵列的一个实例包括四个通道，其中每一通道为约5毫米乘0.6毫米，包括6行乘48列的球。尽管本文中未展示，但在一些常规系统中，在球状栅格阵列103、106中的每一者下方存在再分配层(RDL)，所述RDL将焊料球中的每一者耦合到相应存储器元件(在存储器芯片101的情况下)或耦合到逻辑电路(在逻辑芯片102的情况下)。在其它常规系统中，穿硅通孔(TSV)将所述焊料球连接到其在逻辑芯片102中的相应逻辑电路。
图3为用于与存储器芯片101或逻辑芯片102一起使用的示范性常规球状栅格阵列300的说明。为了便于说明而展示截断的四个通道301-304。为简单起见，仅展示三种触点-电力触点、接地触点及信号触点，在图3中通过阴影来指示。球状栅格阵列300包括触点布置，在所述触点布置中电力连接及接地连接不仅在球状栅格阵列300的外围处，而且还在球状栅格阵列300的中央区域中。举例来说，电力触点310-314围绕球状栅格阵列300的外围而定位，而电力触点315-318围绕球状栅格阵列300的中央区域而定位。
图3中的布置具有一些缺点。举例来说，当触点及其相应层不在同一列中时，使用较多路由资源来在所述相应电力触点及接地触点与电力层及接地层之间制造TSV。类似地，当触点及其相应层不在同一行中时，使用较多水平路由资源。由于所述电力触点及接地触点需要到上层金属的低电阻路径，因此在所述TSV中消耗将近全部的路由资源。换句话说，在使用较多行及/或列来展开TSV的情况下，常规设计使用较多路由资源。此外，当将使用背侧金属层来使同一节点的TSV及触点短路时，常规上通过单独的BGA半自动贴装机(BSM)岛来使所述触点及TSV短路。为一群组触点(每一触点提供电力(或接地))使用单独的BSM岛有些复杂且效率低下。因此，可改进球状栅格阵列300。
返回到图1，注意到存储器芯片101放置于逻辑芯片102上，使得球状栅格阵列103、106的球彼此接触。然而，球状栅格阵列103并未覆盖存储器芯片101的背侧的整个表面区域。在生产期间，可将底填料(未图示)添加到芯片封装100以向各种组件提供机械支撑，但在生产期间(在添加底填料之前)围绕存储器芯片的外围的压力可导致影响球状栅格阵列103、106的相互接触及对准的扭矩。随着存储器芯片101的背侧的未被球状栅格阵列103覆盖的表面区域的量增加，扭矩的问题也增加。
发明内容
在一个实施例中，一种半导体芯片包含电触点阵列及多个通孔，所述多个通孔将所述半导体芯片中的至少一个电路耦合到所述电触点阵列。所述电触点阵列中的电触点中的第一者耦合到所述多个通孔中的N个通孔，且所述电触点阵列中的电触点中的第二者耦合到所述多个通孔中的M个通孔，其中M及N为具有不同值的正整数。
在另一实施例中，一种半导体芯片包含用于提供在所述半导体芯片外部的电接触的第一及第二装置。所述芯片还包含：用于耦合到所述半导体芯片中的第一电路的第一装置，所述第一电路耦合装置与所述第一电接触装置连通；及用于耦合到所述半导体芯片中的第二电路的第二装置。所述第二电路耦合装置与所述第二电接触装置连通。第一电路耦合装置的数目不同于第二电路耦合装置的数目。
在又一实施例中，一种半导体芯片制造方法包含制造耦合到所述半导体芯片中的至少一个电路的多个通孔及制造与所述多个通孔连通的电触点阵列。所述电触点阵列中的电触点中的第一者耦合到所述多个通孔中的N个通孔，且所述电触点阵列中的电触点中的第二者耦合到所述多个通孔中的M个通孔，其中M及N为具有不同值的正整数。
前文已相当广泛地概述了本发明的特征及技术优势以便可更好地理解以下具体实施方式。下文将描述形成本发明的权利要求书的标的物的额外特征及优势。所属领域的技术人员应了解，所揭示的概念及特定实施例可容易地利用为用于修改或设计用于实现本发明的相同目的的其它结构的基础。所属领域的技术人员还应认识到，此些等效构造并不脱离如在所附权利要求书中所阐述的本发明的技术。当结合附图考虑时，从以下描述将更好地理解被认为是本发明所特有的新颖特征(关于其组织及操作方法两者)以及另外的目标及优势。然而，应明确理解，所述图式中的每一者仅出于说明及描述目的而提供且不希望界定本发明的限制。
附图说明
为实现对本发明的更完整理解，现参考结合附图进行的以下描述。
图1为示范性常规芯片封装的说明。
图2为用于图1的存储器芯片的常规示范性布局的说明。
图3为用于与图1的存储器芯片或逻辑芯片一起使用的示范性常规球状栅格阵列的说明。
图4为根据一个实施例改编的示范性系统的说明。
图5为根据一个实施例改编的示范性过程的说明。
图6为根据一个实施例改编的示范性阵列的说明。
图7为用于在一些实施例中使用的与输入/输出触点相关的示范性TSV布置的说明。
图8为根据一个实施例改编的示范性过程的说明。
图9展示可有利地使用本发明的实施例的示范性无线通信系统。
具体实施方式
图4为根据一个实施例改编的示范性系统400的说明。系统400包括逻辑芯片402及存储器芯片401。存储器芯片401包括触点422、423，且逻辑芯片402包括触点412、413。为便利起见，图4仅展示四个触点412、413、422、423，但应理解各种实施例可包括更多的以阵列布置的触点。在图4中，以阵列布置所述触点，所述触点经对准以提供逻辑芯片402与存储器芯片401之间的电接触。具体地说，触点422及423与再分配层415连通以存取存储器芯片401中的各种存储器单元(未图示)。同样地，触点412及413依靠穿硅通孔(TSV)416、417与逻辑电路(未图示)及金属层418连通。尽管在图4的实施例中在逻辑芯片402上未展示RDL，但在替代实施例中可提供RDL。另外，使用硅作为半导体材料为示范性的，且其它实施例可使用其它半导体材料。
将注意力转向TSV 416、417，注意到触点412与单一TSV连通，而触点413与两个TSV连通。各种实施例针对一些触点使用不同数目的TSV以改进性能。举例来说，在此实例中，触点412为信号触点，且TSV 416将数据信号从金属层418中的电路输送到触点412。此外，在此实例中，触点413为通过TSV 417a及417b接收电力的电力触点。一般来说，随着在单一触点处的TSV的数目增加，电阻减少，同时电容增加。另一方面，一般来说，随着在单一触点处的TSV的数目减少，电阻增加，同时电容减少。触点412与单一TSV连通以减小触点412与金属层418中的电路之间的电容的量。另一方面，触点413与两个TSV连通以减小电源(未图示)与触点413之间的电阻量，且可耐受某种量的电容，尤其是考虑到电阻减少的益处。
尽管图4展示一个示范性实施例，但实施例的范围不限于每触点任何特定数目的TSV。在一些应用中，用于信号触点的TSV数目超过一个，而一些电力触点可利用仅单一TSV。对给定触点进行服务的TSV的数目可经配置以在成本、性能或其它相关因素方面有益于设计。此外，各种实施例可出于除了输送电力或信号以外的目的来使用通孔。举例来说，一些实施例可使用通孔通过将热量移向芯片外部来提供热支持，且可根据以上描述的原理来配置此类热通孔。
机械支撑凸块411、421不与逻辑电路或存储器单元相接触。而是，机械支撑凸块411、421放置于芯片401、402中的每一者的球状栅格阵列区域的外部，朝向其相应芯片的外围，以提供机械支撑。在许多实施例中，触点412、413及422、423为焊料球，且机械支撑凸块411及421为也通过生产触点412、413及422、423的相同过程所制造的球。在其它实施例中，使用与实际电触点不同的过程及/或在与实际电触点不同的时间处制造机械支撑凸块。此外，实施例的范围不限于任何特定形状的电触点或机械支撑凸块。另外，在一些实施例中，有可能将机械支撑凸块添加到一个芯片而不添加到另一芯片，同时(例如)通过使用较大的凸块或不同形状的凸块提供机械支撑。
机械支撑凸块411、421经对准且放置于芯片401及402的边缘附近以改善机械压力的效应，机械压力的效应原本可能导致扭矩且破坏触点412、413及422、423的对准及/或电连通。例如凸块411及421等机械支撑凸块的可用性可向芯片封装设计者提供灵活性。举例来说，存储器芯片上的触点可以阵列来放置于芯片的中心附近，如图2中所展示。当将存储器芯片与逻辑芯片进行堆叠时，归因于所述两个芯片之间的阵列连接，在所述存储器芯片的中心处可存在良好支撑。然而，如果所述存储器芯片的表面面积大于所述存储器芯片的触点阵列的面积，则所述存储器芯片的边缘附近几乎无机械支撑，从而使得当在所述存储器芯片的边缘附近施加力时所述堆叠遭受机械故障。
芯片封装设计者可将机械支撑凸块添加到存储器芯片及/或逻辑芯片以增加机械支撑。机械支撑凸块的可用性可允许设计者从多种存储器芯片当中进行选择，其中一些存储器芯片的表面面积与其相应触点阵列的面积相比为大的。设计者可在制造芯片期间或稍后在堆叠芯片时添加机械支撑凸块。
尽管以上实施例包括一个存储器芯片及一个逻辑芯片，但实施例的范围不限于此。举例来说，不论所使用的芯片类型或芯片数目如何，各种实施例可将机械支撑凸块应用于任何种类的堆叠芯片布置。
图5为根据一个实施例改编的示范性过程500的说明。可(例如)由制造半导体芯片封装的人及/或机器来执行过程500。
在框501中，在芯片封装中堆叠第一及第二半导体芯片。第一半导体芯片具有第一电触点阵列，所述第一电触点阵列与在第二半导体芯片上的第二电触点阵列对准。所述半导体芯片中的任一者或两者可包括布置于其中的通孔以优化一个或一个以上因素(例如，性能)，如以上关于图4所论述。在框502中，在第一及第二电触点阵列外部的表面区域内且在第一与第二半导体芯片之间使用凸块提供用于所述芯片封装的机械支撑。所述凸块可(例如)基于机械支撑在何处最有效来放置。举例来说，可将所述凸块放置于所述芯片中的较小者的转角处或附近、所述芯片中的较小者的一个或一个以上边缘的邻近区域中及/或可能有帮助的其它任何位置。可根据现在已知或稍后开发的多种技术中的任一者来制造所述凸块。在一个实例中，在晶片上沉积凸块下金属层(UBM)，从而提供用于电镀的电极。执行光刻过程来图案化所述晶片上的抗蚀剂，其中用以形成凸块的区域将不具有抗蚀剂。将所述晶片浸没到电镀溶液中，其中所述晶片经偏置为阴极。在目标区域上沉积金属(例如，Cu、Sn及/或其类似者)。在完成电镀之后，将所述抗蚀剂剥离。通过湿化学来移除在敞露区域上的UBM。
尽管将过程500展示为一系列离散过程，但实施例的范围不限于此。各种实施例可添加、省略、重新布置或修改过程500的动作。举例来说，在一些实施例中，在堆叠所述半导体芯片之前(例如在制造所述个别半导体芯片期间)添加所述凸块。在其它实施例中，可甚至在制造完所述半导体芯片之后添加所述凸块。在各种实施例中，过程500可包括另外的动作，例如添加底填料及/或将芯片封装并入到装置中，所述装置例如为蜂窝式电话、计算机、导航装置或其类似者。
以上的实例实施例展示用于提供机械支撑的技术，包括机械支撑凸块的使用。以下的实例说明用于在两个或两个以上堆叠芯片之间以及在电触点与芯片内的电路之间提供电连通的技术。
图6为根据一个实施例改编的示范性阵列600的说明。触点阵列600可用于存储器芯片及逻辑芯片(例如，图1及图4的芯片)中。与图3的布局相反，电力触点及接地触点群集在所述阵列的外围附近且远离所述阵列的中心。举例来说，以行610及611布置电力触点，且以行620及621布置接地触点。所述电力触点与电力金属层630连通。类似地，所述接地触点与接地金属层640连通，在此实例中，所述接地金属层640包括单一BGA半自动贴装机(BSM)形状。
图6中所展示的布置的结果是为了保持所述电力触点在其它电力触点附近、所述接地触点在其它接地触点附近，且所述电力触点及接地触点两者均放置于接近电力金属层及接地金属层处。此外，即使接地金属层640接近阵列600的中心，所述接地触点(及电力触点)仍被排除在所述阵列的中心之外。与图3中所展示的常规阵列相反，图6的阵列以允许所述触点中的较多者通过水漫型(flood-type)区域而非作为单独的BSM岛短路的方式来对准所述触点。换句话说，图6的实例布局布置所述触点以使得一个VDD(电力)节点使所述电力触点短路，且一个Vss(接地)节点使所述接地触点短路，至少在路由资源方面，此布置比图3的阵列更有效率。
图6展示未被划分成多个通道的阵列，但实施例的范围不限于此。在另一实例中，将阵列划分成四个通道。许多实施例包括N乘M个通道布置，其中N及M可为任何大于零的整数。可根据多种实施例来改编任何触点阵列。
图7为用于在一些实施例中使用的与输入/输出触点(例如，焊料球)相关的示范性TSV布置的说明。图7提供触点(例如，焊料凸块)710、720及730的俯视平面图，其中所展示的点用以说明关于触点710、720及730中的每一者的可能的TSV放置。所述TSV中的每一者可在给定触点与在半导体芯片内部的一个或一个以上逻辑电路或存储器单元(未图示)之间提供电连通或热连通。
如图所示，触点710与一个TSV 711连通，而触点720与两个TSV 721、722连通。触点730与四个TSV 731-734连通。触点710、720及730的形状以及TSV的相对放置及数目为示范性的且在其它实施例中可不同。可改编根据图7的原理的TSV布置以用于与图1及4中的触点阵列一起使用。
图8为根据一个实施例改编的示范性过程800的说明。可(例如)由制造半导体芯片封装的人及/或机器来执行过程800。
在框801中，将接地与第一触点群组电接触。在框802中，将电源与第二触点群组电接触。在一些实施例中，所述触点包括在球状栅格阵列中的焊料凸块，且所述电源及接地包括金属层。可以多种方式中的任一者(包括通过使用TSV及/或RDL)来进行在所述接地/电源与所述触点之间的电连通。TSV可经布置以影响一个或一个以上相关因素(例如，电阻及/或电容)，如以上关于图4所论述。
在框803中，数据线电接触第三触点群组。所述数据线上的数据信号可从存储器单元或逻辑电路来接收且可通过使用TSV及/或RDL来输送。第一及第二触点群组群集在所述阵列的外围周围。所述电力触点及接地触点的布置使得所述电力触点及接地触点不在所述触点阵列的中心附近而是围绕所述阵列的外围来布置，如图6中所展示。
尽管将过程800展示为一系列离散过程，但实施例的范围不限于此。各种实施例可添加、省略、重新布置或修改过程800的动作。举例来说，在一些实施例中，使用相同过程在相同时间处制造所述触点及其电连接。另外，过程800可包括另外的处理，例如将所述阵列与另一芯片上的阵列对准及堆叠所述芯片以使得所述芯片彼此连通。根据过程800制造的半导体芯片可并入到多种基于处理器的装置中的任一者中。
图9展示其中可有利地使用本发明的实施例的示范性无线通信系统900。出于说明的目的，图9展示三个远程单元920、930及940以及两个基站950、960。将认识到，无线通信系统可具有更多远程单元及基站。远程单元920、930及940分别包括经改进的半导体装置925A、925B及925C，如以上所论述，在各种实施例中，所述半导体装置包括经改进的电触点布置及/或内部机械支撑结构。图9展示来自基站950、960到远程单元920、930及940的前向链路信号980，及从远程单元920、930及940到基站950、960的反向链路信号990。
在图9中，远程单元920被展示为移动电话，远程单元930被展示为便携式计算机，且远程单元940被展示为无线本地环路系统中的计算机。举例来说，远程单元920可包括移动装置，例如蜂窝式电话、手持式个人通信系统(PCS)单元、例如个人数据助理等便携式数据单元。远程单元920还可包括例如仪表读取设备等固定位置数据单元。尽管图9说明根据本发明教示的远程单元，但本发明不限于这些示范性所说明单元。本发明可适用于包括半导体芯片的任何装置中。尽管已阐述了特定电路，但所属领域的技术人员将了解，实践本发明并非需要全部所揭示的电路。另外，尚未描述某些众所周知的电路，以集中精力于本发明。
本文中所描述的方法可依据应用而通过各种组件加以实施。举例来说，这些方法可以硬件、固件、软件或其任何组合加以实施。对于硬件实施方案，处理单元可实施于一个或一个以上专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理装置(DSPD)、可编程逻辑装置(PLD)、现场可编程门阵列(FPGA)、处理器、控制器、微控制器、微处理器、电子装置、经设计以执行本文中所描述的功能的其它电子单元或其组合内。
对于固件及/或软件实施方案，可使用执行本文中所描述的功能的模块(例如，程序、函数等等)来实施所述方法。有形地体现指令的任何机器可读媒体均可用于实施本文中所描述的方法。举例来说，软件代码可存储于存储器中且由处理器单元执行。存储器可实施于处理器单元内或处理器单元外部。如本文中所使用，术语“存储器”指代任何类型的长期、短期、易失性、非易失性或其它存储器，且不应限于任何特定存储器类型或存储器数目，或上面存储存储器的媒体类型。
如果以固件及/或软件加以实施，则所述功能可作为一个或一个以上指令或代码而存储于计算机可读媒体上。实例包括编码有数据结构的计算机可读媒体及编码有计算机程序的计算机可读媒体。计算机可读媒体包括物理计算机存储媒体。存储媒体可为可由计算机存取的任何可用媒体。借助于实例而非限制，此些计算机可读媒体可包含RAM、ROM、EEPROM、CD-ROM或其它光盘存储装置、磁盘存储装置或其它磁性存储装置，或可用以存储呈指令或数据结构的形式的所要程序代码且可由计算机存取的任何其它媒体；如本文中所使用，磁盘及光盘包括压缩光盘(CD)、激光光盘、光学光盘、数字通用光盘(DVD)、软性磁盘及蓝光光盘，其中磁盘通常以磁性方式再现数据，而光盘通过激光以光学方式再现数据。上述各项的组合也应包括在计算机可读媒体的范围内。
除了存储于计算机可读媒体上以外，指令及/或数据还可作为信号提供在包括于通信设备中的传输媒体上。举例来说，通信设备可包括具有指示指令及数据的信号的收发器。指令及数据经配置以使一个或一个以上处理器实施权利要求书中所概述的功能。
尽管已详细地描述了本发明及其优点，但应理解，在不脱离如由所附权利要求书所界定的本发明的技术的情况下，可对本发明作出各种改变、替代及更改。另外，本申请案的范围不希望限于说明书中所描述的过程、机器、制造、物质组成、装置、方法及步骤的特定实施例。如所属领域的技术人员将易于从本发明了解，可根据本发明而利用目前现存或稍后开发的执行与本文中所描述的对应实施例大致上相同的功能或实现与所述对应实施例大致上相同的结果的过程、机器、制造、物质组成、装置、方法或步骤。因此，所附权利要求书既定在其范围内包括此些过程、机器、制造、物质组成、装置、方法或步骤。

Claims (22)

1.一种半导体芯片，其包含：
电触点阵列，其包含接地触点阵列、电力触点阵列以及信号触点阵列，所述电力触点阵列和所述接地触点阵列布置在所述半导体芯片的外围，所述信号触点阵列布置在所述半导体芯片的中心且比所述电力触点阵列和所述接地触点阵列距所述半导体芯片的边缘隔开更远，且所述信号触点阵列至少部分地被接地金属层包围；及
多个通孔，所述多个通孔将所述半导体芯片中的至少一个电路耦合到所述电触点阵列，其中所述电触点阵列中的所述电触点中的第一者耦合到所述多个通孔中的N个通孔，且其中所述电触点阵列中的所述电触点中的第二者耦合到所述多个通孔中的M个通孔，其中M及N为具有不同值的正整数。
2.根据权利要求1所述的半导体芯片，其中所述第一电触点包含电力触点，且其中所述第二电触点包含信号触点，且另外其中M大于N。
3.根据权利要求1所述的半导体芯片，其中所述多个通孔包含至少一个热通孔。
4.根据权利要求1所述的半导体芯片，其中所述多个通孔包含穿硅通孔TSV。
5.根据权利要求1所述的半导体芯片，其中所述N个通孔直接耦合到所述第一电触点。
6.根据权利要求1所述的半导体芯片，其中所述N个通孔通过再分配层耦合到所述第一电触点。
7.根据权利要求1所述的半导体芯片，其进一步包含：
多个支撑凸块，其位于所述电触点阵列外部，所述支撑凸块提供用于包括所述半导体芯片的芯片封装的机械支撑。
8.根据权利要求7所述的半导体芯片，其中所述半导体芯片包含逻辑芯片，所述逻辑芯片耦合到所述芯片封装中的存储器芯片。
9.根据权利要求1所述的半导体芯片，其并入到音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和/或计算机中。
10.一种半导体芯片，其包含：
电触点阵列，其包含：
用于提供在所述半导体芯片外部的电接触的电力装置；
用于提供在所述半导体芯片外部的电接触的信号装置；及
用于在所述半导体芯片的外部提供电触点的接地装置；
用于耦合到所述半导体芯片中的第一电路的第一装置，所述第一电路耦合装置与所述第一电接触装置连通；及
用于耦合到所述半导体芯片中的第二电路的第二装置，所述第二电路耦合装置与所述第二电接触装置连通；
其中第一电路耦合装置的数目不同于第二电路耦合装置的数目；及
其中所述电力装置和所述接地装置布置在所述半导体芯片的外围，所述信号装置布置在所述半导体芯片的中心且比所述电力装置和所述接地装置距所述半导体芯片的边缘隔开更远，且所述信号装置至少部分地被接地金属层包围。
11.根据权利要求10所述的半导体芯片，其中所述电力装置、所述信号装置以及所述接地装置包含在球状栅格阵列中的焊料球。
12.根据权利要求10所述的半导体芯片，其中所述第一及第二电路耦合装置包含穿硅通孔TSV。
13.根据权利要求10所述的半导体芯片，其中所述第一电路耦合装置的数目大于所述第二电路耦合装置的数目。
14.根据权利要求10所述的半导体芯片，其中所述半导体芯片被包括在具有存储器芯片的芯片封装中，其中所述电力装置及所述信号装置提供与所述存储器芯片上的多个触点的电连通。
15.根据权利要求10所述的半导体芯片，其并入到音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和/或计算机中。
16.一种制造半导体芯片的方法，所述制造方法包含：
制造多个通孔，所述多个通孔耦合到所述半导体芯片中的至少一个电路；及
制造与所述多个通孔连通的电触点阵列，所述电触点阵列包含接地触点阵列，电力触点阵列以及信号触点阵列，其中所述电触点阵列中的所述电触点中的第一者耦合到所述多个通孔中的N个通孔，且其中所述电触点阵列中的所述电触点中的第二者耦合到所述多个通孔中的M个通孔，其中M及N为具有不同值的正整数；
将所述电力触点阵列和所述接地触点阵列布置在所述半导体芯片的外围；
将所述信号触点阵列布置在所述半导体芯片的中心且比所述电力触点阵列和所述接地触点阵列距所述半导体芯片的边缘隔开更远；且
将所述信号触点阵列布置在接地金属层内。
17.根据权利要求16所述的方法，其进一步包含：在芯片封装中将所述半导体芯片与另一半导体芯片进行堆叠。
18.根据权利要求16所述的方法，其进一步包含：
将所述半导体芯片并入到音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和/或计算机中。
19.一种制造半导体芯片的方法，所述制造方法包含以下步骤：
制造耦合到所述半导体芯片中的至少一个电路的多个通孔；及
制造与所述多个通孔连通的电触点阵列，所述电触点阵列包含接地触点阵列，电力触点阵列以及信号触点阵列，其中所述电触点阵列中的所述电触点中的第一者耦合到所述多个通孔中的N个通孔，且其中所述电触点阵列中的所述电触点中的第二者耦合到所述多个通孔中的M个通孔，其中M及N为具有不同值的正整数；
将所述电力触点阵列和所述接地触点阵列布置在所述半导体芯片的外围；
将所述信号触点阵列布置在所述半导体芯片的中心且比所述电力触点阵列和所述接地触点阵列距所述半导体芯片的边缘隔开更远，且
将所述信号触点阵列布置在接地金属层内。
20.根据权利要求19所述的方法，其中所述电触点阵列包含焊料凸块。
21.根据权利要求19所述的方法，其进一步包含：在芯片封装中将所述半导体芯片与另一半导体芯片进行堆叠。
22.根据权利要求19所述的方法，其进一步包含：
将所述半导体芯片并入到音乐播放器、视频播放器、娱乐单元、导航装置、通信装置、个人数字助理PDA、固定位置数据单元和/或计算机中。
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WO2011097630A3 (en) 2011-09-29
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KR20120134121A (ko) 2012-12-11
US20110193212A1 (en) 2011-08-11
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