WO2008114313A1 - Ｐｌｌ周波数シンセサイザ - Google Patents

Ｐｌｌ周波数シンセサイザ Download PDF

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Publication number
WO2008114313A1
WO2008114313A1 PCT/JP2007/000244 JP2007000244W WO2008114313A1 WO 2008114313 A1 WO2008114313 A1 WO 2008114313A1 JP 2007000244 W JP2007000244 W JP 2007000244W WO 2008114313 A1 WO2008114313 A1 WO 2008114313A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
control code
voltage
frequency control
controlled
Prior art date
Application number
PCT/JP2007/000244
Other languages
English (en)
French (fr)
Inventor
Masafumi Kondou
Toshihiko Mori
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000244 priority Critical patent/WO2008114313A1/ja
Priority to JP2009504906A priority patent/JP4641325B2/ja
Publication of WO2008114313A1 publication Critical patent/WO2008114313A1/ja
Priority to US12/560,118 priority patent/US8138842B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

　周波数シンセサイザは，電圧制御発振器と，電圧制御発振器の出力信号の周波数を分周する分周器と，基準周波数を有する参照入力信号と分周器の分周出力信号との位相を比較して位相差信号を出力する位相比較器と，位相差信号に応じて制御電圧を生成する制御電圧生成ユニットとを有するＰＬＬ回路を有し，分周器は周波数選択信号に応答して複数の分周比のうち選択された分周比に可変設定される。更に，電圧制御発振器の電圧制御される周波数レンジを設定する周波数制御コードを，可変設定される分周比に対応して検出する周波数レンジチューニング回路と，それが検出した周波数制御コー前記分周比に対応して記憶する周波数制御コードメモリとを有する。初期化期間では，周波数レンジチューニング回が分周比に対応する周波数制御コードを検出し，周波数制御コードメモリがそれを記憶する。通常動作期間では，周波数選択信号に応答して，周波数制御コードメモリに記憶されている周波数制御コードであって，可変設定される分周比に対応する周波数制御コードが電圧制御発振器に出力される。
PCT/JP2007/000244 2007-03-16 2007-03-16 Ｐｌｌ周波数シンセサイザ WO2008114313A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/000244 WO2008114313A1 (ja) 2007-03-16 2007-03-16 Ｐｌｌ周波数シンセサイザ
JP2009504906A JP4641325B2 (ja) 2007-03-16 2007-03-16 Ｐｌｌ周波数シンセサイザ
US12/560,118 US8138842B2 (en) 2007-03-16 2009-09-15 PLL frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000244 WO2008114313A1 (ja) 2007-03-16 2007-03-16 Ｐｌｌ周波数シンセサイザ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/560,118 Continuation US8138842B2 (en) 2007-03-16 2009-09-15 PLL frequency synthesizer

Publications (1)

Publication Number Publication Date
WO2008114313A1 true WO2008114313A1 (ja) 2008-09-25

Family

ID=39765434

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000244 WO2008114313A1 (ja) 2007-03-16 2007-03-16 Ｐｌｌ周波数シンセサイザ

Country Status (3)

Country Link
US (1) US8138842B2 (ja)
JP (1) JP4641325B2 (ja)
WO (1) WO2008114313A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8436686B2 (en) * 2010-09-20 2013-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for efficient time slicing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237699A (ja) * 2000-02-23 2001-08-31 Hitachi Ltd 無線通信システム
JP2003152535A (ja) * 2001-11-16 2003-05-23 Hitachi Ltd 通信用半導体集積回路および無線通信システム

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0669722B1 (en) 1994-02-28 2001-10-17 Nec Corporation PLL circuit having shortened locking time
JP2885662B2 (ja) 1994-02-28 1999-04-26 山形日本電気株式会社 Ｐｌｌ回路
JP3320651B2 (ja) 1998-05-06 2002-09-03 富士通株式会社 半導体装置
JP3488180B2 (ja) 2000-05-30 2004-01-19 松下電器産業株式会社 周波数シンセサイザ
JP3415574B2 (ja) 2000-08-10 2003-06-09 Ｎｅｃエレクトロニクス株式会社 Ｐｌｌ回路
JP2005109618A (ja) * 2003-09-29 2005-04-21 Renesas Technology Corp 通信用半導体集積回路および携帯端末システム
US7230496B2 (en) * 2004-02-19 2007-06-12 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer, radio communication system using the synthesizer, and control method of the synthesizer
JP2006033488A (ja) * 2004-07-16 2006-02-02 Renesas Technology Corp 通信用半導体集積回路
JP4542978B2 (ja) * 2005-10-27 2010-09-15 パナソニック株式会社 電源電圧制御装置
US7609122B2 (en) * 2007-10-05 2009-10-27 Silicon Storage Technology, Inc. Method and system for calibration of a tank circuit in a phase lock loop

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237699A (ja) * 2000-02-23 2001-08-31 Hitachi Ltd 無線通信システム
JP2003152535A (ja) * 2001-11-16 2003-05-23 Hitachi Ltd 通信用半導体集積回路および無線通信システム

Also Published As

Publication number Publication date
JPWO2008114313A1 (ja) 2010-06-24
JP4641325B2 (ja) 2011-03-02
US20100007425A1 (en) 2010-01-14
US8138842B2 (en) 2012-03-20

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