WO2008111409A1 - 半導体チップ及び半導体装置 - Google Patents

半導体チップ及び半導体装置 Download PDF

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Publication number
WO2008111409A1
WO2008111409A1 PCT/JP2008/053612 JP2008053612W WO2008111409A1 WO 2008111409 A1 WO2008111409 A1 WO 2008111409A1 JP 2008053612 W JP2008053612 W JP 2008053612W WO 2008111409 A1 WO2008111409 A1 WO 2008111409A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitative coupling
silicon substrate
signal transmission
transmission circuit
semiconductor chip
Prior art date
Application number
PCT/JP2008/053612
Other languages
English (en)
French (fr)
Inventor
Eiji Hankui
Toshihide Kuriyama
Hideki Sasaki
Muneo Fukaishi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/529,443 priority Critical patent/US7990747B2/en
Priority to JP2009503966A priority patent/JP5471439B2/ja
Publication of WO2008111409A1 publication Critical patent/WO2008111409A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

　複数ＣＰＵ間、ＣＰＵ－メモリ間、複数メモリ間など、データ伝送の高速化や大容量化の要求と、実装面積の小型化の要求の特に強い半導体チップおよび半導体装置に対し、チップ間を非接触で３層以上に積み上げることにより、接続信頼性の高い半導体装置及びその半導体チップを提供する。 　本発明の半導体チップ２ｂは、第１の信号伝送回路６ｂと第１の切替えスイッチ７が形成されたシリコン基板３ｂと、第１の容量性結合用上部電極８ｂがその上に形成された配線層４ｂとから構成される半導体チップであって、シリコン基板を貫通する第１のビアホール９を介してシリコン基板の裏面にも第１の容量性結合用下部電極８ｃが形成され、第１の容量性結合用上部電極は第１の信号伝送回路に直接接続されているのに対し、第１の容量性結合用下部電極は第１のビアホールと第１の切替えスイッチとを介して第１の信号伝送回路に接続されている。
PCT/JP2008/053612 2007-03-09 2008-02-29 半導体チップ及び半導体装置 WO2008111409A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/529,443 US7990747B2 (en) 2007-03-09 2008-02-29 Semiconductor chip and semiconductor device
JP2009503966A JP5471439B2 (ja) 2007-03-09 2008-02-29 半導体チップ及び半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007060352 2007-03-09
JP2007-060352 2007-03-09

Publications (1)

Publication Number Publication Date
WO2008111409A1 true WO2008111409A1 (ja) 2008-09-18

Family

ID=39759352

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053612 WO2008111409A1 (ja) 2007-03-09 2008-02-29 半導体チップ及び半導体装置

Country Status (3)

Country Link
US (1) US7990747B2 (ja)
JP (1) JP5471439B2 (ja)
WO (1) WO2008111409A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186764A (ja) * 2009-02-10 2010-08-26 Hitachi Ltd 半導体集積回路装置
WO2010110244A1 (ja) * 2009-03-25 2010-09-30 株式会社 東芝 三次元半導体集積回路
WO2010119625A1 (ja) * 2009-04-13 2010-10-21 日本電気株式会社 半導体装置及びそのテスト方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10826536B1 (en) * 2019-10-03 2020-11-03 International Business Machines Corporation Inter-chip data transmission system using single-ended transceivers
JP7282329B2 (ja) * 2019-10-04 2023-05-29 本田技研工業株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190770A (ja) * 1992-01-09 1993-07-30 Fujitsu Ltd 半導体装置
JP2006019328A (ja) * 2004-06-30 2006-01-19 Nec Corp 積層型半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS562662A (en) 1979-06-22 1981-01-12 Hitachi Ltd Laminated electric circuit
JPS60246654A (ja) 1984-05-22 1985-12-06 Agency Of Ind Science & Technol 三次元集積回路
JPS6220362A (ja) * 1985-07-19 1987-01-28 Hitachi Ltd 積層電気回路用信号伝送回路
US6728113B1 (en) 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
US5818112A (en) 1994-11-15 1998-10-06 Siemens Aktiengesellschaft Arrangement for capacitive signal transmission between the chip layers of a vertically integrated circuit
TW419810B (en) 1998-06-18 2001-01-21 Hitachi Ltd Semiconductor device
JP5136056B2 (ja) * 2005-09-06 2013-02-06 日本電気株式会社 半導体装置
US7473999B2 (en) * 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
JP5078338B2 (ja) * 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 半導体記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190770A (ja) * 1992-01-09 1993-07-30 Fujitsu Ltd 半導体装置
JP2006019328A (ja) * 2004-06-30 2006-01-19 Nec Corp 積層型半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010186764A (ja) * 2009-02-10 2010-08-26 Hitachi Ltd 半導体集積回路装置
WO2010110244A1 (ja) * 2009-03-25 2010-09-30 株式会社 東芝 三次元半導体集積回路
JP2010226008A (ja) * 2009-03-25 2010-10-07 Toshiba Corp 三次元半導体集積回路
US8497732B2 (en) 2009-03-25 2013-07-30 Kabushiki Kaisha Toshiba Three-dimensional semiconductor integrated circuit
WO2010119625A1 (ja) * 2009-04-13 2010-10-21 日本電気株式会社 半導体装置及びそのテスト方法

Also Published As

Publication number Publication date
US7990747B2 (en) 2011-08-02
JP5471439B2 (ja) 2014-04-16
JPWO2008111409A1 (ja) 2010-06-24
US20100097159A1 (en) 2010-04-22

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