US20100097159A1 - Semiconductor chip and semiconductor device - Google Patents
Semiconductor chip and semiconductor device Download PDFInfo
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- US20100097159A1 US20100097159A1 US12/529,443 US52944308A US2010097159A1 US 20100097159 A1 US20100097159 A1 US 20100097159A1 US 52944308 A US52944308 A US 52944308A US 2010097159 A1 US2010097159 A1 US 2010097159A1
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- 239000000758 substrate Substances 0.000 claims abstract description 72
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device for performing signal transmission between chips or between a chip and a package and the semiconductor chips thereof and, more particularly, to a semiconductor device for contactlessly performing signal transmission among a plurality of chips wherein a plurality of chips are stacked in a layered manner (three-dimensional manner) and the semiconductor chips thereof.
- this configuration is expected to come into practical use for the connection between semiconductor chips that requires multitude of electrodes, particularly among a plurality of CPUs, between a CPU and a memory, and among a plurality of memories, and for a semiconductor device in which these semiconductor chips are stacked.
- FIG. 1 illustrates a typical semiconductor device for performing contactless signal transmission, wherein electrode A and electrode B are formed on the circuit surfaces of chip A and chip B, respectively, adjacently oppositely to each other.
- electrode A is assumed to be a driver and electrode B is assumed to be a receiver, then electrostatic capacitance is present between the two electrodes, causing the two electrodes to capacitively couple with each other. That is, electrical lines of force generated from electrode A at this time reach electrode B, thereby placing the two electrodes in a state of being electrically coupled with each other (capacitive coupling). Consequently, a signal exchange is made from electrode A to electrode B.
- Patent documents 1 and 2 disclose a stacked electrical circuit in which a conductive region for penetrating through the front and back sides of a silicon substrate is provided and a signal transmission is performed with the mode thereof categorized into (1) a case where a signal from a wafer stacked on an upper side is received; (2) a case where a signal is transmitted to a wafer stacked on an upper side; (3) a case where a signal from a wafer stacked on a lower side is received; and (4) a case where a signal is transmitted to a wafer stacked on a lower side.
- Patent document 3 discloses a three-layer modular electronic system, though the system is intended not for signal transmission among three or more chips but for signal transmission between two chips.
- electrodes are provided on upper and lower sides between the chips and a dielectric material substrate, in which an interconnection that penetrates the electrodes is formed, is sandwiched between the electrodes.
- Patent document 1 Japanese Patent Laid-Open No. 56-002662
- Patent document 2 Japanese Patent Laid-Open No. 62-020362
- Patent document 3 Published Japanese translations of PCT international publication No. 09-504908
- Patent documents 1 and 2 do not disclose any specific exemplary embodiments with regard to circuits for performing transmission/reception and switching signals between the upper and lower sides. Accordingly, although a contactless method is employed, theses patent documents could not achieve an increase in the speed and capacity of inter-chip data transmission and a reduction in the packaging size of a semiconductor device.
- Patent document 3 illustrates in FIG. 8 an embodiment in which a one-to-many connection is made between chips by using an interconnection within the dielectric material substrate, the exemplary embodiment suffers from a problem in which the operation speed decreases because a circuit of branch destination serves as a load on the circuit operation.
- a semiconductor chip includes a silicon substrate on which a first signal transmission circuit and a first changeover switch are formed; a wiring layer formed on the silicon substrate; and a first capacitive-coupling upper electrode formed on the wiring layer; wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole penetrating the silicon substrate, the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, and the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and the first changeover switch.
- a semiconductor device comprises a semiconductor chip including a silicon substrate on which a first signal transmission circuit and a first changeover switch are formed; an interconnection layer formed on the silicon substrate; and a first capacitive-coupling upper electrode formed on the interconnection layer; wherein the first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate, the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, and the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and the first changeover switch.
- a signal transmission between respective two semiconductor chips is controlled and a signal transmission between predetermined electrodes within predetermined semiconductor chips is realized.
- a signal is transmitted through a capacitive coupling, there is no need to ensure electrical conductivity as in the case of contact-type electrodes, thereby increasing the tolerance of positioning accuracy between semiconductor chips.
- FIG. 1 is a cross-sectional view illustrating the configuration of a related semiconductor device for performing signal transmission by means of capacitive coupling between two chips.
- FIG. 2 is a cross-sectional view illustrating the configuration of a related semiconductor device for performing signal transmission by means of capacitive coupling among three chips.
- FIG. 3 is a schematic view illustrating a semiconductor device according to an exemplary embodiment of the present invention in which three semiconductor chips are stacked.
- FIG. 4 is an enlarged view of an electrode pad portion in FIG. 3 , illustrating the configuration of a first exemplary embodiment.
- FIG. 5 is a circuit diagram of semiconductor chip 2 b illustrated in FIG. 4 .
- FIG. 6 is another enlarged view of the electrode pad portion in FIG. 3 , illustrating the configuration of a second exemplary embodiment.
- FIG. 7 is a circuit diagram of semiconductor chip 2 b illustrated in FIG. 6 .
- FIG. 8 is another enlarged view of the electrode pad portion in FIG. 3 , illustrating the configuration of a third exemplary embodiment.
- FIG. 9 is a circuit diagram of semiconductor chip 2 b illustrated in FIG. 8 .
- FIG. 10 is another enlarged view of the electrode pad portion in FIG. 3 , illustrating the configuration-of a fourth exemplary embodiment.
- FIG. 11 is a circuit diagram of semiconductor chip 2 b illustrated in FIG. 10 .
- FIG. 12 is another enlarged view of the electrode pad portion in FIG. 3 , illustrating the configuration of a fifth exemplary embodiment.
- FIG. 13 is a circuit diagram of semiconductor chip 2 b illustrated in FIG. 12 .
- FIG. 14 is a circuit diagram of semiconductor chip 2 b of a sixth exemplary embodiment.
- FIG. 15 is a schematic view to explain the operation of one-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and a capacitive-coupling portion includes an amplifier element.
- FIG. 16 is a schematic view to explain the operation of one-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and a capacitive-coupling portion includes an amplifier fitted with a switch function.
- FIG. 17 is a schematic view to explain the operation of two-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and from the lower electrode to the upper electrode and a capacitive-coupling portion includes an amplifier element.
- FIG. 18 is a schematic view to explain the operation of two-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and from the lower electrode to the upper electrode and a capacitive-coupling portion includes an amplifier having a switch function.
- FIG. 19 is a diagram of a transmitter/receiver circuit of the first exemplary embodiment.
- FIG. 20 is a schematic view illustrating a timing chart of a transmitter/receiver circuit of the first exemplary embodiment.
- FIG. 21 is a block diagram illustrating a sampling latch-type receiver circuit as an example of a receiver circuit of the first exemplary embodiment.
- FIG. 3 illustrates semiconductor device 1 in which three semiconductor chips 2 a, 2 b and 2 c are stacked.
- An electrode pad is formed on a surface of each semiconductor chip and these electrode pads are positioned opposite to each other at a certain distance, so that an inter-chip signal exchange is performed between the opposed electrode pads.
- an electrode pad is formed on a surface in which a circuit is formed, while in semiconductor chip 2 b, an electrode pad is also formed on the rear surface thereof.
- This semiconductor chip 2 b makes it possible to exchange a signal among semiconductor chips even if three or more semiconductor chips are stacked.
- FIG. 4 is an enlarged view of an electrode pad portion in FIG. 3 , and illustrates the configuration of a first exemplary embodiment.
- Semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 a is formed in silicon substrates 3 a, and electrode pad 8 a is formed in or on interconnection layers 4 a formed on the transmitter/receiver circuit.
- Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 c is formed in silicon substrates 3 c, and electrode pad 8 d is formed in or on interconnection layers 4 c formed on the transmitter/receiver circuit.
- Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switch 7 is formed in silicon substrate 3 b.
- electrode pad 8 b is formed in or on interconnection layer 4 b and electrode pad 8 c is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 that penetrates silicon substrate 3 b.
- electrode pad 8 b present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 b, whereas electrode pad 8 c present on the rear surface is connected to the transmitter/receiver circuit through via hole 9 and switch 7 .
- FIG. 5 illustrates the circuit diagram of semiconductor chip 2 b previously shown.
- transmitter/receiver circuits 6 a, 6 b and 6 c are shown being integral as a transmitter/receiver circuit in the exemplary embodiment, the transmitter/receiver circuit may be a transmitter circuit and a receiver circuit that are separate from each other.
- via hole 9 is connected to electrode pad 8 c.
- a via hole is formed on a silicon substrate, a thin insulating layer must be provided on a boundary face between the silicon and the via hole, unlike when a via hole is formed on an organic substrate. Consequently, the parasitic capacitance of the via hole may amount to as large as several pF, which value is not negligible, as compared with capacitance formed between electrode pads of adjacent semiconductor chips. For this reason, in the present invention, switch 7 is provided in order to make the parasitic capacitance of this via hole 9 invisible from a signal that is input from electrode pad 8 b.
- electrode pad 8 b when a signal is output from transmitter/receiver circuit 6 b to electrode pad 8 c, electrode pad 8 b, as well as via hole 9 and electrode pad 8 c, are visible from transmitter/receiver circuit 6 b.
- the parasitic capacitance of electrode pad 8 b is sufficiently small compared with that of via hole 9 and hence is negligible.
- Interposing switch 7 not only between transmitter/receiver circuit 6 b and electrode pad 8 c but also between transmitter/receiver circuit 6 b and electrode pad 8 b is conceivable.
- a switch is provided only in a portion that connects to the via hole and that has the largest parasitic capacitance.
- switch 7 When a signal is input from electrode pad 8 c, switch 7 is closed. As a result, the signal that is input from electrode pad 8 c is supplied to transmitter/receiver circuit 6 b. On the other hand, when a signal is output from the transmitter/receiver circuit to electrode pad 8 b, switch 7 is opened.
- Semiconductor chips 2 a, 2 b and 2 c described above may be stacked as illustrated in FIG. 3 to form semiconductor device 1 .
- FIG. 6 illustrates a second exemplary embodiment.
- switch 7 is provided between transmitter/receiver circuit 6 b and via hole 9 .
- switch 7 b is additionally provided between transmitter/receiver circuit 6 b and electrode pad 8 b.
- switch 7 a the switch provided between transmitter/receiver circuit 6 b and via hole 9 is denoted as switch 7 a.
- Both switches 7 a and 7 b are formed on the same silicon substrate as transmitter/receiver circuit 6 b.
- the remainder of the second exemplary embodiment is the same as the first exemplary embodiment described earlier.
- switch 7 b has the capability to eliminate the parasitic capacitance of electrode pad 8 b, thus improving the signal quality.
- Semiconductor chips 2 a, 2 b and 2 c described above may be stacked as illustrated in FIG. 3 to form semiconductor device 1 .
- FIG. 8 illustrates a third exemplary embodiment.
- switch 7 a is provided between transmitter/receiver circuit 6 b and via hole 9 and switch 7 b is additionally provided between transmitter/receiver circuit 6 b and electrode pad 8 b.
- switch 7 c for directly opening/closing a path between upper and lower electrode pads 8 b and 8 c. All of switches 7 a, 7 b and 7 c are formed on the same silicon substrate as transmitter/receiver circuit 6 b. The remainder of the third exemplary embodiment is the same as the second exemplary embodiment described earlier.
- FIG. 9 illustrates the circuit diagram shown in FIG. 8 .
- a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b and a signal change between electrode pad Sc and transmitter/receiver circuit 6 b are performed in the same manner as in the second exemplary embodiment.
- switch 7 c is closed and switches 7 a and 7 b are opened.
- transmitter/receiver circuit 6 b is not visible as a load.
- the signal does not pass through two switches 7 a and 7 b , but is allowed to pass through only one switch 7 c. Therefore, signal attenuation becomes smaller.
- Semiconductor chips 2 a, 2 b and 2 c described above may be stacked as illustrated in FIG. 3 to form semiconductor device 1 .
- FIG. 10 illustrates a fourth exemplary embodiment.
- Semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 a is formed in silicon substrate 3 a, and electrode pad 8 a is formed in or on interconnection layers 4 a formed on the transmitter/receiver circuit.
- Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 c is formed in silicon substrate 3 c, and electrode pad 8 d is formed in or on interconnection layers 4 c formed on the transmitter/receiver circuit.
- Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switches 7 a and 7 d are formed in silicon substrate 3 b.
- Electrode pad 8 b is formed in or on interconnection layer 4 b, and electrode pad 8 c is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 a that penetrates silicon substrate 3 b. Electrode pad 8 e is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 b that penetrates silicon substrate 3 b.
- electrode pad 8 b that is present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 b, but electrode pad 8 c that is present on the rear surface is connected to transmitter/receiver circuit 6 b through via hole 9 a and switch 7 a, and electrode pad 8 e that is present on the rear surface is connected to transmitter/receiver circuit 6 b through via hole 9 b and switch 7 d.
- Two switches 7 a and 7 d have the function of cutting off the interconnection so that the parasitic capacitances of via hole 9 a and 9 b are invisible from transmitter/receiver circuit 6 b and also have the function of selecting electrode pad 8 c or electrode pad 8 e.
- FIG. 11 is the circuit diagram shown in FIG. 10 .
- switch 7 a When switch 7 a is closed and switch 7 d is opened, a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b and a signal change between electrode pad 8 c and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment.
- switch 7 a When switch 7 a is opened and switch 7 d is closed, a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b and a signal exchange between electrode pad 8 e and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment.
- the data processing rate is increased by forming a one-to-many connection between the upper and lower chips.
- switches 7 a and 7 d loads on electrodes 8 c and 8 e can be isolated, thus maintaining high signal quality.
- semiconductor devices 2 a, 2 b and 2 c described above may be stacked as illustrated in FIG. 3 to form semiconductor device 1 .
- This semiconductor device is a semiconductor device wherein a one-to-many connection is formed between the upper and lower chips, and provides the above-described advantages.
- FIG. 12 illustrates a fifth exemplary embodiment.
- Semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 a is formed in silicon substrate 3 a, and electrode pad 8 a is formed in or on interconnection layer 4 a formed on the transmitter/receiver circuit.
- Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 c is formed in silicon substrate 3 c, and electrode pad 8 d is formed in or on interconnection layer 4 c formed on the transmitter/receiver circuit.
- Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switches 11 a and 11 d are formed in silicon substrate 3 b.
- electrode pad 8 b is formed in or on interconnection layer 4 b, and electrode pad 8 c is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 a that penetrates silicon substrate 3 b. Still furthermore, electrode pad 8 e is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 b that penetrates silicon substrate 3 b.
- electrode pad 8 b that is present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 b, but electrode pad 8 c that is present on the rear surface is connected to transmitter/receiver circuit 6 b through via hole 9 a and switch 11 a .
- electrode pad 8 e that is present on the rear surface is connected to transmitter/receiver circuit 6 b through via hole 9 b and switch 11 d.
- Two switches 11 a and 11 d have the function of cutting off the interconnection so that the parasitic capacitances of via hole 9 a and 9 b are invisible from transmitter/receiver circuit 6 b and also have the function of selecting electrode pad 8 c or electrode pad 8 e.
- semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 e is formed in silicon substrate 3 a, and electrode pad 8 f is formed in or on interconnection layer 4 a formed on the transmitter/receiver circuit.
- semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 f is formed in silicon substrate 3 c, and electrode pad 8 h is formed in or on interconnection layer 4 c formed on the transmitter/receiver circuit.
- Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 d, switches 11 b and 11 c are formed in silicon substrate 3 b.
- electrode pad 8 g is formed in or on interconnection layer 4 b.
- electrode pad 8 g that is present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 d, but electrode pad 8 e that is present on the rear surface is connected to transmitter/receiver circuit 6 d through via hole 9 b and switch 11 b.
- electrode pad 8 c that is present on the rear surface is connected to transmitter/receiver circuit 6 d through via hole 9 a and switch 11 c.
- Two switches 11 b and 11 c have the function of cutting off the interconnection so that the parasitic capacitances of via hole 9 a and 9 b are invisible from transmitter/receiver circuit 6 d and also have the function of selecting electrode pad 8 c or electrode pad 8 e.
- semiconductor chip 2 b formed on semiconductor chip 2 b are two transmitter/receiver circuits 6 b and 6 d and four switches 11 a , 11 b , 11 c and 11 d .
- FIG. 13 illustrates the circuit diagram shown in FIG. 12 .
- switch 11 a When switch 11 a is closed and switch 11 d is opened, a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b and a signal change between electrode pad 8 c and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment.
- switch 11 a When switch 11 a is opened and switch 11 d is closed, a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b and a signal exchange between electrode pad 8 e and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment.
- the data processing rate is increased higher than in the fourth exemplary embodiment by forming a many-to-many connection between the upper and lower chips.
- loads on electrodes 8 c and 8 e can be isolated by the switches, thus maintaining high signal quality.
- semiconductor devices 2 a, 2 b and 2 c described above may be stacked as illustrated in FIG. 3 to form semiconductor device 1 .
- This semiconductor device is a semiconductor device wherein a one-to-many connection is formed between the upper and lower chips form, and provides the above-described advantages.
- FIG. 14 illustrates a circuit diagram of a sixth exemplary embodiment.
- the sixth exemplary embodiment is a combination of the third exemplary embodiment and the fifth exemplary embodiment.
- Switch 12 b is provided between transmitter/receiver circuit 6 b and electrode pad 8 b and switch 12 g is provided between transmitter/receiver circuit 6 b and electrode pad 8 g.
- switch 12 h is provided between transmitter/receiver circuit 6 d and electrode pad 8 b and switch 12 d is provided between transmitter/receiver circuit 6 d and electrode pad 8 g.
- Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switches 12 a and 12 f are formed in silicon substrate 3 b . Furthermore, electrode pad 8 b is formed in or on interconnection layer 4 b, and electrode pad 8 c is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 a that penetrates silicon substrate 3 b. Still furthermore, electrode pad 8 e is additionally formed on the rear surface of silicon substrate 3 b through via hole 9 b that penetrates silicon substrate 3 b.
- Electrode pad 8 c is connected to transmitter/receiver circuit 6 b through via hole 9 a and switch 12 a.
- electrode pad 8 e is connected to transmitter/receiver circuit 6 b through via hole 9 b and switch 12 f.
- Two switches 12 a and 12 f have the function of cutting off the interconnection so that the parasitic capacitances of via hole 9 a and 9 b are invisible from transmitter/receiver circuit 6 b and also have the function of selecting electrode pad 8 c or electrode pad 8 e.
- semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 d, switches 12 c and 12 e are formed on silicon substrate 3 b . Furthermore, electrode pad 8 g is formed in or on interconnection layer 4 b.
- Electrode pad 8 e is connected to transmitter/receiver circuit 6 d through via hole 9 b and switch 12 c.
- electrode pad 8 c is connected to transmitter/receiver circuit 6 d through via hole 9 a and switch 12 e.
- Two switches 12 c and 12 e have the function of cutting off the interconnection so that the parasitic capacitances of via hole 9 a and 9 b are invisible from transmitter/receiver circuit 6 d and also have the function of selecting electrode pad 8 c or electrode pad 8 e.
- switches 12 h and 12 e for directly opening/closing a path between upper and lower electrode pads 8 b and 8 c and switches 12 g and 12 f for directly opening/closing a path between upper and lower electrode pads 8 g and 8 e.
- semiconductor chip 2 b formed on semiconductor chip 2 b are two transmitter/receiver circuits 6 b and 6 d and eight switches 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, 12 g and 12 h that form a crossbar switch.
- switches 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, 12 g and 12 h that form a crossbar switch.
- switches 12 a, 12 b, 12 e and 12 h are closed and switches 12 c, 12 d, 12 f and 12 g are opened, a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b and a signal exchange between electrode pad 8 c and transmitter/receiver circuit 6 b are performed in the same manner as in the third exemplary embodiment.
- switches 12 a, 12 b, 12 e and 12 h are opened and switches 12 c, 12 d, 12 f and 12 g are closed, a signal exchange between electrode pad 8 g and transmitter/receiver circuit 6 d and a signal exchange between electrode pad 8 e and transmitter/receiver circuit 6 d are performed in the same manner as in the third exemplary embodiment.
- switches 12 a, 12 c, 12 e and 12 f are closed and switches 12 b, 12 d, 12 g and 12 h are opened, a signal exchange between electrode pad 8 b and transmitter/receiver circuit 6 b, a signal exchange between electrode pad 8 c and transmitter/receiver circuit 6 b, a signal exchange between electrode pad 8 g and transmitter/receiver circuit 6 d and a signal exchange between electrode pad 8 e and transmitter/receiver circuit 6 d are performed in the same manner as in the fifth exemplary embodiment.
- the data processing rate is increased higher than in the fifth exemplary embodiment by connecting between the upper and lower chips by means of crossbar switches.
- loads on a plurality of electrodes can be isolated by the switches, thus maintaining high signal quality.
- crossbar switch configuration allows a required contact point to be selected and then opened or closed, problems such as inter-chip data collision or crosstalk are less likely to occur and transmission speed can be easily increased. These effects are significant particularly when a plurality of microcontrollers are connected to one another in the CPU-to-CPU connection.
- semiconductor devices 2 a, 2 b and 2 c described above may be stacked as illustrated in FIG. 1 to form semiconductor device 1 .
- This semiconductor device is a semiconductor device wherein the upper and lower chips are connected by crossbar switches, and provides the above-described advantages.
- FIG. 15 illustrates one-way communication in which data transmission is performed in a direction from an upper electrode to a lower electrode.
- switches 7 A and 7 B are turned on and switches 7 C and 7 D are turned off.
- data that is input from upper electrode 8 b is received and amplified by amplifier 13 A, passes through switch 7 A and contact point 10 A and is received and amplified by amplifier 13 B.
- Data that is amplified by amplifier 13 B is input to an internal circuit through switch 7 B.
- amplifiers 13 C and 13 D receive and amplify similar data.
- switches 7 C and 7 D are turned off, contention does not take place between data from amplifier 13 A and data from amplifier 13 C at contact point 10 A, and data transmission to lower electrode 8 c by way of through-via hole 9 also does not take place. As a result, a desired data transmission is performed without causing any false operation. Furthermore, by performing data transmission through amplifiers, it is possible to accurately receive a signal that is attenuated by capacitive coupling and the resistance of switch 7 A. In addition, when there are no amplifiers, transmission power needs to be increased in order to maintain the strength of a received signal to be greater than the sensitivity of a receiver circuit, but by performing data transmission through amplifiers, transmission power can be reduced.
- the transmission amplitude needs to be increased so that three or more chips can perform transmission.
- the transmission amplitude may only be as large as is required for one chip, since a signal is amplified for transmission from each one chip to another.
- the chips the number of which is the number of chips that is determined at the time of design, can be stacked.
- the number of chips to be stacked needs not be considered at the time of design.
- switches 7 A, 7 B and 7 D are turned on and switch 7 C is turned off.
- the data from upper electrode 8 b is transmitted to the internal circuit through amplifier 13 A, switch 7 A, amplifier 13 B and switch 7 B and, at the same time, is also transmitted to lower electrode 8 c through amplifier 13 A, switch 7 A, amplifier 13 D and switch 7 D.
- amplifier 13 C receives and amplifies similar data.
- switch 7 C is turned off, no conflict occurs at contact point 10 A between the data from the upper electrode and the data from the internal circuit.
- the chips can operate normally.
- a capacitive-coupling portion includes amplifier elements, as described in FIG. 15 , data transmission from upper electrode 8 b to lower electrode 8 c can also be achieved even when using amplifiers that have a switch function.
- a capacitive-coupling portion includes amplifiers that have a switch function, with reference to FIG. 17 .
- switches 7 A 1 and 7 B 1 are turned on, and switches 7 A 2 , 7 B 2 , 7 C 1 and 7 C 2 are turned off.
- data that is input to upper electrode 8 b is received and amplified by amplifier 15 A 1 , passes through switch 7 A 1 and is received and amplified by amplifier 15 B 1 .
- the data that is amplified by amplifier 15 B 1 passes through switch 7 A 1 , and is transmitted to the internal circuit through switch 7 B 1 .
- switches 7 A 2 , 7 B 2 , 7 C 1 and 7 C 2 are turned off, there is no data contention at contact point 10 A.
- the data can be transmitted normally.
- FIG. 18 illustrates a ninth exemplary embodiment.
- amplifier elements that have a switch are used in place of the amplifiers and switch elements that are separately arranged in the eighth exemplary embodiment. Since amplifier elements fitted with a switch are used in place of amplifiers and switches, the present exemplary embodiment is the same in operation as the eighth exemplary embodiment, but has advantages such as areal reductions and reductions in power consumption.
- Examples of a transmitter/receiver circuit of the first exemplary embodiment will be described using the transmitter/receiver circuit diagram of FIG. 19 and the timing chart of FIG. 20 .
- Transmission data is a non-return-to-zero (NRZ) signal which is transmitted in synchronization with the rising timing of a clock signal and is input from terminal Din to transmission buffer 18 .
- the level of a signal to be conveyed to lower electrode 8 c by way of through-via hole 9 is determined to be either the voltage of data or half the voltage of data, according to transmission clock CLK. That is, the transmission data of a transmission buffer output is conveyed to lower electrode 8 c within a high-level period of transmission clock CLK, and a voltage level half the voltage of the transmission data is conveyed to lower electrode 8 c within a low-level period of transmission clock CLK.
- switch 17 C operates according to reception clock CLK.
- reception clock CLK is at a high level
- the data of upper electrode 8 d is received by a reception buffer or by a sampling latch.
- reception clock CLK is at a low level
- a half voltage is applied to upper electrode 8 d , thereby resetting the voltage at the upper electrode.
- FIG. 21 illustrates a sampling latch-type receiver circuit as an example of receiver circuit 19 .
- a capacitive-coupling voltage is applied to terminal “in”, and a half voltage is applied to the other input terminal forming a differential pair together with terminal “in”.
- This sampling latch circuit operates in such a manner that when a CLK input is at a low level, all four wire connections of the drain terminals of nMOSs that are connected to wire connections “out” and “outb”, terminal “in” and the half-voltage input terminal are pre-charged to a power supply voltage. At this time, if the CLK input changes to a high level, then the receiver circuit senses a difference between voltages that are input to the “in” terminal and the half-voltage terminal and outputs the result of sensing as differential outputs “out” and “outb”.
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Abstract
Description
- The present invention relates to a semiconductor device for performing signal transmission between chips or between a chip and a package and the semiconductor chips thereof and, more particularly, to a semiconductor device for contactlessly performing signal transmission among a plurality of chips wherein a plurality of chips are stacked in a layered manner (three-dimensional manner) and the semiconductor chips thereof.
- In order to meet demands for increasing the speed and capacity of data transmission among a plurality of semiconductor chips and for reducing the packaging area of a semiconductor device, a variety of semiconductor devices wherein a plurality of semiconductor chips are stacked have been realized. Of these semiconductor devices, there is known a semiconductor device having a configuration in which electrodes formed on a chip are closely arranged contactlessly and oppositely to each other and inter-chip signal transmission is performed by means of capacitive coupling between the two electrodes. In this configuration, contact failure that often occurs when electrodes are brought into contact with each other, presents no problem. For this reason, this configuration is expected to come into practical use for the connection between semiconductor chips that requires multitude of electrodes, particularly among a plurality of CPUs, between a CPU and a memory, and among a plurality of memories, and for a semiconductor device in which these semiconductor chips are stacked.
-
FIG. 1 illustrates a typical semiconductor device for performing contactless signal transmission, wherein electrode A and electrode B are formed on the circuit surfaces of chip A and chip B, respectively, adjacently oppositely to each other. When electrode A is assumed to be a driver and electrode B is assumed to be a receiver, then electrostatic capacitance is present between the two electrodes, causing the two electrodes to capacitively couple with each other. That is, electrical lines of force generated from electrode A at this time reach electrode B, thereby placing the two electrodes in a state of being electrically coupled with each other (capacitive coupling). Consequently, a signal exchange is made from electrode A to electrode B. - In this related art, however, signal transmission among three or more chips is not possible, though signal transmission between opposed chips, i.e., one-to-one inter-chip transmission, is possible. When a signal is transmitted from lowermost-layer chip A to uppermost-layer chip C in cases where conventional chips are simply stacked in a three-dimensional manner as illustrated in
FIG. 2 , assuming, for example, that the chips are configured using a commonly-used semiconductor substrate (for example, a silicon substrate), then electric fields transmitted from the lowermost layer to the uppermost layer attenuate due to the effect of conductive property (loss) that the substrate of chip B located in an intermediate layer has. Therefore, it has been difficult to adequately perform signal transmission between chip A and chip C. - Hence, in order to enable a signal transmission among three or more chips,
Patent documents 1 and 2 disclose a stacked electrical circuit in which a conductive region for penetrating through the front and back sides of a silicon substrate is provided and a signal transmission is performed with the mode thereof categorized into (1) a case where a signal from a wafer stacked on an upper side is received; (2) a case where a signal is transmitted to a wafer stacked on an upper side; (3) a case where a signal from a wafer stacked on a lower side is received; and (4) a case where a signal is transmitted to a wafer stacked on a lower side. - In addition,
Patent document 3 discloses a three-layer modular electronic system, though the system is intended not for signal transmission among three or more chips but for signal transmission between two chips. In the system, electrodes are provided on upper and lower sides between the chips and a dielectric material substrate, in which an interconnection that penetrates the electrodes is formed, is sandwiched between the electrodes. - Patent document 1: Japanese Patent Laid-Open No. 56-002662
- Patent document 2: Japanese Patent Laid-Open No. 62-020362
- Patent document 3: Published Japanese translations of PCT international publication No. 09-504908
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Patent documents 1 and 2 do not disclose any specific exemplary embodiments with regard to circuits for performing transmission/reception and switching signals between the upper and lower sides. Accordingly, although a contactless method is employed, theses patent documents could not achieve an increase in the speed and capacity of inter-chip data transmission and a reduction in the packaging size of a semiconductor device. In addition, althoughPatent document 3 illustrates inFIG. 8 an embodiment in which a one-to-many connection is made between chips by using an interconnection within the dielectric material substrate, the exemplary embodiment suffers from a problem in which the operation speed decreases because a circuit of branch destination serves as a load on the circuit operation. - It is an object of the present invention to provide a semiconductor device and a semiconductor chip, which are constructed to have a high reliable interconnection by stacking three or more layers of chips without contacts therebetween, wherein for the semiconductor chip and the semiconductor device, there is a particularly strong demand to increase the speed and capacity of data transmission among a plurality of CPUs, between a CPU and a memory, and among a plurality of memories and the like, and there is a particularly strong demand to reduce the size of the semiconductor device.
- A semiconductor chip according to the present invention includes a silicon substrate on which a first signal transmission circuit and a first changeover switch are formed; a wiring layer formed on the silicon substrate; and a first capacitive-coupling upper electrode formed on the wiring layer; wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole penetrating the silicon substrate, the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, and the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and the first changeover switch.
- A semiconductor device according to the present invention comprises a semiconductor chip including a silicon substrate on which a first signal transmission circuit and a first changeover switch are formed; an interconnection layer formed on the silicon substrate; and a first capacitive-coupling upper electrode formed on the interconnection layer; wherein the first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate, the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, and the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and the first changeover switch.
- According to the present invention, in a semiconductor device comprising three or more layers of semiconductor chips, a signal transmission between respective two semiconductor chips is controlled and a signal transmission between predetermined electrodes within predetermined semiconductor chips is realized. In addition, since a signal is transmitted through a capacitive coupling, there is no need to ensure electrical conductivity as in the case of contact-type electrodes, thereby increasing the tolerance of positioning accuracy between semiconductor chips.
-
FIG. 1 is a cross-sectional view illustrating the configuration of a related semiconductor device for performing signal transmission by means of capacitive coupling between two chips. -
FIG. 2 is a cross-sectional view illustrating the configuration of a related semiconductor device for performing signal transmission by means of capacitive coupling among three chips. -
FIG. 3 is a schematic view illustrating a semiconductor device according to an exemplary embodiment of the present invention in which three semiconductor chips are stacked. -
FIG. 4 is an enlarged view of an electrode pad portion inFIG. 3 , illustrating the configuration of a first exemplary embodiment. -
FIG. 5 is a circuit diagram ofsemiconductor chip 2 b illustrated inFIG. 4 . -
FIG. 6 is another enlarged view of the electrode pad portion inFIG. 3 , illustrating the configuration of a second exemplary embodiment. -
FIG. 7 is a circuit diagram ofsemiconductor chip 2 b illustrated inFIG. 6 . -
FIG. 8 is another enlarged view of the electrode pad portion inFIG. 3 , illustrating the configuration of a third exemplary embodiment. -
FIG. 9 is a circuit diagram ofsemiconductor chip 2 b illustrated inFIG. 8 . -
FIG. 10 is another enlarged view of the electrode pad portion inFIG. 3 , illustrating the configuration-of a fourth exemplary embodiment. -
FIG. 11 is a circuit diagram ofsemiconductor chip 2 b illustrated inFIG. 10 . -
FIG. 12 is another enlarged view of the electrode pad portion inFIG. 3 , illustrating the configuration of a fifth exemplary embodiment. -
FIG. 13 is a circuit diagram ofsemiconductor chip 2 b illustrated inFIG. 12 . -
FIG. 14 is a circuit diagram ofsemiconductor chip 2 b of a sixth exemplary embodiment. -
FIG. 15 is a schematic view to explain the operation of one-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and a capacitive-coupling portion includes an amplifier element. -
FIG. 16 is a schematic view to explain the operation of one-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and a capacitive-coupling portion includes an amplifier fitted with a switch function. -
FIG. 17 is a schematic view to explain the operation of two-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and from the lower electrode to the upper electrode and a capacitive-coupling portion includes an amplifier element. -
FIG. 18 is a schematic view to explain the operation of two-way communication in which the flow of data transmission is in a direction from an upper electrode to a lower electrode and from the lower electrode to the upper electrode and a capacitive-coupling portion includes an amplifier having a switch function. -
FIG. 19 is a diagram of a transmitter/receiver circuit of the first exemplary embodiment. -
FIG. 20 is a schematic view illustrating a timing chart of a transmitter/receiver circuit of the first exemplary embodiment. -
FIG. 21 is a block diagram illustrating a sampling latch-type receiver circuit as an example of a receiver circuit of the first exemplary embodiment. -
- 1 semiconductor device
- 2 a, 2 b, 2 c semiconductor chip
- 3 a, 3 b, 3 c silicon substrate
- 4 a, 4 b, 4 c interconnection layer
- 5 a, 5 b adhesion layer
- 6 a, 6 b, 6 c, 6 d, 6 e, 6 f transmitter/receiver circuit
- 7, 7 a, 7 b, 7 c, 7 d, 11 a, 11 b, 11 c, 11 d, 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, 12 g, 12 h, 7A, 7B, 7C, 7D, 7A1, 7B1, 7C1, 7A2, 7B2, 7C2, 17A, 17B, 17C switch
- 8 a, 8 b, 8 c, 8 d, 8 e, 8 f, 8 g, 8 h electrode pad
- 9, 9 a, 9 b through-via hole
- 10 terminal leading to internal circuit
- 10A contact point
- 13A, 13B, 13C, 13D, 15A1, 15B1, 15C1, 15A2, 15B2, 15C2 amplifier
- 14A, 14B, 14C, 14D, 16A1, 16B1, 16C1, 16A2, 16B2, 16C2 amplifier with switch
- 18 transmission buffer
- 19 reception buffer, sampling latch
- Exemplary embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings.
-
FIG. 3 illustratessemiconductor device 1 in which threesemiconductor chips semiconductor chips semiconductor chip 2 b, an electrode pad is also formed on the rear surface thereof. Thissemiconductor chip 2 b makes it possible to exchange a signal among semiconductor chips even if three or more semiconductor chips are stacked. -
FIG. 4 is an enlarged view of an electrode pad portion inFIG. 3 , and illustrates the configuration of a first exemplary embodiment.Semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 a is formed insilicon substrates 3 a, andelectrode pad 8 a is formed in or oninterconnection layers 4 a formed on the transmitter/receiver circuit.Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 c is formed insilicon substrates 3 c, andelectrode pad 8 d is formed in or oninterconnection layers 4 c formed on the transmitter/receiver circuit.Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b,switch 7 is formed insilicon substrate 3 b. In addition,electrode pad 8 b is formed in or oninterconnection layer 4 b andelectrode pad 8 c is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 that penetratessilicon substrate 3 b. - In
semiconductor chip 2 b,electrode pad 8 b present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 b, whereaselectrode pad 8 c present on the rear surface is connected to the transmitter/receiver circuit through viahole 9 andswitch 7. - Operation of the present invention will be described with reference to
FIG. 5 . -
FIG. 5 illustrates the circuit diagram ofsemiconductor chip 2 b previously shown. - When a signal is input from
electrode pad 8 b,switch 7 is opened. As a result, the signal that is input fromelectrode pad 8 b is supplied to transmitter/receiver circuit 6 b. On the other hand, when a signal from the transmitter/receiver circuit is input toelectrode pad 8 c,switch 7 is closed. Although each of transmitter/receiver circuits - As can be seen from the circuit diagram of
FIG. 5 , viahole 9 is connected toelectrode pad 8 c. When a via hole is formed on a silicon substrate, a thin insulating layer must be provided on a boundary face between the silicon and the via hole, unlike when a via hole is formed on an organic substrate. Consequently, the parasitic capacitance of the via hole may amount to as large as several pF, which value is not negligible, as compared with capacitance formed between electrode pads of adjacent semiconductor chips. For this reason, in the present invention,switch 7 is provided in order to make the parasitic capacitance of this viahole 9 invisible from a signal that is input fromelectrode pad 8 b. - On the other hand, when a signal is output from transmitter/
receiver circuit 6 b toelectrode pad 8 c,electrode pad 8 b, as well as viahole 9 andelectrode pad 8 c, are visible from transmitter/receiver circuit 6 b. However, the parasitic capacitance ofelectrode pad 8 b is sufficiently small compared with that of viahole 9 and hence is negligible. -
Interposing switch 7 not only between transmitter/receiver circuit 6 b andelectrode pad 8 c but also between transmitter/receiver circuit 6 b andelectrode pad 8 b is conceivable. In the present exemplary embodiment, in order to achieve low power consumption, a switch is provided only in a portion that connects to the via hole and that has the largest parasitic capacitance. - When a signal is input from
electrode pad 8 c,switch 7 is closed. As a result, the signal that is input fromelectrode pad 8 c is supplied to transmitter/receiver circuit 6 b. On the other hand, when a signal is output from the transmitter/receiver circuit toelectrode pad 8 b,switch 7 is opened. -
Semiconductor chips FIG. 3 to formsemiconductor device 1. -
FIG. 6 illustrates a second exemplary embodiment. - In the first exemplary embodiment,
switch 7 is provided between transmitter/receiver circuit 6 b and viahole 9. In the present exemplary embodiment, however,switch 7 b is additionally provided between transmitter/receiver circuit 6 b andelectrode pad 8 b. Note that the switch provided between transmitter/receiver circuit 6 b and viahole 9 is denoted asswitch 7 a. Bothswitches receiver circuit 6 b. The remainder of the second exemplary embodiment is the same as the first exemplary embodiment described earlier. - Operation of the second exemplary embodiment will be described with reference to
FIG. 7 . When a signal is input fromelectrode pad 8 b,switch 7 b is closed andswitch 7 a is opened. As a result, viahole 9 having large parasitic capacitance is invisible fromelectrode pad 8 b. On the other hand, when a signal is output from transmitter/receiver circuit 6 b toelectrode pad 8 c,switch 7 b is opened and switch 7 a is closed. As a result, the parasitic capacitance ofelectrode pad 8 b becomes invisible. - When a signal is input from
electrode pad 8 c,switch 7 a is closed andswitch 7 b is opened. As a result, the parasitic capacitance ofelectrode pad 8 b becomes invisible. On the other hand, when a signal is output from transmitter/receiver circuit 6 b toelectrode pad 8 b,switch 7 a is opened andswitch 7 b is closed. As a result, viahole 9 having large parasitic capacitance is invisible fromelectrode pad 8 b. - When a signal is input from
electrode pad 8 c, the parasitic capacitance ofelectrode pad 8 b, as well as the parasitic capacitance of viahole 9, is visible in the first exemplary embodiment. Accordingly, there is a possibility, particularly when chips are connected in a multistage manner beyondelectrode pad 8 b, that this parasitic capacitance becomes larger, degrading signal quality. In the present exemplary embodiment, however,switch 7 b has the capability to eliminate the parasitic capacitance ofelectrode pad 8 b, thus improving the signal quality. -
Semiconductor chips FIG. 3 to formsemiconductor device 1. -
FIG. 8 illustrates a third exemplary embodiment. - In the second exemplary embodiment, switch 7 a is provided between transmitter/
receiver circuit 6 b and viahole 9 andswitch 7 b is additionally provided between transmitter/receiver circuit 6 b andelectrode pad 8 b. In the present exemplary embodiment, however, there is providedswitch 7 c for directly opening/closing a path between upper andlower electrode pads switches receiver circuit 6 b. The remainder of the third exemplary embodiment is the same as the second exemplary embodiment described earlier. -
FIG. 9 illustrates the circuit diagram shown inFIG. 8 . - A signal exchange between
electrode pad 8 b and transmitter/receiver circuit 6 b and a signal change between electrode pad Sc and transmitter/receiver circuit 6 b are performed in the same manner as in the second exemplary embodiment. When a signal is directly transmitted betweenelectrode pad 8 b andelectrode pad 8 c,switch 7 c is closed and switches 7 a and 7 b are opened. In this case, transmitter/receiver circuit 6 b is not visible as a load. - The same signal transmission as described above is possible in the first and second exemplary embodiments. In that case, since the transmitter/receiver circuit is visible as a load, signal attenuation becomes accordingly large.
- In the present exemplary embodiment, particularly when a signal needs to be directly transmitted from
semiconductor chip 2 a tosemiconductor chip 2 c or fromsemiconductor chip 2 c tosemiconductor chip 2 a, the signal does not pass through twoswitches switch 7 c. Therefore, signal attenuation becomes smaller. -
Semiconductor chips FIG. 3 to formsemiconductor device 1. -
FIG. 10 illustrates a fourth exemplary embodiment. -
Semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 a is formed insilicon substrate 3 a, andelectrode pad 8 a is formed in or oninterconnection layers 4 a formed on the transmitter/receiver circuit.Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 c is formed insilicon substrate 3 c, andelectrode pad 8 d is formed in or oninterconnection layers 4 c formed on the transmitter/receiver circuit.Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switches 7 a and 7 d are formed insilicon substrate 3 b.Electrode pad 8 b is formed in or oninterconnection layer 4 b, andelectrode pad 8 c is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 a that penetratessilicon substrate 3 b.Electrode pad 8 e is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 b that penetratessilicon substrate 3 b. - In
semiconductor chip 2 b,electrode pad 8 b that is present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 b, butelectrode pad 8 c that is present on the rear surface is connected to transmitter/receiver circuit 6 b through viahole 9 a andswitch 7 a, andelectrode pad 8 e that is present on the rear surface is connected to transmitter/receiver circuit 6 b through viahole 9 b andswitch 7 d. - Two
switches hole receiver circuit 6 b and also have the function of selectingelectrode pad 8 c orelectrode pad 8 e. -
FIG. 11 is the circuit diagram shown inFIG. 10 . - When
switch 7 a is closed andswitch 7 d is opened, a signal exchange betweenelectrode pad 8 b and transmitter/receiver circuit 6 b and a signal change betweenelectrode pad 8 c and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment. - When
switch 7 a is opened andswitch 7 d is closed, a signal exchange betweenelectrode pad 8 b and transmitter/receiver circuit 6 b and a signal exchange betweenelectrode pad 8 e and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment. - In the present exemplary embodiment, the data processing rate is increased by forming a one-to-many connection between the upper and lower chips. In addition, by providing
switches electrodes -
Semiconductor chips FIG. 3 to formsemiconductor device 1. This semiconductor device is a semiconductor device wherein a one-to-many connection is formed between the upper and lower chips, and provides the above-described advantages. -
FIG. 12 illustrates a fifth exemplary embodiment. -
Semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 a is formed insilicon substrate 3 a, andelectrode pad 8 a is formed in or oninterconnection layer 4 a formed on the transmitter/receiver circuit.Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 c is formed insilicon substrate 3 c, andelectrode pad 8 d is formed in or oninterconnection layer 4 c formed on the transmitter/receiver circuit.Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switches 11 a and 11 d are formed insilicon substrate 3 b. Furthermore,electrode pad 8 b is formed in or oninterconnection layer 4 b, andelectrode pad 8 c is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 a that penetratessilicon substrate 3 b. Still furthermore,electrode pad 8 e is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 b that penetratessilicon substrate 3 b. - In
semiconductor chip 2 b,electrode pad 8 b that is present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 b, butelectrode pad 8 c that is present on the rear surface is connected to transmitter/receiver circuit 6 b through viahole 9 a and switch 11 a. In addition,electrode pad 8 e that is present on the rear surface is connected to transmitter/receiver circuit 6 b through viahole 9 b and switch 11 d. - Two switches 11 a and 11 d have the function of cutting off the interconnection so that the parasitic capacitances of via
hole receiver circuit 6 b and also have the function of selectingelectrode pad 8 c orelectrode pad 8 e. - In addition,
semiconductor chip 2 a is configured such that at least one transmitter/receiver circuit 6 e is formed insilicon substrate 3 a, andelectrode pad 8 f is formed in or oninterconnection layer 4 a formed on the transmitter/receiver circuit.Semiconductor chip 2 c is configured such that at least one transmitter/receiver circuit 6 f is formed insilicon substrate 3 c, andelectrode pad 8 h is formed in or oninterconnection layer 4 c formed on the transmitter/receiver circuit.Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 d, switches 11 b and 11 c are formed insilicon substrate 3 b. Furthermore,electrode pad 8 g is formed in or oninterconnection layer 4 b. - In
semiconductor chip 2 b,electrode pad 8 g that is present on the circuit surface thereof is directly connected to transmitter/receiver circuit 6 d, butelectrode pad 8 e that is present on the rear surface is connected to transmitter/receiver circuit 6 d through viahole 9 b and switch 11 b. In addition,electrode pad 8 c that is present on the rear surface is connected to transmitter/receiver circuit 6 d through viahole 9 a andswitch 11 c. - Two switches 11 b and 11 c have the function of cutting off the interconnection so that the parasitic capacitances of via
hole receiver circuit 6 d and also have the function of selectingelectrode pad 8 c orelectrode pad 8 e. - That is, formed on
semiconductor chip 2 b are two transmitter/receiver circuits switches right electrode pads -
FIG. 13 illustrates the circuit diagram shown inFIG. 12 . - When switch 11 a is closed and switch 11 d is opened, a signal exchange between
electrode pad 8 b and transmitter/receiver circuit 6 b and a signal change betweenelectrode pad 8 c and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment. - When switch 11 a is opened and switch 11 d is closed, a signal exchange between
electrode pad 8 b and transmitter/receiver circuit 6 b and a signal exchange betweenelectrode pad 8 e and transmitter/receiver circuit 6 b are performed in the same manner as in the first exemplary embodiment. - When
switch 11 b is closed and switch 11 c is opened, a signal exchange betweenelectrode pad 8 g and transmitter/receiver circuit 6 d and a signal exchange betweenelectrode pad 8 e and transmitter/receiver circuit 6 d are performed in the same manner as in the first exemplary embodiment. - When
switch 11 b is opened and switch 11 c is closed, a signal exchange betweenelectrode pad 8 g and transmitter/receiver circuit 6 d and a signal exchange betweenelectrode pad 8 c and transmitter/receiver circuit 6 d are performed in the same manner as in the first exemplary embodiment. - In the present exemplary embodiment, the data processing rate is increased higher than in the fourth exemplary embodiment by forming a many-to-many connection between the upper and lower chips. In addition, loads on
electrodes -
Semiconductor chips FIG. 3 to formsemiconductor device 1. This semiconductor device is a semiconductor device wherein a one-to-many connection is formed between the upper and lower chips form, and provides the above-described advantages. -
FIG. 14 illustrates a circuit diagram of a sixth exemplary embodiment. The sixth exemplary embodiment is a combination of the third exemplary embodiment and the fifth exemplary embodiment. -
Switch 12 b is provided between transmitter/receiver circuit 6 b andelectrode pad 8 b and switch 12 g is provided between transmitter/receiver circuit 6 b andelectrode pad 8 g. In addition, switch 12 h is provided between transmitter/receiver circuit 6 d andelectrode pad 8 b and switch 12 d is provided between transmitter/receiver circuit 6 d andelectrode pad 8 g. -
Semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 b, switches 12 a and 12 f are formed insilicon substrate 3 b. Furthermore,electrode pad 8 b is formed in or oninterconnection layer 4 b, andelectrode pad 8 c is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 a that penetratessilicon substrate 3 b. Still furthermore,electrode pad 8 e is additionally formed on the rear surface ofsilicon substrate 3 b through viahole 9 b that penetratessilicon substrate 3 b. -
Electrode pad 8 c is connected to transmitter/receiver circuit 6 b through viahole 9 a and switch 12 a. In addition,electrode pad 8 e is connected to transmitter/receiver circuit 6 b through viahole 9 b and switch 12 f. - Two switches 12 a and 12 f have the function of cutting off the interconnection so that the parasitic capacitances of via
hole receiver circuit 6 b and also have the function of selectingelectrode pad 8 c orelectrode pad 8 e. - In addition,
semiconductor chip 2 b is configured such that in addition to at least one transmitter/receiver circuit 6 d, switches 12 c and 12 e are formed onsilicon substrate 3 b. Furthermore,electrode pad 8 g is formed in or oninterconnection layer 4 b. -
Electrode pad 8 e is connected to transmitter/receiver circuit 6 d through viahole 9 b and switch 12 c. In addition,electrode pad 8 c is connected to transmitter/receiver circuit 6 d through viahole 9 a andswitch 12 e. - Two switches 12 c and 12 e have the function of cutting off the interconnection so that the parasitic capacitances of via
hole receiver circuit 6 d and also have the function of selectingelectrode pad 8 c orelectrode pad 8 e. - In the present exemplary embodiment, there are provided
switches lower electrode pads lower electrode pads - That is, formed on
semiconductor chip 2 b are two transmitter/receiver circuits switches right electrode pads - When switches 12 a, 12 b, 12 e and 12 h are closed and switches 12 c, 12 d, 12 f and 12 g are opened, a signal exchange between
electrode pad 8 b and transmitter/receiver circuit 6 b and a signal exchange betweenelectrode pad 8 c and transmitter/receiver circuit 6 b are performed in the same manner as in the third exemplary embodiment. - When switches 12 a, 12 b, 12 e and 12 h are opened and
switches electrode pad 8 g and transmitter/receiver circuit 6 d and a signal exchange betweenelectrode pad 8 e and transmitter/receiver circuit 6 d are performed in the same manner as in the third exemplary embodiment. - When switches 12 a, 12 c, 12 e and 12 f are closed and switches 12 b, 12 d, 12 g and 12 h are opened, a signal exchange between
electrode pad 8 b and transmitter/receiver circuit 6 b, a signal exchange betweenelectrode pad 8 c and transmitter/receiver circuit 6 b, a signal exchange betweenelectrode pad 8 g and transmitter/receiver circuit 6 d and a signal exchange betweenelectrode pad 8 e and transmitter/receiver circuit 6 d are performed in the same manner as in the fifth exemplary embodiment. - In the present exemplary embodiment, the data processing rate is increased higher than in the fifth exemplary embodiment by connecting between the upper and lower chips by means of crossbar switches. In addition, loads on a plurality of electrodes can be isolated by the switches, thus maintaining high signal quality.
- Since the crossbar switch configuration allows a required contact point to be selected and then opened or closed, problems such as inter-chip data collision or crosstalk are less likely to occur and transmission speed can be easily increased. These effects are significant particularly when a plurality of microcontrollers are connected to one another in the CPU-to-CPU connection.
-
Semiconductor chips FIG. 1 to formsemiconductor device 1. This semiconductor device is a semiconductor device wherein the upper and lower chips are connected by crossbar switches, and provides the above-described advantages. - When a plurality of chips are stacked and inter-chip data is transmitted and received through capacitive coupling, the following problems occur: 1) a signal to be transmitted/received has a differential waveform; 2) when a signal passes through a through-via hole, the signal is affected by the parasitic capacitance at the through-via hole and the strength of a received signal decreases; and 3) since a signal is transmitted through
switches 12 a to 12 h shown in, for example, the sixth exemplary embodiment, the strength of the received signal is decreased by the resistances ofswitches 12 a to 12 h. A description will now be made of a method to solve these problems by using amplifier elements in data transmission/reception through capacitive coupling, with reference toFIG. 15 .FIG. 15 illustrates one-way communication in which data transmission is performed in a direction from an upper electrode to a lower electrode. - First, when data is transmitted from
upper electrode 8 b toterminal 10 for transmitter/receiver circuit 6 b or the like, switches 7A and 7B are turned on andswitches 7C and 7D are turned off. As a result, data that is input fromupper electrode 8 b is received and amplified byamplifier 13A, passes throughswitch 7A andcontact point 10A and is received and amplified byamplifier 13B. Data that is amplified byamplifier 13B is input to an internal circuit throughswitch 7B. At this time,amplifiers switches 7C and 7D are turned off, contention does not take place between data fromamplifier 13A and data fromamplifier 13C atcontact point 10A, and data transmission tolower electrode 8 c by way of through-viahole 9 also does not take place. As a result, a desired data transmission is performed without causing any false operation. Furthermore, by performing data transmission through amplifiers, it is possible to accurately receive a signal that is attenuated by capacitive coupling and the resistance ofswitch 7A. In addition, when there are no amplifiers, transmission power needs to be increased in order to maintain the strength of a received signal to be greater than the sensitivity of a receiver circuit, but by performing data transmission through amplifiers, transmission power can be reduced. - Next, when data from the internal circuit is transferred to
lower electrode 8 c, switches 7C and 7D are turned on andswitches amplifier 13C, passes through switch 7C andcontact point 10A, and is then transmitted toamplifier 13D. The transmitted data is received and amplified byamplifier 13D, and output to lowerelectrode 8 c throughswitch 7D and through-viahole 9. At this time, sinceamplifier 13B is connected to contactpoint 10A,amplifier 13B receives and amplifies similar data. However, sinceswitch 7B is turned off, there is no occurrence of data contention atterminal 10 that is connected to the internal circuit and no false operation is caused. In addition, although data that is input toupper electrode 8 b is received and amplified byamplifier 13A, there is no occurrence of data contention atcontact point 10A and no operation is caused becauseswitch 7A is turned off. As a result, a desired data transmission is performed in a direction from the internal circuit towardlower electrode 8 c. Furthermore, since the signal is amplified byamplifier 13D, it is possible to convey the signal received atupper electrode 8 b to lowerelectrode 8 c with the signal being amplified. Consequently, it is possible to transmit a signal to a lower chip with the signal being fully amplified, although the signal transmission is executed by means of capacitive coupling. When three or more chips are stacked, if there are no amplifiers, the transmission amplitude needs to be increased so that three or more chips can perform transmission. When data transmission is performed through amplifiers, however, the transmission amplitude may only be as large as is required for one chip, since a signal is amplified for transmission from each one chip to another. In addition, when there are no amplifiers, only the chips, the number of which is the number of chips that is determined at the time of design, can be stacked. When data transmission is performed through amplifiers, however, the number of chips to be stacked needs not be considered at the time of design. - When data from an upper electrode is transmitted to both the internal circuit and
lower electrode 8 c, switches 7A, 7B and 7D are turned on and switch 7C is turned off. As a result, the data fromupper electrode 8 b is transmitted to the internal circuit throughamplifier 13A, switch 7A,amplifier 13B andswitch 7B and, at the same time, is also transmitted tolower electrode 8 c throughamplifier 13A, switch 7A,amplifier 13D and switch 7D. At this time,amplifier 13C receives and amplifies similar data. However, since switch 7C is turned off, no conflict occurs atcontact point 10A between the data from the upper electrode and the data from the internal circuit. Thus, the chips can operate normally. - An explanation will now be made of the operation of one-way communication in which data transmission is performed in a direction from an upper electrode to a lower electrode and a capacitive-coupling portion includes amplifiers with a switch function, with reference to
FIG. 16 . - When a capacitive-coupling portion includes amplifier elements, as described in
FIG. 15 , data transmission fromupper electrode 8 b to lowerelectrode 8 c can also be achieved even when using amplifiers that have a switch function. - When data is transmitted from
upper electrode 8 b to the internal circuit, for example, it is possible to perform the data transmission normally, while avoiding data contention, by turning onamplifiers FIG. 15 . Data transmission from the internal circuit to lowerelectrode 8 c and data transmission fromupper electrode 8 b to both the internal circuit andlower electrode 8 c can be performed normally, while avoiding data contention in the same manner as inFIG. 15 . - By connecting an amplifier in series with a switch or by using an amplifier with a switch, a reduction in amplitude due to the resistance of a switch can be improved thereby enhancing signal quality.
- An explanation will now be made of operation in a case in which a flow of data is both in a direction from an upper electrode to a lower electrode and in a direction from a lower electrode to an upper electrode, and a capacitive-coupling portion includes amplifiers that have a switch function, with reference to
FIG. 17 . - When data is transmitted from
upper electrode 8 b to an internal circuit, switches 7A1 and 7B1 are turned on, and switches 7A2, 7B2, 7C1 and 7C2 are turned off. As a result, data that is input toupper electrode 8 b is received and amplified by amplifier 15A1, passes through switch 7A1 and is received and amplified by amplifier 15B1. The data that is amplified by amplifier 15B1 passes through switch 7A1, and is transmitted to the internal circuit through switch 7B1. At this time, since switches 7A2, 7B2, 7C1 and 7C2 are turned off, there is no data contention atcontact point 10A. Thus, the data can be transmitted normally. On the other hand, when data is transmitted from the internal circuit toupper electrode 8 b, data transmission can be performed, without causing any data contention, by turning on switches 7B2 and 7A2 and turning off switches 7A1, 7B1, 7C1 and 7C2. Similarly, when data is transmitted fromupper electrode 8 b to lowerelectrode 8 c or fromlower electrode 8 c toupper electrode 8 b, data transmission can be performed, as in the case of transmitting data fromupper electrode 8 b to lowerelectrode 8 c, by correctly selecting switches to be turned on and to be turned off. In addition, it is also possible to simultaneously transmit data from one electrode toward two electrodes, as in the case of transmission fromupper electrode 8 b to both the internal circuit andlower electrode 8 c. -
FIG. 18 illustrates a ninth exemplary embodiment. In the present exemplary embodiment, amplifier elements that have a switch are used in place of the amplifiers and switch elements that are separately arranged in the eighth exemplary embodiment. Since amplifier elements fitted with a switch are used in place of amplifiers and switches, the present exemplary embodiment is the same in operation as the eighth exemplary embodiment, but has advantages such as areal reductions and reductions in power consumption. - Examples of a transmitter/receiver circuit of the first exemplary embodiment will be described using the transmitter/receiver circuit diagram of
FIG. 19 and the timing chart ofFIG. 20 . - Transmission data is a non-return-to-zero (NRZ) signal which is transmitted in synchronization with the rising timing of a clock signal and is input from terminal Din to
transmission buffer 18. The level of a signal to be conveyed tolower electrode 8 c by way of through-viahole 9 is determined to be either the voltage of data or half the voltage of data, according to transmission clock CLK. That is, the transmission data of a transmission buffer output is conveyed tolower electrode 8 c within a high-level period of transmission clock CLK, and a voltage level half the voltage of the transmission data is conveyed tolower electrode 8 c within a low-level period of transmission clock CLK. Only the information on transition of the data atlower electrode 8 c is conveyed toupper electrode 8 d coupled withlower electrode 8 c through capacitive coupling, due to the capacitive coupling. For example, when the transmission data is “1”,lower electrode 8 c is set to “1” at the rising timing of transmission clock CLK and an upward-going pulse is conveyed toupper electrode 8 d according to the data transition oflower electrode 8 c from “½” to “1”.Lower electrode 8 c is set to “½” at the falling timing of transmission clock CLK and a downward-going pulse is conveyed toupper electrode 8 d according to the data transition oflower electrode 8 c from “1” to “½”. Conversely, when the transmission data is “0”,lower electrode 8 c is set to “0” at the rising timing of transmission clock CLK, and a downward-going pulse is conveyed toupper electrode 8 d according to the data transition oflower electrode 8 c from “½” to “0”.Lower electrode 8 c is set to “½” at the falling timing of transmission clock CLK and an upward-going pulse is conveyed toupper electrode 8 d according to the data transition oflower electrode 8 c from “0” to “½”. In this way, a transmission data of “1” or “0” is converted to an upward-going pulse or a downward-going pulse atupper electrode 8 d at the rising timing of transmission clock CLK. The transmission data is thus conveyed toupper electrode 8 d. - On the other hand, in a receiving-side circuit including
upper electrode 8 d,switch 17C operates according to reception clock CLK. When reception clock CLK is at a high level, the data ofupper electrode 8 d is received by a reception buffer or by a sampling latch. When reception clock CLK is at a low level, a half voltage is applied toupper electrode 8 d, thereby resetting the voltage at the upper electrode. -
FIG. 21 illustrates a sampling latch-type receiver circuit as an example ofreceiver circuit 19. - A capacitive-coupling voltage is applied to terminal “in”, and a half voltage is applied to the other input terminal forming a differential pair together with terminal “in”. This sampling latch circuit operates in such a manner that when a CLK input is at a low level, all four wire connections of the drain terminals of nMOSs that are connected to wire connections “out” and “outb”, terminal “in” and the half-voltage input terminal are pre-charged to a power supply voltage. At this time, if the CLK input changes to a high level, then the receiver circuit senses a difference between voltages that are input to the “in” terminal and the half-voltage terminal and outputs the result of sensing as differential outputs “out” and “outb”.
- Although the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to the above-described exemplary embodiments. Various modifications that can be understood to those skilled in the art may be made to the constitution and details of the present invention within the scope thereof.
- This application claims the right of priority based on Japanese Patent Application No. 2007-060352, filed on Mar. 9, 2007, the entire content of which is incorporated herein by reference.
Claims (16)
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PCT/JP2008/053612 WO2008111409A1 (en) | 2007-03-09 | 2008-02-29 | Semiconductor chip, and semiconductor device |
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US10826536B1 (en) * | 2019-10-03 | 2020-11-03 | International Business Machines Corporation | Inter-chip data transmission system using single-ended transceivers |
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JP5280880B2 (en) * | 2009-02-10 | 2013-09-04 | 株式会社日立製作所 | Semiconductor integrated circuit device |
JP5641701B2 (en) * | 2009-03-25 | 2014-12-17 | 株式会社東芝 | 3D semiconductor integrated circuit |
JPWO2010119625A1 (en) * | 2009-04-13 | 2012-10-22 | 日本電気株式会社 | Semiconductor device and test method thereof |
JP7282329B2 (en) * | 2019-10-04 | 2023-05-29 | 本田技研工業株式会社 | semiconductor equipment |
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JPS562662A (en) | 1979-06-22 | 1981-01-12 | Hitachi Ltd | Laminated electric circuit |
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JPS6220362A (en) * | 1985-07-19 | 1987-01-28 | Hitachi Ltd | Signal transmission circuit for laminated electric circuit |
JPH05190770A (en) | 1992-01-09 | 1993-07-30 | Fujitsu Ltd | Semiconductor device |
US6728113B1 (en) | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
US5818112A (en) | 1994-11-15 | 1998-10-06 | Siemens Aktiengesellschaft | Arrangement for capacitive signal transmission between the chip layers of a vertically integrated circuit |
TW419810B (en) | 1998-06-18 | 2001-01-21 | Hitachi Ltd | Semiconductor device |
JP4063796B2 (en) * | 2004-06-30 | 2008-03-19 | 日本電気株式会社 | Multilayer semiconductor device |
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US7906846B2 (en) * | 2005-09-06 | 2011-03-15 | Nec Corporation | Semiconductor device for implementing signal transmission and/or power supply by means of the induction of a coil |
US20090065871A1 (en) * | 2005-09-23 | 2009-03-12 | Megica Corporation | Semiconductor chip and process for forming the same |
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