WO2008105100A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2008105100A1
WO2008105100A1 PCT/JP2007/053836 JP2007053836W WO2008105100A1 WO 2008105100 A1 WO2008105100 A1 WO 2008105100A1 JP 2007053836 W JP2007053836 W JP 2007053836W WO 2008105100 A1 WO2008105100 A1 WO 2008105100A1
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WO
WIPO (PCT)
Prior art keywords
layer
composition
chemical formula
oxide
composition parameter
Prior art date
Application number
PCT/JP2007/053836
Other languages
English (en)
French (fr)
Inventor
Wensheng Wang
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/053836 priority Critical patent/WO2008105100A1/ja
Priority to PCT/JP2008/051090 priority patent/WO2008105204A1/ja
Priority to JP2009501154A priority patent/JP5104850B2/ja
Priority to CN2008800065920A priority patent/CN101641782B/zh
Priority to KR1020097016930A priority patent/KR101084408B1/ko
Publication of WO2008105100A1 publication Critical patent/WO2008105100A1/ja
Priority to US12/548,911 priority patent/US8405188B2/en
Priority to US13/780,177 priority patent/US8664011B2/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/65Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

キャパシタ上部電極Q2は、組成パラメータx1を使って化学式AOx1(A:金属元素)で表され実際の組成が組成パラメータx2を使って化学式AOx2で表される第1酸化物よりなる第1の層57と、第1の層57上に形成され、組成パラメータy1を使って化学式BOy1で表され実際の組成が組成パラメータy2を使って化学式BOy2(B:金属元素)で表される第2酸化物であって、石垣状或いは柱状に接合される結晶からなり、第1の層57より酸化の割合が高く構成され、組成パラメータx1、x2、y1およびy2の間には、関係y2/y1>x1/x1が成立する第2の層58と、第2の層58上形成され、貴金属膜或いは貴金属を含む合金よりなる第3の層59とを有する。
PCT/JP2007/053836 2007-02-28 2007-02-28 半導体装置及びその製造方法 WO2008105100A1 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法
PCT/JP2008/051090 WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法
JP2009501154A JP5104850B2 (ja) 2007-02-28 2008-01-25 半導体装置の製造方法
CN2008800065920A CN101641782B (zh) 2007-02-28 2008-01-25 半导体器件及其制造方法
KR1020097016930A KR101084408B1 (ko) 2007-02-28 2008-01-25 반도체 장치 및 그 제조방법
US12/548,911 US8405188B2 (en) 2007-02-28 2009-08-27 Semiconductor device and method of manufacturing the semiconductor device
US13/780,177 US8664011B2 (en) 2007-02-28 2013-02-28 Semiconductor device and method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
WO2008105100A1 true WO2008105100A1 (ja) 2008-09-04

Family

ID=39720944

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法
PCT/JP2008/051090 WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/051090 WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法

Country Status (4)

Country Link
US (2) US8405188B2 (ja)
KR (1) KR101084408B1 (ja)
CN (1) CN101641782B (ja)
WO (2) WO2008105100A1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101830193B1 (ko) * 2010-07-02 2018-02-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US8780628B2 (en) * 2011-09-23 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
JP5845866B2 (ja) * 2011-12-07 2016-01-20 富士通セミコンダクター株式会社 半導体装置の製造方法
WO2014094882A1 (en) * 2012-12-21 2014-06-26 European Space Agency Additive manufacturing method using focused light heating source
JP2015133392A (ja) * 2014-01-10 2015-07-23 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US9711454B2 (en) * 2015-08-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through via structure for step coverage improvement
US10319635B2 (en) * 2017-05-25 2019-06-11 Sandisk Technologies Llc Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2002110934A (ja) * 2000-09-29 2002-04-12 Fujitsu Ltd 半導体装置およびその製造方法
JP2002203948A (ja) * 2001-01-05 2002-07-19 Matsushita Electric Ind Co Ltd 半導体装置
JP2002324894A (ja) * 2001-04-25 2002-11-08 Fujitsu Ltd 半導体装置およびその製造方法
JP2006073648A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置及びその製造方法

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Publication number Priority date Publication date Assignee Title
JP3299909B2 (ja) 1997-02-25 2002-07-08 シャープ株式会社 酸化物導電体を用いた多層構造電極
JP3109485B2 (ja) 1998-08-03 2000-11-13 日本電気株式会社 金属酸化物誘電体膜の気相成長方法
JP3159255B2 (ja) 1998-09-16 2001-04-23 日本電気株式会社 強誘電体容量で用いる電極のスパッタ成長方法
JP3545279B2 (ja) 1999-10-26 2004-07-21 富士通株式会社 強誘電体キャパシタ、その製造方法、および半導体装置
US6887716B2 (en) 2000-12-20 2005-05-03 Fujitsu Limited Process for producing high quality PZT films for ferroelectric memory integrated circuits
JP4050004B2 (ja) 2001-03-28 2008-02-20 富士通株式会社 半導体装置及びその製造方法
JP4428500B2 (ja) * 2001-07-13 2010-03-10 富士通マイクロエレクトロニクス株式会社 容量素子及びその製造方法
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JP4657545B2 (ja) 2001-12-28 2011-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110934A (ja) * 2000-09-29 2002-04-12 Fujitsu Ltd 半導体装置およびその製造方法
JP2002203948A (ja) * 2001-01-05 2002-07-19 Matsushita Electric Ind Co Ltd 半導体装置
JP2002324894A (ja) * 2001-04-25 2002-11-08 Fujitsu Ltd 半導体装置およびその製造方法
JP2006073648A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR101084408B1 (ko) 2011-11-18
CN101641782A (zh) 2010-02-03
CN101641782B (zh) 2012-10-10
US8405188B2 (en) 2013-03-26
KR20090110908A (ko) 2009-10-23
US20130177997A1 (en) 2013-07-11
WO2008105204A1 (ja) 2008-09-04
US8664011B2 (en) 2014-03-04
US20090315144A1 (en) 2009-12-24

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