WO2008105100A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2008105100A1 WO2008105100A1 PCT/JP2007/053836 JP2007053836W WO2008105100A1 WO 2008105100 A1 WO2008105100 A1 WO 2008105100A1 JP 2007053836 W JP2007053836 W JP 2007053836W WO 2008105100 A1 WO2008105100 A1 WO 2008105100A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- composition
- chemical formula
- oxide
- composition parameter
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000203 mixture Substances 0.000 abstract 7
- 239000000126 substance Substances 0.000 abstract 4
- 229910052751 metal Inorganic materials 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 2
- 229910000510 noble metal Inorganic materials 0.000 abstract 2
- 239000000956 alloy Substances 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 230000001747 exhibiting effect Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000004575 stone Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
キャパシタ上部電極Q2は、組成パラメータx1を使って化学式AOx1(A:金属元素)で表され実際の組成が組成パラメータx2を使って化学式AOx2で表される第1酸化物よりなる第1の層57と、第1の層57上に形成され、組成パラメータy1を使って化学式BOy1で表され実際の組成が組成パラメータy2を使って化学式BOy2(B:金属元素)で表される第2酸化物であって、石垣状或いは柱状に接合される結晶からなり、第1の層57より酸化の割合が高く構成され、組成パラメータx1、x2、y1およびy2の間には、関係y2/y1>x1/x1が成立する第2の層58と、第2の層58上形成され、貴金属膜或いは貴金属を含む合金よりなる第3の層59とを有する。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/053836 WO2008105100A1 (ja) | 2007-02-28 | 2007-02-28 | 半導体装置及びその製造方法 |
PCT/JP2008/051090 WO2008105204A1 (ja) | 2007-02-28 | 2008-01-25 | 半導体装置及びその製造方法 |
JP2009501154A JP5104850B2 (ja) | 2007-02-28 | 2008-01-25 | 半導体装置の製造方法 |
CN2008800065920A CN101641782B (zh) | 2007-02-28 | 2008-01-25 | 半导体器件及其制造方法 |
KR1020097016930A KR101084408B1 (ko) | 2007-02-28 | 2008-01-25 | 반도체 장치 및 그 제조방법 |
US12/548,911 US8405188B2 (en) | 2007-02-28 | 2009-08-27 | Semiconductor device and method of manufacturing the semiconductor device |
US13/780,177 US8664011B2 (en) | 2007-02-28 | 2013-02-28 | Semiconductor device and method of manufacturing the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/053836 WO2008105100A1 (ja) | 2007-02-28 | 2007-02-28 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008105100A1 true WO2008105100A1 (ja) | 2008-09-04 |
Family
ID=39720944
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/053836 WO2008105100A1 (ja) | 2007-02-28 | 2007-02-28 | 半導体装置及びその製造方法 |
PCT/JP2008/051090 WO2008105204A1 (ja) | 2007-02-28 | 2008-01-25 | 半導体装置及びその製造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/051090 WO2008105204A1 (ja) | 2007-02-28 | 2008-01-25 | 半導体装置及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US8405188B2 (ja) |
KR (1) | KR101084408B1 (ja) |
CN (1) | CN101641782B (ja) |
WO (2) | WO2008105100A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101830193B1 (ko) * | 2010-07-02 | 2018-02-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
US8780628B2 (en) * | 2011-09-23 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including a voltage divider and methods of operating the same |
JP5845866B2 (ja) * | 2011-12-07 | 2016-01-20 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
WO2014094882A1 (en) * | 2012-12-21 | 2014-06-26 | European Space Agency | Additive manufacturing method using focused light heating source |
JP2015133392A (ja) * | 2014-01-10 | 2015-07-23 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US9711454B2 (en) * | 2015-08-29 | 2017-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through via structure for step coverage improvement |
US10319635B2 (en) * | 2017-05-25 | 2019-06-11 | Sandisk Technologies Llc | Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002110934A (ja) * | 2000-09-29 | 2002-04-12 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2002203948A (ja) * | 2001-01-05 | 2002-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2002324894A (ja) * | 2001-04-25 | 2002-11-08 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2006073648A (ja) * | 2004-08-31 | 2006-03-16 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3299909B2 (ja) | 1997-02-25 | 2002-07-08 | シャープ株式会社 | 酸化物導電体を用いた多層構造電極 |
JP3109485B2 (ja) | 1998-08-03 | 2000-11-13 | 日本電気株式会社 | 金属酸化物誘電体膜の気相成長方法 |
JP3159255B2 (ja) | 1998-09-16 | 2001-04-23 | 日本電気株式会社 | 強誘電体容量で用いる電極のスパッタ成長方法 |
JP3545279B2 (ja) | 1999-10-26 | 2004-07-21 | 富士通株式会社 | 強誘電体キャパシタ、その製造方法、および半導体装置 |
US6887716B2 (en) | 2000-12-20 | 2005-05-03 | Fujitsu Limited | Process for producing high quality PZT films for ferroelectric memory integrated circuits |
JP4050004B2 (ja) | 2001-03-28 | 2008-02-20 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP4428500B2 (ja) * | 2001-07-13 | 2010-03-10 | 富士通マイクロエレクトロニクス株式会社 | 容量素子及びその製造方法 |
JP2003204043A (ja) | 2001-10-24 | 2003-07-18 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP4657545B2 (ja) | 2001-12-28 | 2011-03-23 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP4316188B2 (ja) | 2002-05-29 | 2009-08-19 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP4153333B2 (ja) | 2003-03-10 | 2008-09-24 | 株式会社アルバック | 酸化物薄膜の製造方法 |
JP2004296929A (ja) * | 2003-03-27 | 2004-10-21 | Seiko Epson Corp | 強誘電体キャパシタの製造方法、強誘電体キャパシタ、記憶素子、電子素子、メモリ装置及び電子機器 |
JP2005183842A (ja) | 2003-12-22 | 2005-07-07 | Fujitsu Ltd | 半導体装置の製造方法 |
US20050161717A1 (en) * | 2004-01-28 | 2005-07-28 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
JP2006128274A (ja) | 2004-10-27 | 2006-05-18 | Seiko Epson Corp | 強誘電体キャパシタおよび強誘電体メモリの製造方法 |
JP2006222227A (ja) * | 2005-02-09 | 2006-08-24 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR100663356B1 (ko) * | 2005-02-14 | 2007-01-02 | 삼성전자주식회사 | 부분적 화학기계적 연마공정을 갖는 강유전체 메모리 소자제조방법들 |
JP2006245457A (ja) | 2005-03-07 | 2006-09-14 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
CN101203957B (zh) | 2005-06-17 | 2011-03-30 | 富士通半导体股份有限公司 | 半导体装置的制造方法 |
-
2007
- 2007-02-28 WO PCT/JP2007/053836 patent/WO2008105100A1/ja active Application Filing
-
2008
- 2008-01-25 WO PCT/JP2008/051090 patent/WO2008105204A1/ja active Application Filing
- 2008-01-25 KR KR1020097016930A patent/KR101084408B1/ko active IP Right Grant
- 2008-01-25 CN CN2008800065920A patent/CN101641782B/zh active Active
-
2009
- 2009-08-27 US US12/548,911 patent/US8405188B2/en active Active
-
2013
- 2013-02-28 US US13/780,177 patent/US8664011B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002110934A (ja) * | 2000-09-29 | 2002-04-12 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2002203948A (ja) * | 2001-01-05 | 2002-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2002324894A (ja) * | 2001-04-25 | 2002-11-08 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2006073648A (ja) * | 2004-08-31 | 2006-03-16 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR101084408B1 (ko) | 2011-11-18 |
CN101641782A (zh) | 2010-02-03 |
CN101641782B (zh) | 2012-10-10 |
US8405188B2 (en) | 2013-03-26 |
KR20090110908A (ko) | 2009-10-23 |
US20130177997A1 (en) | 2013-07-11 |
WO2008105204A1 (ja) | 2008-09-04 |
US8664011B2 (en) | 2014-03-04 |
US20090315144A1 (en) | 2009-12-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2008105100A1 (ja) | 半導体装置及びその製造方法 | |
TW200746388A (en) | Complex oxide laminate, method of manufacturing complex oxide laminate, and device | |
WO2005092796A3 (en) | Titanium-containing perovskite compound and production method thereof | |
WO2008111188A1 (ja) | 半導体装置及びその製造方法 | |
WO2016122150A3 (ko) | 유기전기 소자용 화합물, 이를 이용한 유기전기소자 및 그 전자 장치 | |
WO2012112927A3 (en) | Methods of forming semiconductor films including i2-ii-iv-vi4 and i2-(ii,iv)-iv-vi4 semiconductor films and electronic devices including the semiconductor films | |
WO2011028377A3 (en) | High concentration water pulses for atomic layer deposition | |
EP1555700A3 (en) | Method for manufacturing a nonvolatile memory device with a variable resistor | |
JP2004161602A5 (ja) | Hf含有組成物の誘電率(k値)増進 | |
JP2010219509A5 (ja) | ||
WO2008114423A1 (ja) | 半導体装置およびその製造方法 | |
WO2011090570A3 (en) | Semiconductor package with embedded die and its methods of fabrication | |
WO2010048408A3 (en) | Carbon-based memory elements exhibiting reduced delamination and methods of forming the same | |
WO2004017377A3 (en) | Atomic layer deposition of high k metal oxides | |
JP2009124167A5 (ja) | ||
TW200707538A (en) | Semiconductor device and method of manufacturing the same | |
WO2008108128A1 (ja) | 誘電体、誘電体を用いたキャパシタ、誘電体を用いた半導体装置、及び誘電体の製造方法 | |
WO2010120954A3 (en) | Doped zro2 capacitor materials and structures | |
WO2009017109A1 (ja) | 高誘電性フィルム | |
WO2009072201A1 (ja) | 抵抗変化素子とその製造方法、及び抵抗変化素子を用いた半導体記憶装置 | |
EP2629343A3 (en) | Thermoelectric conversion module and method for manufacturing thermoelectric conversion module | |
RU2009117697A (ru) | Распыляемая мишень на основе оксида титана для прозрачной проводящей пленки, способ получения такой пленки и состав для использования в этом способе | |
WO2019103461A3 (ko) | 양극활물질 전구체, 그 제조 방법, 이를 이용해 제조된 양극 활물질, 양극 및 이차전지 | |
WO2006094280A3 (en) | Metal-insulator-metal capacitor manufactured using etchback | |
EP1630855A3 (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07737555 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 07737555 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: JP |