WO2008105100A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2008105100A1
WO2008105100A1 PCT/JP2007/053836 JP2007053836W WO2008105100A1 WO 2008105100 A1 WO2008105100 A1 WO 2008105100A1 JP 2007053836 W JP2007053836 W JP 2007053836W WO 2008105100 A1 WO2008105100 A1 WO 2008105100A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
composition
chemical formula
oxide
composition parameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/053836
Other languages
English (en)
French (fr)
Inventor
Wensheng Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/053836 priority Critical patent/WO2008105100A1/ja
Priority to CN2008800065920A priority patent/CN101641782B/zh
Priority to KR1020097016930A priority patent/KR101084408B1/ko
Priority to PCT/JP2008/051090 priority patent/WO2008105204A1/ja
Priority to JP2009501154A priority patent/JP5104850B2/ja
Publication of WO2008105100A1 publication Critical patent/WO2008105100A1/ja
Priority to US12/548,911 priority patent/US8405188B2/en
Anticipated expiration legal-status Critical
Priority to US13/780,177 priority patent/US8664011B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/694—Electrodes comprising noble metals or noble metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Landscapes

  • Semiconductor Memories (AREA)

Abstract

キャパシタ上部電極Ｑ２は、組成パラメータｘ１を使って化学式ＡＯｘ1（Ａ：金属元素）で表され実際の組成が組成パラメータｘ２を使って化学式ＡＯｘ2で表される第１酸化物よりなる第１の層５７と、第１の層５７上に形成され、組成パラメータｙ１を使って化学式ＢＯｙ1で表され実際の組成が組成パラメータｙ２を使って化学式ＢＯｙ２（Ｂ：金属元素）で表される第２酸化物であって、石垣状或いは柱状に接合される結晶からなり、第１の層５７より酸化の割合が高く構成され、組成パラメータｘ１、ｘ２、ｙ１およびｙ２の間には、関係ｙ２／ｙ１＞ｘ１／ｘ１が成立する第２の層５８と、第２の層５８上形成され、貴金属膜或いは貴金属を含む合金よりなる第３の層５９とを有する。
PCT/JP2007/053836 2007-02-28 2007-02-28 半導体装置及びその製造方法 Ceased WO2008105100A1 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法
CN2008800065920A CN101641782B (zh) 2007-02-28 2008-01-25 半导体器件及其制造方法
KR1020097016930A KR101084408B1 (ko) 2007-02-28 2008-01-25 반도체 장치 및 그 제조방법
PCT/JP2008/051090 WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法
JP2009501154A JP5104850B2 (ja) 2007-02-28 2008-01-25 半導体装置の製造方法
US12/548,911 US8405188B2 (en) 2007-02-28 2009-08-27 Semiconductor device and method of manufacturing the semiconductor device
US13/780,177 US8664011B2 (en) 2007-02-28 2013-02-28 Semiconductor device and method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
WO2008105100A1 true WO2008105100A1 (ja) 2008-09-04

Family

ID=39720944

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2007/053836 Ceased WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法
PCT/JP2008/051090 Ceased WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/051090 Ceased WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法

Country Status (4)

Country Link
US (2) US8405188B2 (ja)
KR (1) KR101084408B1 (ja)
CN (1) CN101641782B (ja)
WO (2) WO2008105100A1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101830193B1 (ko) * 2010-07-02 2018-02-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US8780628B2 (en) * 2011-09-23 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
JP5845866B2 (ja) 2011-12-07 2016-01-20 富士通セミコンダクター株式会社 半導体装置の製造方法
WO2014094882A1 (en) * 2012-12-21 2014-06-26 European Space Agency Additive manufacturing method using focused light heating source
JP2015133392A (ja) * 2014-01-10 2015-07-23 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US9711454B2 (en) 2015-08-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through via structure for step coverage improvement
US10319635B2 (en) * 2017-05-25 2019-06-11 Sandisk Technologies Llc Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110934A (ja) * 2000-09-29 2002-04-12 Fujitsu Ltd 半導体装置およびその製造方法
JP2002203948A (ja) * 2001-01-05 2002-07-19 Matsushita Electric Ind Co Ltd 半導体装置
JP2002324894A (ja) * 2001-04-25 2002-11-08 Fujitsu Ltd 半導体装置およびその製造方法
JP2006073648A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3299909B2 (ja) 1997-02-25 2002-07-08 シャープ株式会社 酸化物導電体を用いた多層構造電極
JP3109485B2 (ja) 1998-08-03 2000-11-13 日本電気株式会社 金属酸化物誘電体膜の気相成長方法
JP3159255B2 (ja) 1998-09-16 2001-04-23 日本電気株式会社 強誘電体容量で用いる電極のスパッタ成長方法
JP3545279B2 (ja) 1999-10-26 2004-07-21 富士通株式会社 強誘電体キャパシタ、その製造方法、および半導体装置
US6887716B2 (en) * 2000-12-20 2005-05-03 Fujitsu Limited Process for producing high quality PZT films for ferroelectric memory integrated circuits
JP4050004B2 (ja) 2001-03-28 2008-02-20 富士通株式会社 半導体装置及びその製造方法
JP4428500B2 (ja) * 2001-07-13 2010-03-10 富士通マイクロエレクトロニクス株式会社 容量素子及びその製造方法
JP2003204043A (ja) 2001-10-24 2003-07-18 Fujitsu Ltd 半導体装置及びその製造方法
JP4657545B2 (ja) 2001-12-28 2011-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4316188B2 (ja) 2002-05-29 2009-08-19 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP4153333B2 (ja) 2003-03-10 2008-09-24 株式会社アルバック 酸化物薄膜の製造方法
JP2004296929A (ja) * 2003-03-27 2004-10-21 Seiko Epson Corp 強誘電体キャパシタの製造方法、強誘電体キャパシタ、記憶素子、電子素子、メモリ装置及び電子機器
JP2005183842A (ja) 2003-12-22 2005-07-07 Fujitsu Ltd 半導体装置の製造方法
US20050161717A1 (en) * 2004-01-28 2005-07-28 Fujitsu Limited Semiconductor device and method of fabricating the same
JP2006128274A (ja) 2004-10-27 2006-05-18 Seiko Epson Corp 強誘電体キャパシタおよび強誘電体メモリの製造方法
JP2006222227A (ja) 2005-02-09 2006-08-24 Fujitsu Ltd 半導体装置及びその製造方法
KR100663356B1 (ko) * 2005-02-14 2007-01-02 삼성전자주식회사 부분적 화학기계적 연마공정을 갖는 강유전체 메모리 소자제조방법들
JP2006245457A (ja) 2005-03-07 2006-09-14 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP5076890B2 (ja) 2005-06-17 2012-11-21 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110934A (ja) * 2000-09-29 2002-04-12 Fujitsu Ltd 半導体装置およびその製造方法
JP2002203948A (ja) * 2001-01-05 2002-07-19 Matsushita Electric Ind Co Ltd 半導体装置
JP2002324894A (ja) * 2001-04-25 2002-11-08 Fujitsu Ltd 半導体装置およびその製造方法
JP2006073648A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR101084408B1 (ko) 2011-11-18
CN101641782A (zh) 2010-02-03
WO2008105204A1 (ja) 2008-09-04
US8405188B2 (en) 2013-03-26
US20130177997A1 (en) 2013-07-11
KR20090110908A (ko) 2009-10-23
US20090315144A1 (en) 2009-12-24
CN101641782B (zh) 2012-10-10
US8664011B2 (en) 2014-03-04

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