WO2008081805A1 - 配線膜の形成方法、トランジスタ、及び電子装置 - Google Patents

配線膜の形成方法、トランジスタ、及び電子装置 Download PDF

Info

Publication number
WO2008081805A1
WO2008081805A1 PCT/JP2007/074930 JP2007074930W WO2008081805A1 WO 2008081805 A1 WO2008081805 A1 WO 2008081805A1 JP 2007074930 W JP2007074930 W JP 2007074930W WO 2008081805 A1 WO2008081805 A1 WO 2008081805A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
resistance
low
wiring film
transistor
Prior art date
Application number
PCT/JP2007/074930
Other languages
English (en)
French (fr)
Inventor
Satoru Takasawa
Masaki Takei
Hirohisa Takahashi
Hiroaki Katagiri
Sadayuki Ukishima
Noriaki Tani
Satoru Ishibashi
Tadashi Masuda
Original Assignee
Ulvac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac, Inc. filed Critical Ulvac, Inc.
Priority to KR1020097007110A priority Critical patent/KR101132582B1/ko
Priority to CN2007800404997A priority patent/CN101529567B/zh
Priority to EP07860159.8A priority patent/EP2101346A4/en
Priority to JP2008552118A priority patent/JPWO2008081805A1/ja
Publication of WO2008081805A1 publication Critical patent/WO2008081805A1/ja
Priority to US12/480,150 priority patent/US20090236603A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Abstract

　密着性に優れ、低抵抗な配線膜を形成する。成膜対象物２１が配置された真空槽２に酸素ガスを導入して純銅ターゲット１１をスパッタリングし、成膜対象物２１の表面に銅を主成分とし、酸素を含有するバリア膜２２を成膜した後、酸素ガスの導入を停止して純銅ターゲット１１をスパッタリングし、純銅の低抵抗膜２３を成膜する。バリア膜２２と低抵抗膜２３は銅を主成分とするため、一度にパターニング可能である。低抵抗膜２３はバリア膜２２より低抵抗であるから、配線膜２５全体も低抵抗になる。バリア膜２２はガラスやシリコンに対する密着性が高いから、配線膜２５全体の密着性も高い。
PCT/JP2007/074930 2006-12-28 2007-12-26 配線膜の形成方法、トランジスタ、及び電子装置 WO2008081805A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020097007110A KR101132582B1 (ko) 2006-12-28 2007-12-26 배선막의 형성 방법
CN2007800404997A CN101529567B (zh) 2006-12-28 2007-12-26 布线膜的形成方法、晶体管以及电子装置
EP07860159.8A EP2101346A4 (en) 2006-12-28 2007-12-26 METHOD FOR FORMING WIRING FILM, TRANSISTOR, AND ELECTRONIC DEVICE
JP2008552118A JPWO2008081805A1 (ja) 2006-12-28 2007-12-26 配線膜の形成方法、トランジスタ、及び電子装置
US12/480,150 US20090236603A1 (en) 2006-12-28 2009-06-08 Process for forming a wiring film, a transistor, and an electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006354858 2006-12-28
JP2006-354858 2006-12-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/480,150 Continuation US20090236603A1 (en) 2006-12-28 2009-06-08 Process for forming a wiring film, a transistor, and an electronic device

Publications (1)

Publication Number Publication Date
WO2008081805A1 true WO2008081805A1 (ja) 2008-07-10

Family

ID=39588488

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/074930 WO2008081805A1 (ja) 2006-12-28 2007-12-26 配線膜の形成方法、トランジスタ、及び電子装置

Country Status (7)

Country Link
US (1) US20090236603A1 (ja)
EP (1) EP2101346A4 (ja)
JP (1) JPWO2008081805A1 (ja)
KR (1) KR101132582B1 (ja)
CN (2) CN102097472A (ja)
TW (1) TWI395270B (ja)
WO (1) WO2008081805A1 (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009038284A (ja) * 2007-08-03 2009-02-19 Mitsubishi Materials Corp 薄膜トランジスター
JP2009170769A (ja) * 2008-01-18 2009-07-30 Mitsubishi Materials Corp 薄膜トランジスター
JP2010265524A (ja) * 2009-05-15 2010-11-25 Kanto Chem Co Inc 銅含有積層膜用エッチング液
JP2013507782A (ja) * 2009-10-15 2013-03-04 アプライド マテリアルズ インコーポレイテッド 半導体デバイスを製造する方法および設備と半導体デバイス
US8470651B2 (en) 2008-10-24 2013-06-25 Mitsubishi Materials Corporation Method for producing a thin film transistor, and a thin film transistor
US8624397B2 (en) 2009-06-12 2014-01-07 Mitsubishi Materials Corporation Electrode layer structure for a thin-film transistor and process for manufacture thereof
JP2017135415A (ja) * 2009-11-13 2017-08-03 株式会社半導体エネルギー研究所 半導体装置の作製方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5411481B2 (ja) * 2008-10-22 2014-02-12 国立大学法人東北大学 マグネトロンスパッタ装置
KR101583602B1 (ko) * 2009-07-23 2016-01-11 엘지디스플레이 주식회사 구리배선 형성방법과 구리배선을 포함하는 액정표시장치용 어레이기판
CN102521445B (zh) * 2011-12-09 2014-01-01 清华大学 磁控溅射设备中铜靶刻蚀形貌的仿真计算方法
JP5787779B2 (ja) * 2012-01-25 2015-09-30 日東電工株式会社 導電性フィルムロールの製造方法
JP6108210B2 (ja) * 2012-01-31 2017-04-05 日立金属株式会社 電子部品用積層配線膜
JP2022156320A (ja) * 2021-03-31 2022-10-14 Tdk株式会社 積層電子部品

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06333925A (ja) * 1993-05-20 1994-12-02 Nippon Steel Corp 半導体集積回路及びその製造方法
JPH1012151A (ja) 1996-04-25 1998-01-16 Lg Electron Inc プラズマディスプレイパネルの電極及びその形成方法
JP2002091338A (ja) * 2000-09-12 2002-03-27 Toshiba Corp アレイ基板およびその製造方法ならびに液晶表示素子
JP2005158887A (ja) 2003-11-21 2005-06-16 Dept Corp 回路基板及びその製造方法
JP2006148040A (ja) * 2004-11-17 2006-06-08 Samsung Electronics Co Ltd 薄膜トランジスタ表示板及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037257A (en) * 1997-05-08 2000-03-14 Applied Materials, Inc. Sputter deposition and annealing of copper alloy metallization
KR100399556B1 (ko) * 1998-12-14 2003-10-17 엘지.필립스 엘시디 주식회사 배선, 이를 사용한 박막 트랜지스터 기판, 및 그제조방법과 액정표시장치
US7023059B1 (en) * 2004-03-01 2006-04-04 Advanced Micro Devices, Inc. Trenches to reduce lateral silicide growth in integrated circuit technology
KR101167661B1 (ko) * 2005-07-15 2012-07-23 삼성전자주식회사 배선 구조와 배선 형성 방법 및 박막 트랜지스터 기판과 그제조 방법
KR101168728B1 (ko) * 2005-07-15 2012-07-26 삼성전자주식회사 배선 구조와 배선 형성 방법 및 박막 트랜지스터 기판과 그제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06333925A (ja) * 1993-05-20 1994-12-02 Nippon Steel Corp 半導体集積回路及びその製造方法
JPH1012151A (ja) 1996-04-25 1998-01-16 Lg Electron Inc プラズマディスプレイパネルの電極及びその形成方法
JP2002091338A (ja) * 2000-09-12 2002-03-27 Toshiba Corp アレイ基板およびその製造方法ならびに液晶表示素子
JP2005158887A (ja) 2003-11-21 2005-06-16 Dept Corp 回路基板及びその製造方法
JP2006148040A (ja) * 2004-11-17 2006-06-08 Samsung Electronics Co Ltd 薄膜トランジスタ表示板及びその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2101346A4

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009038284A (ja) * 2007-08-03 2009-02-19 Mitsubishi Materials Corp 薄膜トランジスター
JP2009170769A (ja) * 2008-01-18 2009-07-30 Mitsubishi Materials Corp 薄膜トランジスター
US8470651B2 (en) 2008-10-24 2013-06-25 Mitsubishi Materials Corporation Method for producing a thin film transistor, and a thin film transistor
JP2010265524A (ja) * 2009-05-15 2010-11-25 Kanto Chem Co Inc 銅含有積層膜用エッチング液
US8624397B2 (en) 2009-06-12 2014-01-07 Mitsubishi Materials Corporation Electrode layer structure for a thin-film transistor and process for manufacture thereof
JP2013507782A (ja) * 2009-10-15 2013-03-04 アプライド マテリアルズ インコーポレイテッド 半導体デバイスを製造する方法および設備と半導体デバイス
JP2017135415A (ja) * 2009-11-13 2017-08-03 株式会社半導体エネルギー研究所 半導体装置の作製方法
US10056494B2 (en) 2009-11-13 2018-08-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10516055B2 (en) 2009-11-13 2019-12-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10944010B2 (en) 2009-11-13 2021-03-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11456385B2 (en) 2009-11-13 2022-09-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US11955557B2 (en) 2009-11-13 2024-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US20090236603A1 (en) 2009-09-24
CN101529567B (zh) 2012-07-04
KR101132582B1 (ko) 2012-04-06
JPWO2008081805A1 (ja) 2010-04-30
KR20090053853A (ko) 2009-05-27
CN101529567A (zh) 2009-09-09
CN102097472A (zh) 2011-06-15
TW200842981A (en) 2008-11-01
EP2101346A1 (en) 2009-09-16
EP2101346A4 (en) 2015-11-18
TWI395270B (zh) 2013-05-01

Similar Documents

Publication Publication Date Title
WO2008081805A1 (ja) 配線膜の形成方法、トランジスタ、及び電子装置
WO2008081806A1 (ja) 配線膜の形成方法、トランジスタ、及び電子装置
WO2011013683A1 (ja) 配線構造および配線構造を備えた表示装置
TW200741972A (en) Semiconductor device and method for making the same
TWI445095B (zh) 薄膜電晶體的製造方法，薄膜電晶體
KR101175970B1 (ko) 배선층, 반도체 장치, 액정 표시 장치
KR101175085B1 (ko) 반도체 장치, 반도체 장치를 갖는 액정 표시 장치, 반도체 장치의 제조 방법
WO2008016650A3 (en) Methods of forming carbon-containing silicon epitaxial layers
WO2008024205A3 (en) Front contact with high work-function tco for use in photovoltaic device and method of making same
TW200744241A (en) Method of making an encapsulated plasma sensitive device
TWI652359B (zh) 積層配線膜及薄膜電晶體元件
WO2008069930A3 (en) Flexible substrates having a thin-film barrier
US9947796B2 (en) Oxide thin film transistor and manufacturing method thereof, array substrate and display device
SG132584A1 (en) Formation of metal silicide layer over copper interconnect for reliability enhancement
TW200705017A (en) Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thin film transistor substrate
TW200614424A (en) Method for fabricating copper-based interconnections for semiconductor device
KR20100110392A (ko) 박막 트랜지스터의 제조 방법, 박막 트랜지스터
CN104752345B (zh) 薄膜晶体管阵列基板及其制作方法
TW201034200A (en) Thin-film transistor having barrier layer as constituent layer and copper alloy sputtering target for forming barrier layer by sputter deposition
TW200740289A (en) Organic electroluminescent element and its manufacturing method
CN102576675B (zh) 布线层、半导体装置、具有半导体装置的液晶显示装置
AU2002358303A1 (en) Material deposition from a liquefied gas solution
WO2009001896A1 (ja) 成膜方法および処理システム
Yu et al. The role of oxygen in the deposition of copper–calcium thin film as diffusion barrier for copper metallization
JP2012222166A (ja) 配線膜、薄膜トランジスタ、ターゲット、配線膜の形成方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780040499.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07860159

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2008552118

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: KR

Ref document number: 1020097007110

Country of ref document: KR

REEP Request for entry into the european phase

Ref document number: 2007860159

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007860159

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE