WO2008081567A1 - シリコンウエーハの評価方法 - Google Patents

シリコンウエーハの評価方法 Download PDF

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Publication number
WO2008081567A1
WO2008081567A1 PCT/JP2007/001397 JP2007001397W WO2008081567A1 WO 2008081567 A1 WO2008081567 A1 WO 2008081567A1 JP 2007001397 W JP2007001397 W JP 2007001397W WO 2008081567 A1 WO2008081567 A1 WO 2008081567A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon wafer
electrodes
insulating film
evaluation method
evaluated
Prior art date
Application number
PCT/JP2007/001397
Other languages
English (en)
French (fr)
Inventor
Hisayuki Saito
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to JP2008552018A priority Critical patent/JPWO2008081567A1/ja
Priority to US12/448,408 priority patent/US8111081B2/en
Priority to EP07859649A priority patent/EP2105956A4/en
Priority to CN2007800492235A priority patent/CN101606239B/zh
Publication of WO2008081567A1 publication Critical patent/WO2008081567A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49227—Insulator making

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

　本発明は、シリコンウエーハ上に絶縁膜と１つ以上の電極を順次形成してＭＯＳキャパシタを作製した後、前記形成した電極から絶縁膜に電界を印加して該絶縁膜の絶縁破壊特性を測定することによってシリコンウエーハを評価する方法であって、少なくとも、前記１つ以上の電極を形成するときに、該形成する電極全てによる占有面積を前記シリコンウエーハ表面の面積の５％以上として、該シリコンウエーハを評価するシリコンウエーハの評価方法である。これにより、シリコンウエーハをＴＤＤＢ法等の簡単な方法により、かつ、ＤＳＯＤ法と同程度で欠陥の検出を高い精度で行うことができる評価方法が提供される。
PCT/JP2007/001397 2007-01-05 2007-12-14 シリコンウエーハの評価方法 WO2008081567A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008552018A JPWO2008081567A1 (ja) 2007-01-05 2007-12-14 シリコンウエーハの評価方法
US12/448,408 US8111081B2 (en) 2007-01-05 2007-12-14 Method for evaluating silicon wafer
EP07859649A EP2105956A4 (en) 2007-01-05 2007-12-14 METHOD FOR EVALUATING SILICON WAFERS
CN2007800492235A CN101606239B (zh) 2007-01-05 2007-12-14 硅晶片的评价方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-000629 2007-01-05
JP2007000629 2007-01-05

Publications (1)

Publication Number Publication Date
WO2008081567A1 true WO2008081567A1 (ja) 2008-07-10

Family

ID=39588257

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/001397 WO2008081567A1 (ja) 2007-01-05 2007-12-14 シリコンウエーハの評価方法

Country Status (7)

Country Link
US (1) US8111081B2 (ja)
EP (1) EP2105956A4 (ja)
JP (1) JPWO2008081567A1 (ja)
KR (1) KR20090096711A (ja)
CN (1) CN101606239B (ja)
TW (1) TW200845257A (ja)
WO (1) WO2008081567A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056264A (ja) * 2008-08-28 2010-03-11 Sumco Corp シリコンウェーハの評価方法および製造方法
JP2016103528A (ja) * 2014-11-27 2016-06-02 信越半導体株式会社 シリコン単結晶ウェーハの評価方法

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KR101333374B1 (ko) * 2011-12-09 2013-12-02 명지대학교 산학협력단 실리콘 관통 전극 프로파일 평가 방법 및 장치
JP2014192493A (ja) 2013-03-28 2014-10-06 Toyoda Gosei Co Ltd 半導体装置
CN106933119B (zh) * 2015-12-30 2021-05-11 巴彦淖尔聚光硅业有限公司 多晶硅还原炉调功柜控制系统
JP6536517B2 (ja) * 2016-09-07 2019-07-03 信越半導体株式会社 結晶欠陥評価方法
US9953727B1 (en) * 2017-02-10 2018-04-24 Globalfoundries Inc. Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing
JP6711327B2 (ja) * 2017-07-18 2020-06-17 株式会社Sumco シリコンウェーハ製造工程の評価方法およびシリコンウェーハの製造方法
CN111029270A (zh) * 2019-12-19 2020-04-17 西安奕斯伟硅片技术有限公司 晶圆处理方法及装置

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JPH08330316A (ja) 1995-05-31 1996-12-13 Sumitomo Sitix Corp シリコン単結晶ウェーハおよびその製造方法
JPH0964345A (ja) * 1995-08-18 1997-03-07 Fujitsu Ltd 電界効果半導体装置のゲート絶縁膜耐圧モニタ
JP2006005088A (ja) * 2004-06-16 2006-01-05 Siltronic Japan Corp シリコン半導体基板とその製造方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010056264A (ja) * 2008-08-28 2010-03-11 Sumco Corp シリコンウェーハの評価方法および製造方法
JP2016103528A (ja) * 2014-11-27 2016-06-02 信越半導体株式会社 シリコン単結晶ウェーハの評価方法

Also Published As

Publication number Publication date
EP2105956A4 (en) 2012-03-07
CN101606239A (zh) 2009-12-16
CN101606239B (zh) 2011-05-04
KR20090096711A (ko) 2009-09-14
US8111081B2 (en) 2012-02-07
US20100019796A1 (en) 2010-01-28
JPWO2008081567A1 (ja) 2010-04-30
EP2105956A1 (en) 2009-09-30
TW200845257A (en) 2008-11-16

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