Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
  • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
  • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
  • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Definitions

• the present disclosure relates generally to circuits, and more specifically to a phase-locked loop.
• Phase-locked loops are commonly used in many electronics circuits and are particularly important in communication circuits.
• digital systems use clock signals to trigger synchronous circuits, e.g., flip-flops.
• Transmitter and receiver systems use local oscillator (LO) signals for frequency upconversion and downconversion, respectively.
• LO local oscillator
• Wireless devices e.g., cellular phones
• Clock and LO signals are often generated with voltage-controlled oscillators (VCOs) operating within PLLs.
• VCOs voltage-controlled oscillators
• a PLL typically includes a phase frequency detector, a charge pump, a loop filter, and a VCO.
• the phase frequency detector, charge pump, loop filter collectively detect phase error between a reference signal and a clock signal derived from the VCO and generate a control signal for the VCO.
• the control signal adjusts the frequency of the VCO such that the clock signal is locked to the reference signal.
• the phase frequency detector typically generates a pair of signals that is commonly referred to as up and down signals. One signal is typically turned on longer in each clock cycle depending on whether the clock signal is early or late relative to the reference signal.
• the up and down signals are used to couple current sources within the charge pump to the output.
• the phase frequency detector and charge pump should have a linear transfer function of output charge versus phase error.
• this linear transfer function is typically not achieved. Consequently, the output change from the up signal is often not equal to the output charge from the down signal for phase errors of the same magnitude but opposite polarity.
• This charge error is due to up/down current mismatch in the charge pump, which may result from transistor device mismatch and other factors. Non-linearity of the charge pump due to current mismatch may cause additional phase noise that may degrade performance.
• the phase frequency detector uses a new timing/clocking scheme to generate up and down signals such that up/down current mismatch in the charge pump does not contribute to non-linear distortion in the first order.
• the new timing scheme uses only the up signal or only the down signal to reset flip-flops within the phase frequency detector. With the new timing scheme, up/down current mismatch in the charge pump does not show up in the output of the charge pump. Hence, good performance may be achieved even in the presence of transistor device mismatch.
• a PLL includes a phase frequency detector and a charge pump.
• the phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal.
• the first and second signals may be up and down signals, respectively. Alternatively, the first and second signals may be down and up signals, respectively.
• the phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal.
• the charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.
• the phase frequency detector and charge pump may be implemented as described below.
• FIG. 1 shows a block diagram of a fractional-N PLL.
• FIG. 2 shows a phase frequency detector and a charge pump for the PLL.
• FIG. 3 shows a timing diagram for the phase frequency detector in FIG. 2.
• FIG. 4A shows a charge transfer function for the charge pump in FIG. 2.
• FIG. 4B shows a gain function for the charge pump in FIG. 2.
• FIG. 5A shows a linear phase frequency detector and charge pump.
• FIG. 5B shows another linear phase frequency detector and charge pump.
• FIG. 6 shows a timing diagram for the phase frequency detector in FIG. 5A.
• FIG. 7 shows a process for operating a PLL.
• FIG. 8 shows a block diagram of a wireless communication device.
• integer-N PLLs divides the frequency of an oscillator signal from a VCO by an integer divider ratio N, where N > 1.
• a fractional-N PLL divides the frequency of the oscillator signal by a non-integer divider ratio R, e.g., by N some of the time and by N+l some other time, where N ⁇ R ⁇ N+l.
• a sigma- delta frequency synthesizer utilizes a sigma-delta modulator to generate the non-integer divider ratio R for the fractional-N PLL.
• FIG. 1 shows a block diagram of a design of a sigma-delta frequency synthesizer 100 with a fractional-N PLL 110 and a sigma-delta modulator 170.
• PLL 110 includes a phase-frequency detector 120, a charge pump 130, a loop filter 140, a voltage-controlled oscillator (VCO) 150, and a divider 160.
• VCO voltage-controlled oscillator
• Phase-frequency detector 120 receives a reference signal from a reference oscillator (not shown in FIG. 1) and a clock signal from divider 160, compares the phases of the two signals, and provides up and down signals indicative of the phase error/difference between the reference signal and the clock signal.
• the clock signal may also be referred to as divided clock signal, feedback signal, etc.
• the up and down signals are also commonly referred to as early and late signals, advance and retard signals, etc.
• Charge pump 130 receives the up and down signals and generates an output signal, which is a current Icp that is indicative of the detected phase error.
• Loop filter 140 filters the output signal from charge pump 130 and generates a control signal V CTRL for VCO 150.
• Loop filter 140 adjusts the control signal such that the phase or frequency of the clock signal is locked to the phase or frequency of the reference signal.
• Loop filter 140 has a frequency response that is typically selected to achieve the desired closed-loop response for PLL 110.
• the frequency response of loop filter 140 may be selected based on a tradeoff between acquisition and tracking performance and PLL noise performance.
• VCO 150 generates an oscillator signal having a frequency that is determined by the control signal from loop filter 140.
• Divider 160 divides the oscillator signal in frequency by integer factors of N and N+l and provides the clock signal. In general, N may be any positive integer value.
• Sigma-delta modulator 170 receives a divider ratio R, which may be expressed as:
• f vco is the desired frequency for VCO 150
• f ref is the frequency of the reference signal
• Sigma-delta modulator 170 generates a divider control for divider 160 to achieve the divider ratio R.
• This divider control may be a 1-bit control that instructs divider 160 to divide by either N or N+l.
• a logic low (O') on the divider control may correspond to divide by N
• a logic high (' 1 ') on the divider control may correspond to divide by N+l .
• the percentage of zeros and ones on the divider control is determined by the divider ratio R. However, the zeros are distributed on the divider control in a manner such that quantization noise is shifted to higher frequencies and good phase noise characteristic can be achieved for the oscillator signal from VCO 150.
• FIG. 1 shows an example design of a PLL and a frequency synthesizer.
• a PLL and a frequency synthesizer may be implemented with fewer, additional, and/or different circuit blocks than those shown in FIG. 1.
• VCO 150 may be replaced with a current digital-to-analog converter (iDAC) and a current-controlled oscillator (ICO).
• Divider 160 may be a fixed integer-N divider.
• Loop filter 140 may be an adaptive loop filter having a variable loop response, which may be used to change the PLL loop bandwidth and/or damping.
• One or more additional dividers may also be used to divide the oscillator signal to generate one or more additional clock signals at other frequencies of interest.
• FIG. 2 shows a design of a phase frequency detector 120a and a charge pump 130a, which may be used for phase frequency detector 120 and charge pump 130, respectively, in FIG. 1.
• the reference signal and the clock signal are provided to the clock inputs of D flip-flops 220a and 220b, respectively.
• the data (D) inputs of flip-flops 220a and 220b are coupled to a power supply and receive logic high.
• the data (Q) outputs of flip-flops 220a and 220b provide the up and down signals, respectively.
• the up signal is indicative of the reference signal being early with respect to the clock signal.
• the down signal is indicative of the reference signal being late with respect to the clock signal.
• An AND gate 222 receives the up and down signals and performs a logical AND on the two signals.
• a delay unit 224 delays the output of AND gate 222 by a predetermined amount of time T ON and provides a reset signal to the reset (R) inputs of flip-flops 220a and 220b.
• current sources 230a and 230b and switches 232a and 232b are coupled in series and between the power supply and circuit ground.
• Current source 230a provides a current of Iup
• current source 230b provides a current of I DOWN -
• Switch 232a receives the up signal and, when turned on by logic high on the up signal, couples current sources 230a to the output of charge pump 130a.
• Switch 232b receives the down signal and, when turned on by logic high on the down signal, couples current sources 230b to the output of charge pump 130a.
• the T ON delay by unit 224 is used to combat a dead zone in the charge pump.
• Current sources 230a and 230b need some amount of time to turn on and off. This transition time is referred to as the dead zone since, during the transition time, phase information in the up and down signals is lost.
• the T ON delay combats the dead zone.
• FIG. 3 shows a timing diagram that illustrates the operation of phase frequency detector 120a in FIG. 2.
• the up and down signals are at logic low.
• the reference signal transitions from logic low to logic high
• flip-flop 220a is triggered, and the up signal transitions to logic high.
• the clock signal transitions from logic low to logic high
• flip-flop 220b is triggered, and the down signal transitions to logic high.
• the up and down signals are both at logic high
• the output of AND gate 222 transitions to logic high.
• T 13 which is approximately T ON later than T12
• the reset signal transitions to logic high
• flip-flops 220a and 220b are both reset, and the up and down signals transition to logic low.
• the clock signal transitions from logic low to logic high, flip- flop 220b is triggered, and the down signal transitions to logic high.
• the reference signal transitions from logic low to logic high, flip-flop 220a is triggered, and the up signal transitions to logic high.
• the output of AND gate 222 transitions to logic high.
• the reset signal transitions to logic high, flip-flops 220a and 220b are both reset, and the up and down signals transition to logic low.
• two pulses are generated on the up and down signals in each clock cycle.
• FIG. 3 also illustrates the operation of charge pump 130a in FIG. 2.
• current source 230a When the up signal leads the down signal, current source 230a provides a sourcing current of I UP from time Tn to time T 13, and current source 230b provides a sinking current of I DOWN from time T12 to time T13. The net output current is the difference between the sourcing current and the sinking current from time Tn to time T 13 .
• current source 230b When the down signal leads the up signal, current source 230b provides a sinking current of I DOWN from time Ti 4 to time Ti 6 , and current source 230a provides a sourcing current of I UP from time Ti 5 to time Ti 6 .
• the net output current is the difference between the sourcing current and the sinking current from time Ti 4 to time Ti 6 .
• I UP is typically not equal to I DOWN due to transistor device mismatch and other factors.
• dt is the time difference between the rising edge of the reference signal and the rising edge of the clock signal
• Q(dt) is the output charge with the up signal leading the down signal
• the net output charge from charge pump 130a may be expressed as:
• the terms "I*dt” and “-I*dt” correspond to the desired components
• the term “ ⁇ I*dt” corresponds to a non-linear distortion component
• the term ⁇ I*T ON corresponds to direct current (DC) offset.
• the DC offset results in a static phase offset between the reference signal and the clock signal and generally does not impact performance.
• the non-linear component may however degrade phase noise and cause other deleterious effects.
• FIG. 4A shows a transfer function of output charge Q from charge pump 130a versus phase error d ⁇ .
• the transfer function should be a straight line with a slope determined by current I.
• the transfer function is composed of one straight line for negative phase error and another straight line for positive phase error.
• the straight line for positive phase error has higher slope if I UP > I DOWN > as shown in FIGS. 3 and 4 A.
• FIG. 4B shows a gain function for charge pump 130a versus phase error d ⁇ .
• the charge pump gain should be constant for all phase errors. However, due to current mismatch ⁇ I, the charge pump gain is one value for negative phase error and another value for positive phase error.
• the charge pump gain for positive phase error is higher if I up > I D0WN , as shown in FIGS. 3 and 4B.
• the current mismatch ⁇ I may result from mismatch in transistor devices used to implement current sources 230a and 230b, changes in the power supply voltage for the charge pump, and other factors.
• Device mismatch may be reduced by using large device sizes and following good design guidelines. However, large device sizes occupy more circuit area, which is undesirable. Furthermore, device mismatch is not completely eliminated even with large device sizes. Hence, the charge pump can be expected to have some current mismatch.
• a phase frequency detector uses a new timing/clocking scheme to generate up and down signals such that up/down current mismatch in a charge pump does not contribute to non-linear distortion in the first order.
• the new timing scheme uses only the up signal or only the down signal to reset the flip-flops within the phase frequency detector. This is different from the timing scheme shown in FIG. 2 where the up and down signals can both reset the flip-flops.
• the up/down current mismatch in the charge pump does not show up in the output of the charge pump. Hence, good performance may be achieved even in the presence of transistor device mismatch in the charge pump.
• FIG. 5A shows a design of a phase frequency detector 120b and a charge pump 130b, which may be used for phase frequency detector 120 and charge pump 130, respectively, in FIG. 1.
• Phase frequency detector 120b resets its flip-flops based solely on the up signal.
• phase frequency detector 120b the reference signal and the clock signal are provided to the clock inputs of D flip-flops 520a and 520b, respectively.
• the D inputs of flip-flops 520a and 520b are coupled to the power supply.
• the Q outputs of flip-flops 520a and 520b provide the up and down signals, respectively.
• a delay unit 522 delays the up signal by a predetermined amount of time T D .
• An AND gate 524 receives the delayed up signal and the down signal, performs a logical AND on the two signals, and provides a reset signal to the R inputs of flip-flops 520a and 520b.
• Charge pump 130b includes current sources 530a and 530b and switches 532a and 532b that are coupled in series and between the power supply and circuit ground.
• Switch 532a receives the up signal and couples current source 530a to the charge pump output.
• Switch 532b receives the down signal and couples current source 530b to the charge pump output.
• FIG. 5B shows a design of a phase frequency detector 120c, which may also be used for phase frequency detector 120 in FIG. 1.
• Phase frequency detector 120c resets its flip-flops based solely on the down signal.
• Phase frequency detector 120c includes flip-flops 520a and 520b, delay unit 522, and AND gate 524.
• delay unit 522 delays the down signal by the predetermined amount of time T D - AND gate 524 receives the delayed down signal and the up signal and provides the reset signal to flip-flops 520a and 520b.
• FIG. 6 shows a timing diagram that illustrates the operation of phase frequency detector 120b in FIG. 5 A. Initially, the up and down signals are at logic low. At time T 21 , the reference signal transitions to logic high, flip-flop 520a is triggered, and the up signal transitions to logic high. At time T 22 , the clock signal transitions to logic high, flip-flop 520b is triggered, and the down signal transitions to logic high.
• FIG. 6 also illustrates the operation of charge pump 130b in FIG. 5 A.
• the output charge from charge pump 130b may be expressed as:
• the output charge from charge pump 130b may be expressed as:
• the terms "I*dt” and “-I*dt” correspond to the desired components, and the term “ ⁇ I*T D " corresponds to DC offset.
• the up/down current mismatch in current sources 530a and 530b does not show up in the output of charge pump 130b.
• the non- linear component is canceled by introducing a fixed delay T D after the rising edge of the up signal.
• the cancellation of the non-linear component results in (a) the transfer function of output charge Q versus phase error d ⁇ resembling the ideal transfer function shown in FIG. 4A and (b) the charge pump gain resembling the ideal gain function shown in FIG. 4B.
• the fixed delay T D may be selected as follows:
• T ON is an on time used to account for the dead zone of the charge pump
• dtMAx is an expected maximum time difference between the rising edges of the reference and clock signals when the PLL is locked.
• phase frequency detector and the charge pump are typically only needed when the PLL is locked. Phase noise, spurious signal levels, and other specifications are normally applicable for a locked PLL.
• phase noise, spurious signal levels, and other specifications are normally applicable for a locked PLL.
• This range of time/phase differences may be dependent on various factors such as, e.g., the factors N and N+l used for divider 160, the divider control from delta-sigma modulator 170 (which may be dependent on the topology or design of the delta-sigma modulator), etc.
• the range of time/phase differences may be determined via computer simulation, empirical measurements, etc.
• a histogram of time/phase differences may be obtained for many clock cycles during frequency lock for a specific PLL and delta- sigma modulator design.
• dtMAx may then be selected based on the histogram, e.g., set equal to the time/phase difference that covers a target percentage (e.g., 99%) of the clock cycles.
• the time/phase difference dt may be larger than dt MA x-
• the rising edge of the down signal resets the flip-flops after T ON -
• the rising edge of the up signal resets the flip-flops after T D .
• the phase frequency detector and charge pump still function properly but are not linearized when the PLL is not locked, which is normally acceptable behavior.
• a PLL may include a phase frequency detector that receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal.
• the first and second signals may correspond to up and down signals, respectively, and may be generated based on the reference and clock signals, respectively, e.g., as shown in FIG. 5A.
• the first and second signals may correspond to down and up signals, respectively, and may be generated based on the clock and reference signals, respectively, e.g., as shown in FIG. 5B.
• the phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals based on the reset signal.
• the predetermined amount of delay may be selected, e.g., as shown in equation (6), or may be programmable.
• a charge pump receives the first and second signals and generates an output signal indicative of the phase error between the reference signal and the clock signal.
• the charge pump may provide a first current to the output signal based on the first signal and may provide a second current to the output signal based on the second signal, with the first current and second current having opposite polarity.
• the phase frequency detector and charge pump may be implemented as shown in FIG. 5A or 5B or some other design.
• FIG. 7 shows a process 700 for operating a PLL.
• First and second signals are generated based on a reference signal and a clock signal (block 712).
• the first and second signals are reset based on only the first signal (block 714).
• An output signal that is indicative of phase error between the reference signal and the clock signal is generated based on the first and second signals (block 716).
• the output signal may be filtered with a loop filter to generate a control signal for a VCO (block 718).
• An oscillator signal from the VCO may be divided by multiple integer factors (e.g., N and N+l) to generate the clock signal (block 720).
• a divider control may be generated (e.g., with noise shaping by a sigma-delta modulator) to select the multiple integer factors to achieve a non-integer divider ratio (block 722).
• the linear phase frequency detector and charge pump described herein may be used for various types of PLLs, as noted above, and are especially advantageous for signal-delta fractional-N PLLs.
• a signal-delta fractional-N PLL uses noise shaping by a signal-delta modulator to push quantization noise to higher frequencies, which may be more easily filtered by loop filter 140. Non-linearity in the charge pump may cause the higher frequency noise to fold back to lower frequencies and degrade performance. Linearizing the charge pump as described above reduces noise folding effects. Linearizing the charge pump may also reduce fractional spurs or extraneous tones generated from non-linear mixing and inter-modulation.
• the linear phase frequency detector and charge pump described herein may provide various advantages. Linear operation may be achieved even in the presence of mismatch in transistor devices and finite output impedance of the current sources in the charge pump. Consequently, current matching requirements for the current sources may be relaxed, voltage compliance requirements for the charge pump may be improved, and smaller transistor sizes may be used for the charge pump. Furthermore, close-in phase noise may improve, fractional spurious signal level may be lowered, and overall PLL performance may improve. Transistor device mismatch may now cause only reference spurs, which may be suppressed below noise level in a properly designed fractional-N PLL. [0063] The linear phase frequency detector and charge pump described herein may be used for various electronics circuits.
• FIG. 8 shows a block diagram of a design of a wireless device 800 in a wireless communication system.
• Wireless device 800 may be a cellular phone, a terminal, a personal digital assistant (PDA), a handset, or some other device.
• the wireless communication system may be a Code Division Multiple Access (CDMA) system, a Time Division Multiple Access (TDMA) system, a Frequency Division Multiple Access (FDMA) system, a Global System for Mobile Communications (GSM) system, an Orthogonal FDMA (OFDMA) system, a wireless local area network (WLAN), etc.
• CDMA Code Division Multiple Access
• TDMA Time Division Multiple Access
• FDMA Frequency Division Multiple Access
• GSM Global System for Mobile Communications
• OFDMA Orthogonal FDMA
• WLAN wireless local area network
• Wireless device 800 includes a digital processor 810 and a transceiver 830 that support bi-directional communication.
• Digital processor 810 may be implemented with one or more application specific integrated circuits (ASICs), etc.
• Transceiver 830 may be implemented with one or more RF integrated circuits (RFICs), etc.
• an encoder 812 processes (e.g., formats, encodes, and interleaves) data to be transmitted, and a modulator 814 further processes (e.g., modulates and scrambles) the coded data to generate data chips.
• a transmit (TX) baseband unit 832 performs baseband processing such as digital- to-analog conversion, filtering, amplification, etc.
• a mixer 834 upconverts the baseband signal to radio frequency (RF).
• a TX RF unit 836 performs signal conditioning such as filtering and power amplification and generates an RF modulated signal, which is transmitted via an antenna 840.
• a receive (RX) RF unit 842 receives an input RF signal from antenna 840 and performs signal conditioning such as low noise amplification and filtering.
• a mixer 844 downconverts the conditioned RF signal from RF to baseband.
• An RX baseband unit 846 performs baseband processing such as filtering, amplification, analog-to-digital conversion, etc.
• a demodulator (Demod) 816 processes (e.g., descrambles and demodulates) the input samples from unit 846 and provides symbol estimates.
• a decoder 818 processes (e.g., deinterleaves and decodes) the symbol estimates and provides decoded data.
• a processor 820 may support various applications such as video, audio, graphics, and so on.
• a controller/processor 860 directs the operation of various processing units within wireless device 800.
• a memory 862 stores program codes and data for wireless device 800.
• a VCO/PLL 822 generates clock signals for the processing units within digital processor 810.
• a VCO/PLL 850 generates a transmit LO signal used by mixer 834 for frequency upconversion and a receive LO signal used by mixer 844 for frequency downconversion.
• VCO/PLL 822 and VCO/PLL 850 may each employ linear phase frequency detector and charge pump to improve performance.
• a reference oscillator 864 generates a reference signal for VCO/PLL 822 and/or VCO/PLL 850.
• Reference oscillator 864 may be a crystal oscillator (XO), voltage-controlled XO (VCXO), a temperature-compensated XO (TCXO), or some other type of oscillator.
• phase frequency detector, charge pump, and PLL described herein may be implemented in an analog IC, an RFIC, an ASIC, a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a micro-controller, a microprocessor, and other electronic units.
• the phase frequency detector, charge pump, and PLL may be fabricated with various IC process technologies such as N-MOS, P- MOS, CMOS, BJT, GaAs, and so on.
• the phase frequency detector, charge pump, and PLL may also be implemented with discrete components.

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