WO2008026273A1 - Contrôleur dma - Google Patents

Contrôleur dma Download PDF

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Publication number
WO2008026273A1
WO2008026273A1 PCT/JP2006/317191 JP2006317191W WO2008026273A1 WO 2008026273 A1 WO2008026273 A1 WO 2008026273A1 JP 2006317191 W JP2006317191 W JP 2006317191W WO 2008026273 A1 WO2008026273 A1 WO 2008026273A1
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WO
WIPO (PCT)
Prior art keywords
circuit
reconfigurable
data
configuration information
configuration
Prior art date
Application number
PCT/JP2006/317191
Other languages
English (en)
Japanese (ja)
Inventor
Yoshio Hirose
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2008531929A priority Critical patent/JPWO2008026273A1/ja
Priority to PCT/JP2006/317191 priority patent/WO2008026273A1/fr
Publication of WO2008026273A1 publication Critical patent/WO2008026273A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the present invention relates to a DMA controller mounted on a semiconductor integrated circuit.
  • FIG. 24A and FIG. 24B are block diagrams of conventional system LSIs.
  • FIG. 24A is a block diagram of the system LSI when all processing is executed by the processor
  • FIG. 24B is a block diagram of the system LSI provided with dedicated hardware for performing a part of the processing of the application.
  • the system LSI 11 in FIG. 24A includes a processor core 12, an internal memory 13, a memory controller 14, and a DMA controller 15.
  • the processor core 12 executes all the processes requested by the application.
  • the memory controller 14 controls writing and reading of data to the external memory 16.
  • the system LSI 21 in FIG. 24B includes a processor core 12, a memory 13, a memory controller 14, a DMA controller 15, and a plurality of hardware circuits 17a to 17n.
  • dedicated hardware 17a to 17n executes part of the processing required by the application.
  • Patent Document 1 describes an integrated circuit including a connection path for connecting a plurality of computing units in a changeable manner, and dedicated hardware and a processor capable of changing processing specifications by parameter setting.
  • Patent Document 2 describes that data transfer to a reconfigurable logic device can be performed using an instruction set of a general-purpose controller.
  • a reconfigurable logic circuit is used instead of the nodeware circuit 17a to 17n shown in FIG. 24B.
  • the DMA controller 15 transfers the data to the reconfigurable circuit, and the data processed by the reconfigurable logic circuit is transferred to the DMA controller. 15 needs to transfer to the processor core 12 and data transfer takes time.
  • Patent Document 1 Japanese Patent Laid-Open No. 2004-40188
  • Patent Document 2 Japanese Patent Laid-Open No. 11-307725
  • An object of the present invention is to improve the data transfer efficiency of a DMA controller mounted on a semiconductor integrated circuit.
  • the DMA controller of the present invention is mounted on a semiconductor integrated circuit having a processor.
  • a DMA controller includes a configuration information storage circuit that stores configuration information that specifies a circuit configuration, and a reconfigurable circuit that can change the circuit configuration based on the configuration information of the configuration information storage circuit. Prepare.
  • the data is transferred to the input data in order to be processed by a circuit outside the DMA controller.
  • the efficiency of MA transfer can be increased.
  • the reconfigurable circuit includes an input selection circuit that selects one of input data and output data of the reconfigurable circuit and outputs the selected data to the reconfigurable circuit.
  • the first processing is performed on the input data based on the circuit configuration determined by the first configuration information stored in the configuration information storage circuit, and the intermediate data subjected to the first processing is input as the input data.
  • Input to the reconfigurable circuit via a selection circuit and perform a second process on the intermediate data based on a circuit configuration determined by the second configuration information stored in the configuration information storage circuit .
  • output from the configuration information storage circuit to the reconfigurable circuit A control circuit that changes the configuration information to change the circuit configuration of the reconfigurable circuit.
  • control circuit can arbitrarily change the circuit configuration of the reconfigurable circuit by changing the configuration information output from the configuration information storage circuit.
  • the reconfigurable circuit is composed of a plurality of reconfigurable combination circuits connected in cascade
  • the configuration information storage circuit is a plurality of reconfigurable combination circuits corresponding to the plurality of reconfigurable combination circuits. It comprises a configuration information storage circuit, and has an output selection circuit that selects and outputs one of the outputs of the plurality of reconfigurable combinational circuits.
  • the reconfigurable circuit is a plurality of cascaded reconfigurable combinational circuit powers, and the output of the reconfigurable combinational circuit of the input data and the final stage
  • An input selection circuit that selects one of the data and outputs it to the first reconfigurable circuit, and an output selection circuit that selects and outputs one of the outputs of the plurality of reconfigurable combinational circuits.
  • the reconfigurable circuit is a plurality of cascaded reconfigurable combinational circuit forces, and a final stage reconfigurable combinational circuit force is output.
  • Select one of the intermediate buffer that holds the data, the input data, the output of the intermediate buffer, and the output data of the reconfigurable combinational circuit of the final stage to make the reconfigurable circuit of the first stage An output selection circuit for selecting and outputting one of the outputs of the plurality of reconfigurable combinational circuits. Selection circuit.
  • the reconfigurable circuit includes a plurality of reconfigurable combination circuits connected in cascade, and the configuration information storage circuit includes the plurality of reconfigurable combinations.
  • a plurality of reconfigurable combinational circuits when the output data of the reconfigurable combinational circuit in the final stage is fed back to the input side for processing. It has a control circuit that performs control to change the configuration in order in units of processing cycles.
  • FIG. 1 is a diagram showing a configuration of a system LSI according to an embodiment.
  • FIG. 2 is a diagram illustrating a configuration of a DMA controller according to the embodiment.
  • FIG. 3 is a block diagram of a reconfigurable circuit according to the first embodiment.
  • FIG. 4 is a timing chart of the first embodiment.
  • FIG. 5 is a block diagram of a reconfigurable circuit according to the second embodiment.
  • FIG. 6 is a timing chart of the second embodiment.
  • FIG. 7 is a block diagram of a reconfigurable circuit according to a third embodiment.
  • FIG. 8 is a timing chart of the third embodiment.
  • FIG. 9 is a block diagram of a reconfigurable circuit according to a fourth embodiment.
  • FIG. 10 is a timing chart of the fourth embodiment.
  • FIG. 11 is a block diagram of a reconfigurable circuit according to a fifth embodiment.
  • FIG. 12 is a timing chart of the fifth embodiment.
  • FIG. 13 is a block diagram of a reconfigurable circuit according to a sixth embodiment.
  • FIG. 14 is a block diagram of a reconfigurable circuit according to a seventh embodiment.
  • FIG. 15 is a diagram showing a configuration of a control circuit.
  • FIG. 16 is a circuit diagram of a CM control signal generation circuit.
  • FIG. 17 is a circuit diagram of a se control signal generation circuit.
  • FIG. 18 is a circuit diagram of a sel2 control signal generation circuit.
  • FIG. 19 is a circuit diagram of an update signal generation circuit.
  • FIG. 20 is a circuit diagram of an update timing signal generation circuit.
  • FIG. 21 is a timing chart of the control circuit.
  • FIG. 22 is a block diagram of an image processing LSI.
  • FIG. 23 is a block diagram of an image processing LSI according to an embodiment.
  • FIG. 24A is a block diagram of a conventional system LSI.
  • FIG. 24B is a block diagram of a conventional system LSI.
  • FIG. 1 is a diagram showing a configuration of the system LSI 31 in the embodiment.
  • the system LSI 31 includes a processor core 32, an internal memory 33, a memory controller 34 that controls access to the external memory 36, and a DMA controller (DMAC) 35 having a reconfigurable circuit.
  • the processor core 32, the internal memory 33, the memory controller 34, and the DMA controller 35 are connected by a bus 37 !.
  • FIG. 2 is a diagram showing a configuration of the DMA controller 35.
  • the DMA controller 35 includes a bus interface circuit 41, a control register group 42, a control circuit 43, a plurality of buffers 44a to 44n, and a reconfigurable circuit 45.
  • the reconfigurable circuit 45 is, for example, a switching circuit that changes the connection between a plurality of arithmetic circuits or logic circuits and those circuits, and performs different processing on input data by changing the combination of the circuits. can do.
  • the control register group 42 is a register for storing information necessary for DMA transfer, and stores a DMA transfer source address, a transfer destination address, a data transfer size, and a configuration information memory address to be described later for each channel.
  • the update cycle, output selection circuit selection signal, etc. It consists of a number register.
  • the buffers 44a to 44n are memories for storing input data for performing DMA transfer, and may be provided for each channel or may be shared between channels!
  • the control circuit 43 outputs various control signals that change the configuration of the reconfigurable circuit 45 based on the information stored in the control register group 42.
  • FIG. 3 is a block diagram of the reconfigurable circuit 51 of the first embodiment provided in the DMA controller 35.
  • the reconfigurable circuit 51 includes a reconfigurable combination circuit 52 and a configuration information memory (CM: configuration memory) for storing configuration information that determines the circuit configuration of the reconfigurable combination circuit 52. And an output buffer 54 for storing data output from the reconfigurable combinational circuit 52.
  • CM configuration information memory
  • the reconfigurable combinational circuit 52 has a flip-flop (FF) 52a at the output stage, and data of the processing result is held in the flip-flop 52a.
  • the configuration information memory 53 is supplied with a CM control signal (address information) designating configuration information from the control circuit 43, and outputs the configuration information designated by the CM control signal to the reconfigurable combinational circuit 52.
  • the clock signal elk is a signal synchronized with the processing cycle, and the reconfigurable combinational circuit 52 latches input data at the rising timing of the clock signal elk.
  • the configuration information memory 53 stores a plurality of pieces of configuration information for determining the circuit configuration of the reconfigurable combination circuit 52 in advance, and the circuit configuration of the reconfigurable combination circuit 52 is uniquely determined based on the configuration information. It is done.
  • the reconfigurable yarn combining circuit 52 When the input data 2 is also output as the force of the notifier 44a (buffer 1 in FIG. 4), the reconfigurable yarn combining circuit 52 performs processing of a predetermined circuit configuration on the input data 2.
  • the processing result data (processing data 2) is held in the flip-flop 52a and output to the output buffer 54.
  • the reconfigurable combinational circuit 52 performs processing of a predetermined circuit configuration on the input data 3.
  • the processing result data (processing data 3) is held in the flip-flop 52a and output to the output buffer 54.
  • the processing data 2 and processing data 3 stored in the output buffer 54 are output to the processor core 32 and the like via the bus interface circuit 41.
  • the DMA transfer processing for transferring data to a circuit outside the DMA controller 35 for data processing since the reconfigurable circuit 51 is provided in the DMA controller 51, the DMA transfer processing for transferring data to a circuit outside the DMA controller 35 for data processing.
  • DMA transfer processing for transferring data processed by an external circuit to the processor core 32 is not required, and the data transfer time can be shortened to increase the transfer efficiency of DMA transfer.
  • FIG. 5 is a block diagram of a reconfigurable circuit 61 according to the second embodiment.
  • a feature of the second embodiment is that an input selection circuit 62 is provided on the input side of the reconfigurable circuit 61.
  • the input selection circuit 62 selects one of the input data and the output of the reconfigurable combinational circuit 52 and outputs it to the reconfigurable combinational circuit 52. This selection operation is performed according to the sel control signal output from the control circuit 43.
  • the processing result of the reconfigurable combinational circuit 52 having a certain circuit configuration is fed back to the input side, and then the circuit configuration of the reconfigurable combinational circuit 52 is changed. Another process can be performed on the data being processed. In other words, by changing the configuration of the reconfigurable combinational circuit 52, it is possible to execute processing of circuits with different hardware configurations for one piece of data.
  • the circuit scale of the reconfigurable circuit 61 can be reduced as compared with FIG.
  • processing latency is 2
  • the control circuit 43 transmits a CM control signal (information specifying a memory address) that specifies "configuration 1". Information) to the configuration information memory 53.
  • CM control signal information specifying a memory address
  • Information Information
  • the circuit configuration of the reconfigurable combinational circuit 52 is set to the state of “configuration 1”. Performs processing by the circuit of “Configuration 1”.
  • the control circuit 43 outputs a CM control signal designating “configuration 2” to the configuration information memory 53 in the next cycle (second cycle) and enables the sel control signal.
  • the input selection circuit 62 selects the output data (intermediate data 1) of the reconfigurable combinational circuit 52 and outputs it to the reconfigurable combinational circuit 52. Accordingly, in the second cycle, the reconfigurable combinational circuit 52 executes the process by the circuit of “Configuration 2” for the intermediate data 1.
  • the intermediate data processed by the reconfigurable combinational circuit 52 is fed back to the input side, and processing of a different circuit configuration is executed for one input data by changing the circuit configuration. be able to.
  • the configuration of the combinational circuit 52 that can be reconfigured with respect to the input data 2 and the input data 3 is changed into two states of “configuration 1” and “configuration 2”, respectively.
  • the circuit configuration of the reconfigurable combinational circuit 52 is changed to “configuration 2”.
  • the “configuration 2” process is performed on the data of the second process result (intermediate data 2).
  • the same processing is performed for input data 3.
  • data obtained by processing the input data 2 and 3 with the “Configuration 1” circuit and the “Configuration 2” circuit, respectively, is obtained.
  • the input circuit when there is a force S required to perform a plurality of processes on input data, the input circuit can be changed by changing the circuit configuration of the reconfigurable combinational circuit 52. Processing can be realized with fewer reconfigurable combinational circuits 52 than the required number of data processing times. As a result, the circuit scale of the reconfigurable combinational circuit 52 for realizing the processing required for the input data can be reduced, and the device area on the integrated circuit can be reduced.
  • DMA processing of data in the DMA controller 35 is not required because the processing of transferring data to the external circuit by the external circuit or the processing of transferring the data of the processing result of the external circuit by DMA is not necessary. Efficiency can be increased.
  • FIG. 7 is a block diagram of a reconfigurable circuit 71 according to the third embodiment.
  • reconfigurable combinational circuits are connected in cascade in n stages (3 stages in FIG. 7) so that input data can be processed continuously.
  • the reconfigurable circuit 71 includes a cascade-connected stage 1 reconfigurable combination circuit 72, a stage 2 reconfigurable combination circuit 73, and a stage 3 It comprises a reconfigurable combination circuit 74, configuration information memories 75 to 77 for storing configuration information of the respective reconfigurable combination circuits 72 to 74, and an output selection circuit 78.
  • the output selection circuit 78 includes the output of the stage 1 reconfigurable combinational circuit 72, the output of the stage 2 reconfigurable combinational circuit 73, and the stage 3 reconfigurable combinational circuit. Select one of the 74 outputs for output. The selection operation of the output selection circuit 78 is performed according to the sel2 control signal output from the control circuit 43.
  • the reconfigurable circuit 71 is configured so that the reconfigurable combinational circuit 73 of stage 2 performs the first input data when the processing latency of 2 is executed.
  • the next input data can be processed by the reconfigurable combinational circuit 72 of stage 1 at the same time. Therefore, even if the processing latency is 2 or more, the processing result data can be output from the reconfigurable circuit 71, so that the throughput is 1.
  • the operation of the reconfigurable circuit 71 when the input data 1 to 4 for which the processing latency is “2” is continuously input will be described with reference to the timing chart of FIG. .
  • “Configuration 1” is designated as the circuit configuration of the reconfigurable combinational circuit 72 in stage 1
  • “Configuration 2” is designated as the circuit configuration of the reconfigurable combinational circuit 73 in stage 2 To do.
  • the reconfigurable combination circuit 72 of stage 1 when input data 1 is input to the reconfigurable combination circuit 72 of stage 1, the reconfigurable combination circuit 72 is configured as “configuration 1 ”Is executed.
  • the processing result data (intermediate data 1) at this time is held in the flip-flop 72a during the next cycle (second cycle).
  • the reconfigurable combinational circuit 72 performs “configuration 1” hardware for the input data 2. Perform circuit processing.
  • the processing result data (intermediate data 2) at this time is held in the flip-flop 72a during the next cycle (third cycle).
  • the reconfigurable combinational circuit 73 of stage 2 is held in the flip-flop 72a at that time! And executes the processing of the hardware circuit of “configuration 2” on the intermediate data 1 To do.
  • the processing result data (processing data 1) at this time is held in the flip-flop 73a during the next cycle (third cycle).
  • the reconfigurable combinational circuit 72 of stage 1 when the input data 3 is input to the reconfigurable combinational circuit 72 of stage 1, the reconfigurable combinational circuit 72 is configured with the “configuration 1” hardware for the input data 3. Perform circuit processing.
  • the processing result data (intermediate data 3) at this time is held in the flip-flop 74a during the next cycle (fourth cycle).
  • the reconfigurable combinational circuit 73 of stage 2 executes the processing of the hardware circuit of "configuration 2" for the intermediate data 2 held at that time in the flip-flop 72a.
  • the processing result data (processing data 2) at this time is held in the flip-flop 73a during the next cycle (fourth cycle).
  • the output selection circuit 78 since the output selection circuit 78 is given the sel2 control signal for selecting the output of the reconfigurable combinational circuit 73 in stage 2, the output selection circuit 78 Selects processing data 1 held in the flop 73a and outputs it. In the next cycle (fourth cycle), the processing data 1 is output from the bus interface circuit 41 to the data bus 37.
  • the reconfigurable combinational circuit 72 performs the “configuration 1” hardware for the input data 4. Perform circuit processing.
  • the processing result data (intermediate data 4) at this time is held in the flip-flop 72a during the next cycle (fifth cycle).
  • the reconfigurable combinational circuit 73s of stage 2 executes the processing of the hardware circuit of "configuration 2" for the intermediate data 3 held in the flip-flop 72a at that time.
  • the processing result data (processing data 3) at this time is held in the flip-flop 73a during the next cycle (fifth cycle).
  • the output selection circuit 78 selects and outputs the processing data 2 held in the flip-flop 73a of the stage 2 at that time. Then, in the next cycle, the processed data 2 is output from the no interface circuit 41 to the data bus 37. Similarly, the processing data 3 is output from the output selection circuit 78 in the fifth cycle, and the processing data 4 is output from the output selection circuit 78 in the sixth cycle.
  • data having a processing latency of two cycles or more can be obtained by connecting the reconfigurable combinational circuits 72 to 73 in cascade and performing processing in parallel.
  • the data can be input / output every cycle.
  • the processing throughput of the reconfigurable circuit 71 can be improved.
  • the DMA transfer process for processing the input data by other circuits in the integrated circuit, or the data of the processing result This eliminates the need for DMA transfer processing, and improves the transfer efficiency of DMA transfer of data from the DMA controller 35.
  • FIG. 9 is a block diagram of a reconfigurable circuit 81 according to the fourth embodiment.
  • reconfigurable combinational circuits 82 and 83 are connected in cascade (two stages in FIG. 9), and the output of the reconfigurable combinational circuit 83 in the final stage is fed back to the input side.
  • the reconfigurable circuit 81 shown in FIG. 9 comprises a cascaded stage 1 reconfigurable combinational circuit 82 and a stage 2 reconfigurable combinational circuit 83, each reconfigurable Configuration information memories 84 and 85 for storing configuration information of the combinational circuits 82 and 83, an input selection circuit 86, an output selection circuit 87, and an intermediate buffer 88.
  • the output of the stage 2 reconfigurable combinational circuit 83 is fed back to the input selection circuit 86, either directly or through an intermediate notch 88.
  • the input selection circuit 86 selects one of the input data, the output of the intermediate buffer 88, and the output of the stage 2 reconfigurable combinational circuit 83 to select the stage 1 reconfigurable combination. Output to circuit 82.
  • the input selection circuit 86 performs a selection operation based on the sel control signal output from the control circuit 43.
  • the intermediate buffer 88 is a memory that stores a plurality of intermediate data processed by the stage 2 reconfigurable combinational circuit 83, and outputs the stored intermediate data to the input selection circuit 86.
  • the output selection circuit 87 selects and outputs one of the output of the reconfigurable combinational circuit 82 in stage 1 and the output of the reconfigurable combinational circuit 83 in stage 2.
  • the selection operation of the output selection circuit 87 is performed according to the sel2 control signal output from the control circuit 43.
  • the timing chart of FIG. 10 shows the output of the bus interface circuit 41, the output of the buffers 44a to 44d, and the flip-flops of the stage 1 and stage 2 when the input data 1 to 4 having a processing latency of “4” are continuously input. 82a and 83a and the output of the intermediate buffer 88 are shown.
  • the reconfigurable combinational circuits 82 and 83 of the first stage 1 and the final stage 2 are assumed to have the “configuration 1” circuit configuration selected.
  • the reconfigurable combinational circuit 83 of stage 2 is held in the flip-flop 82a of the previous stage at that time!
  • the processing of the hardware circuit of "configuration 1" with respect to the intermediate data 1 Execute.
  • the processing result data (intermediate data 1 ′) at this time is held in the flip-flop 83a during the next cycle (third cycle).
  • the reconfigurable combinational circuit 82 performs “configuration 1” hardware for the input data 3. Perform circuit processing.
  • the processing result data (intermediate data 3) at this time is held in the flip-flop 82a during the next cycle (fourth cycle).
  • the reconfigurable combinational circuit 83 of stage 2 executes the processing of the hardware circuit of “configuration 1” on the intermediate data 2 held in the flip-flop 82a of the previous stage at that time To do.
  • the processing result data (intermediate data 2 ′) at this time is held in the flip-flop 82a during the next cycle (fourth cycle).
  • the reconfigurable combinational circuit 82 is configured as “configuration 1” hardware for the input data 4. Perform circuit processing.
  • the processing result data (intermediate data 4) at this time is held in the flip-flop 82a during the next cycle (fifth cycle).
  • the reconfigurable combinational circuit 83 of stage 2 executes the processing of the hardware circuit of “configuration 1” with respect to the intermediate data 3 held in the flip-flop 82a of the previous stage at that time To do.
  • the processing result data (intermediate data 3 ′) at this time is held in the flip-flop 83a during the next cycle (fifth cycle).
  • intermediate data 1 ′, intermediate data 2 ′, intermediate data 3 ′, and intermediate data 4 ′ which are output data of the reconfigurable combinational circuit 83 in stage 2, are stored in the intermediate buffer 88 in order.
  • stage 2 for input data 4 After the processing in stage 2 for input data 4 is completed, that is, the circuit configurations of combinational circuits 82 and 83 that can be reconfigured at the start time tl of the sixth cycle are changed from "configuration 1" to "configuration 2" To change at the same time.
  • the control circuit 43 outputs a sel control signal that causes the input selection circuit 86 to select the output of the intermediate buffer 88. Therefore, after the sixth cycle, the intermediate data stored in the intermediate buffer 88 by the input selection circuit 86 is selected and input to the reconfigurable combinational circuit 82 of the selected intermediate data force S stage 1.
  • the reconfigurable combinational circuit 82 of stage 1 executes the processing of the hardware circuit of "configuration 2" for the intermediate data 1 'output from the intermediate buffer 88. At this time, no data is output from the reconfigurable combinational circuit 82 in stage 1, and this period is an empty period of output data in stage 1.
  • the reconfigurable combinational circuit 82 of stage 1 executes the processing of the hardware circuit of "configuration 2" on the intermediate data 2 'output from the intermediate buffer 88.
  • the processing result data (intermediate data 2 ′′) at this time is held in the flip-flop 82a of the stage 1 in the next cycle (eighth cycle).
  • intermediate data 3 'and intermediate data 4' are output from the intermediate buffer 88 to the reconfigurable combinational circuit 82 in stage 1, and "configuration" is performed for these intermediate data.
  • 2 hardware circuit processing is executed.
  • reconfigurable combinational circuit 83 the data of the processing result of stage 1 is 2 "hardware circuit processing is executed.
  • the processing for the input data 1 to 4 of the processing latency 4 can be realized by using the two reconfigurable combinational circuits 82 and 83 by the circuit operation as described above.
  • the reconfigurable circuit 81 is configured with a plurality of stages, and data with a large processing latency is reduced by returning the data of the final stage to the first stage. It is possible to process with the circuit. As a result, the device area of the reconfigurable circuit 81 formed on the semiconductor integrated circuit can be reduced. In addition, by changing the circuit configuration of each stage in the first and second time, processing of different hardware circuits for the same data can be realized with a small circuit scale.
  • the data is transferred by DMA to process the input data by another circuit in the integrated circuit, or the processing result data is transferred. Since there is no need for DMA transfer, the transfer efficiency of data DMA transfer can be improved.
  • a path for returning the output of the force output selection circuit that returns the output of the final stage to the top stage is provided to the top stage, and the number of stages and input data are processed. Depending on the latency, the output data of the stage selected by the output selection circuit 87 may be returned to the first stage.
  • This empty cycle problem also occurs when different processes are executed for each channel in a reconfigurable circuit. For example, in a reconfigurable circuit with multiple stage powers, if you perform ⁇ Configuration 1 '' processing on channel 1 data and ⁇ Configuration 2 '' processing on channel 2 data, Channel 1 data and channel 2 data are continuous However, the hardware configuration of the entire stage cannot be changed until the final stage processing for the channel 1 data is completed. Therefore, also in this case, if the number of stages is n, there will be (n-1) cycles of free space.
  • FIG. 11 is a block diagram of a reconfigurable circuit 91 according to the fifth embodiment of the present invention that solves the problem of the above empty cycle.
  • the occurrence of an empty cycle is prevented by sequentially changing the circuit configuration of each stage of the reconfigurable circuit 91.
  • the reconfigurable circuit 91 shown in FIG. 11 includes four stages of reconfigurable combination circuits 92, 93, 94, 95 in a pipeline configuration, and four configuration information memories 96 for storing configuration information. 97, 98, 99, three flip-flops 100, 101, 102, human selection circuit 103, and output selection circuit 104.
  • the flip-flops 100, 101, and 102 sequentially latch the CM control signal at a timing synchronized with the cycle of one cycle (processing cycle).
  • the reconfigurable combinational circuits 92 to 95 have flip-flops 92a to 95a that hold data of processing results.
  • the timing chart in Figure 12 shows that channel 1 input data 1 to 4 and channel 2 input data 1 to 4 with a processing latency of ⁇ 4 '' are input to channel 1 input data 1 to 4 in succession.
  • ⁇ Configuration 1 '' is processed in stages 1 to 4! ⁇
  • the operation timing when ⁇ Configuration 2 '' is processed in stages 1 to 4 for channel 2 input data 1 to 4 is shown. .
  • the reconfigurable circuit 81 of the fourth embodiment shown in FIG. 9 processes the input data of the above two channels, the process at the final stage for the fourth data of channel 1 is performed.
  • the circuit configuration of each stage cannot be changed until the end. Therefore, three cycles are waited until the input data of channel 2 is input to the reconfigurable circuit 81, and an empty cycle is generated accordingly.
  • the last input data 4 of channel 1 is input to stage 1, and the processing in stage 1 for the input data 4 is completed.
  • the circuit configuration of the reconfigurable combinational circuit 92 in stage 1 is changed from “configuration 1” to “configuration 2”.
  • the circuit configurations of the other stages 2 to 4 are not changed.
  • the circuit configuration of the reconfigurable combinational circuit 93 in stage 2 is changed to “configuration 2”.
  • the circuit configuration of the reconfigurable combinational circuit 94 in stage 3 is changed to “configuration 2” at the start time t3 of the next third cycle.
  • the circuit configuration of the stage 4 reconfigurable combinational circuit 95 is changed to “configuration 2”.
  • the change of the circuit configuration of each stage is realized by sequentially shifting the CM control signal for specifying the configuration information to the flip-flops 100, 101, and 102 in FIG.
  • the reconfigurable combinational circuit 92 of stage 1 is output from the buffer 44i (refers to a specific buffer among the buffers 44a to 44n).
  • the processing of the hardware circuit of “Configuration 2” is executed for the first input data 1 of channel 2 to be processed.
  • Data of the processing result at this time (data D1 indicated by hatching in FIG. 12) is held in the flip-flop 92a of stage 1 in the next cycle (second cycle).
  • the CM control signal is latched in the flip-flop 100, and the CM control signal designating "configuration 2" is output to the configuration information memory 97 of stage 2.
  • “configuration 2” configuration information is output from the configuration information memory 97, and the circuit configuration of the stage 2 reconfigurable combinational circuit 93 is changed to “configuration 2”.
  • the reconfigurable combinational circuit 92 of stage 1 executes the processing of the hardware circuit of “configuration 2” on the second input data 2 of channel 2, and the stage The second reconfigurable combinational circuit 93 is held in the stage 1 flip-flop 92a at that time! And executes the processing of the “configuration 2” hardware circuit on the data D1.
  • Stage 1 processing result data D2 and Stage 2 processing result data D1 are the stage 1 flip-flops during the next cycle (third cycle), respectively. 92a and stage 2 flip-flop 93a.
  • the CM control signal force is latched in the flip-flop 101 and is output to the configuration information memory 98 of the address force stage 2 designating “configuration 2”.
  • the configuration information of “configuration 2” is output from the configuration information memory 98, and the circuit configuration power S of the combination circuit 94 that can be reconfigured in stage 3 is changed to “configuration 2”.
  • the reconfigurable combinational circuit 92 of stage 1 executes the processing of the hardware circuit of “configuration 2” for the third input data 3 of channel 2, and the stage The second reconfigurable combinational circuit 93 executes the processing of the “configuration 2” hardware circuit on the data D2 held in the flip-flop 92a of the stage 1 at that time. Furthermore, the stage 3 reconfigurable combinational circuit 94 is then held in the stage 2 flip-flop 93a! And executes the processing of the hardware circuit of “configuration 2” on the data D1.
  • the CM control signal force is latched in the flip-flop 102 and output to the configuration information memory 99 of the address force stage 4 designating “configuration 2”.
  • the configuration information of “configuration 2” is output from the configuration information memory 99, and the circuit configuration power S of the combinational circuit 95 that can be reconfigured in stage 4 is changed to “configuration 2”.
  • the reconfigurable combinational circuit 92 of stage 1 executes the processing of the hardware circuit of “configuration 2” for the fourth input data 4 of channel 2, and the stage The second reconfigurable combinational circuit 93 executes the processing of the “configuration 2” hardware circuit on the data D3 held in the flip-flop 92a of the stage 1 at that time.
  • the reconfigurable combinational circuit 94 in stage 3 executes the processing of the hardware circuit in “configuration 2” for the data D2 held in the flip-flop 93a in stage 2 at that time.
  • the reconfigurable combinational circuit 95 in the stage 4 performs the processing of the hardware circuit in “configuration 2” on the data D1 held in the flip-flop 94a in the stage 3 at that time.
  • the output of the reconfigurable combinational circuits 92 to 95 at each stage is changed. It is possible to prevent a free cycle from occurring. As a result, the processing efficiency of the reconfigurable circuit 91 can be increased.
  • FIG. 13 is a block diagram of a reconfigurable circuit 201 according to the sixth embodiment of the present invention.
  • the difference between the sixth embodiment and the fifth embodiment is that the configuration information of the configuration information memories 202 to 205 can be set from the processor core 32.
  • the processor core 32 When changing the circuit configuration of the reconfigurable circuit 201, the processor core 32 outputs the configuration information to be changed to the data bus 37 and instructs the control circuit 43 to write the configuration information.
  • the control circuit 43 outputs the write addresses of the configuration information memories 202 to 205 to be written as CM control signals.
  • the configuration information output to the data bus 37 is written to the address of the configuration information memory 202 specified by this CM control signal.
  • the circuit configuration of the reconfigurable combinational circuit 92 in stage 1 is changed to a configuration corresponding to the configuration information written at that time.
  • the CM control signal is latched in flip-flop 100 at the rising edge of the next clock signal elk (signal synchronized with the cycle). Then, the configuration information output from the processor core 32 is written to the corresponding address in the configuration information memory 203 of the stage 2 specified by this CM control signal. As a result, the circuit configuration of the reconfigurable combinational circuit 93 in stage 2 is changed based on the configuration information written in the configuration information memory 203 at that time. At this time, if the configuration information output from the processor core 32 to the data bus 37 is changed, the stage 2 circuit configuration can be made different from the stage 1 circuit configuration.
  • the CM control signal is latched in flip-flop 101 at the rising edge of the next cycle.
  • the stage 3 configuration information memory 204 specified by the CM control signal The configuration information currently output to data node 37 is written to the corresponding address.
  • the circuit configuration capability of the reconfigurable combinational circuit 204 in stage 3 is changed based on the configuration information written in the configuration information memory 204 at that time.
  • the CM control signal is latched in flip-flop 102 at the rise timing of the next cycle. Then, the configuration information output to the data node 37 at that time is written in the corresponding address of the configuration information memory 205 of the stage 4 specified by the CM control signal. As a result, the circuit configuration of the reconfigurable combinational circuit 95 in stage 4 is changed based on the configuration information written in the configuration information memory 205 at that time.
  • the processor core 32 can individually set the configuration information of the configuration information memories 202 to 205 of each stage.
  • the circuit configuration of each stage can be changed individually. As a result, it is possible to prevent an empty cycle from occurring in the output of the reconfigurable circuit 201, and to increase the data processing efficiency of the reconfigurable circuit 201.
  • the data is DMA-transferred to another circuit of the integrated circuit that executes specific hardware processing on the input data. This eliminates the need for DMA transfer of the processing result data, thereby reducing the data transfer time.
  • FIG. 14 is a block diagram of a reconfigurable circuit 301 according to the seventh embodiment of the present invention.
  • the difference between the seventh embodiment and the sixth embodiment is that the configuration information is written into the configuration information memories 302 to 305 as part of the DMA transfer.
  • the processor core 34 When rewriting the configuration information in the configuration information memories 302 to 305, the processor core 34 is used for a specific channel (a specific channel that only writes to the configuration information memory) or for general data transfer. The configuration information is output on the data bus 37 using the channel. At the same time, the processor core 34 instructs the control circuit 43 to write the configuration information to the specific configuration information memory.
  • a dedicated CM control signal is output from the control circuit 43 to each of the configuration information memories 302 to 305, and the input data selected by the selector 103 is used as each configuration information memory.
  • Mori 302 ⁇ 305 [Take this power!] Therefore, an arbitrary configuration ⁇ CM control signal that specifies the write address of the blueprint memories 302 to 305 is output, and the processor core 32 outputs the configuration information as input data, so that each configuration information memory 302 to 305 is individually output.
  • Arbitrary configuration information can be written in
  • the processor core 32 outputs specific configuration information as input data, and the control circuit 43 outputs a CM control signal that specifies the write address of the configuration information memory 302 of stage 1, Desired configuration information can be written into the stage 1 configuration information memory 302.
  • the configuration information written in the configuration information memory 302 is output to the stage 1 reconfigurable combinational circuit 92, and the circuit configuration of the stage 1 is changed based on the configuration information.
  • Configuration information can be written to the configuration information memories 303 to 305 in other stages in the same manner.
  • the processor core 32 can individually write the configuration information in the configuration information memories 302 to 305 of each stage using DMA transfer. This makes it possible to change the configuration of the reconfigurable combinational circuits 92 to 95 in each stage in order and process the data continuously in each stage, so that the reconfigurable combinational circuits 92 to 95 are available. It is possible to prevent a free cycle from occurring in the output of data and to improve the data processing efficiency.
  • FIG. 15 is a diagram showing the configuration of the control circuit 43.
  • the control circuit 43 generates a CM control signal that specifies a write address of the configuration information memory, a CM control signal generation circuit 401 that generates a CM control signal, and a se control signal that generates a se control signal that is a selection signal of the input selection circuit 103 and the like. It has a signal generation circuit 402 and a sel2 control signal generation circuit 403 that generates a sel2 control signal that is a selection signal for the output selection circuit 104 and the like.
  • control circuit 43 generates a start signal indicating that a reconfigurable circuit is available.
  • a start signal generation circuit 404 that generates a channel Ch signal
  • a channel selection signal generation circuit 405 that generates a channel Ch selection signal
  • an update signal generation circuit 406 that generates an update signal indicating an address update period of the configuration information memory 84, etc.
  • An update timing signal generation circuit 407 that generates an update_timing signal, and another control signal generation circuit 408.
  • control register group 42 in FIG. 2 will be described. Although not shown in FIG. 2, the control register group 42 includes the following five types of registers.
  • CM address registers CM—ADRS—l to n hold the start address of the configuration information memory 84 and the like.
  • the repeat register RPT — l to n contains data that is being processed at the beginning of a pipeline (stage) such as the reconfigurable circuit 81 in order to complete the requested processing for the input data. Is held repeatedly.
  • the output selection register OUTSEL-l to n holds the selection signal of the output selection circuit 87 and the like.
  • the updater registers UPDATE—l to n hold the cycle for updating the address of the configuration information memory 84 and the like.
  • the transfer burst length registers BST-l to n hold the value obtained by subtracting “1” from the transfer burst length of the input data. For example, if the burst length of data is “4”, “3” is stored in the corresponding transfer burst length registers BSTl to n.
  • FIG. 16 is a circuit diagram of the CM control signal generation circuit 401.
  • the CM post-natal signal generation circuit 401 includes a selector 501, a flip-flop 502, and an adder 503.
  • the selector 501 selects the value of the CM address register CM—ADRS—l to n specified by the channel selection signal and outputs it to the CM address counter 502.
  • the selector 501 selects a value obtained by adding “+1” to the output of the flip-flop 502 when the signal obtained by inverting the start signal with the inverter INV1 is enabled, that is, when the start signal is disabled. And output to the flip-flop 502.
  • the flip-flop 502 latches the output of the selector 501 at a timing synchronized with the cycle when the start signal or the update signal input to the OR gate OR1 is enabled.
  • F The lip flop 502 functions as a CM address counter, and when the start signal is enabled, the value of a specific CM address register in the CM address registers CM—ADRS—l to n is loaded as an initial value.
  • the address is output as a CM control signal. Each time an update signal is input, the address “+1” is output as a CM control signal.
  • FIG. 17 is a circuit diagram of the sel control signal generation circuit 402.
  • the sel control signal generating circuit 402 selects the initial value “1”, one of the outputs of the subtracting circuit 513 and outputs it, and the output of the selector 511 is the value of the upper bit (first bit) of the sel control signal.
  • the sel control signal generation circuit 402 also includes a flip-flop 515 that holds the value of the designated register in the transfer burst length registers BST-1 to n, and whether the output of the flip-flop 515 is “0”. And a determination circuit 516 for outputting the determination result as the value of the lower bit (0th bit) of the sel control signal.
  • the selector 511 outputs “1” when the start signal is enabled, and when the signal obtained by inverting the start signal with the inverter INV2 becomes enabled, that is, the start signal is disabled.
  • the sel flag value is “-1”, the value is output.
  • the flip-flop 512 loads the initial value "1” and outputs it as the value of the upper bits of the sel control signal. After the initial value “1” is loaded, when the update signal becomes enabled, the value “0” obtained by subtracting “1” from the initial value “1” is output as the value of the upper bits of the sel control signal. .
  • determination circuit 516 determines whether the sel control signal “1” is output as the value of the lower bits, and “0” is output as the value of the lower bits of the sel control signal when the transfer burst length is “1”.
  • FIG. 18 is a circuit diagram of the sel2 control signal generation circuit 403.
  • the sel2 control signal generation circuit 403 includes a flip-flop 521 that holds the value of the output selection register OUTSEL-l to n specified by the channel selection signal and outputs it as a sel2 control signal.
  • Output selection register OUTSEL — l to n for example, which input of output selection register 87 in FIG. 9 is selected.
  • the selection signal that determines whether or not is stored.
  • FIG. 19 is a circuit diagram of the update signal generation circuit 406.
  • the update signal generation circuit 406 selects and outputs one of the repeat register RPT-l to n values specified by the channel selection signal and the value decremented by the subtractor 533, and the output of the selector 531 Repeat counter 532 that latches the signal, judgment circuit 534 that determines whether the output of repeat counter 532 is other than "0", and a signal that is the logical product of the output of judgment circuit 534 and the update_timing signal is output as the update signal It becomes power with AND gate AND2.
  • the selector 531 selects the value of the repeat register RPT-i (one of RPTl to n), and the signal obtained by inverting the start signal with the inverter INV3 is enabled.
  • the start signal is disabled, a value obtained by decrementing the value of the repeat counter 532 is selected and output to the repeat counter 532.
  • the repeat counter 532 loads the value of the repeat register RPT —i as an initial value when the start signal is enabled, and the subtracter 533 when the update signal power is enabled.
  • the decremented value is latched and output. For example, when the value of the repeat register RPT-i is “1”, “1” is loaded into the repeat counter 532 when the start signal is enabled.
  • the determination circuit 534 outputs a high level signal because the value of the repeat counter 532 is not “0”. At this time, when the update timing signal is enabled, the update signal output from the AND gate AND2 is enabled.
  • FIG. 20 is a circuit diagram of the update timing signal generation circuit 407.
  • the update timing signal generation circuit 407 includes a selector 541 that selects and outputs one of the values of the update registers UPDATE—l to n and the output of the subtractor 543, and an update counter 542 that latches the output of the selector 541. And a determination circuit 544 for determining whether or not the output force of the updater counter 542 is not “0”.
  • the judgment circuit 544 outputs a high level signal to the OR gate OR4 when the value of the update counter 542 is not “0”, and outputs a low level signal to the OR gate OR4 when the value of the update counter 542 is “0”.
  • the update timing signal generation circuit 407 includes a flip-flop 545 that latches the output of the update counter 542, a determination circuit 546 that determines whether or not the output of the update counter 542 is “0”, and a flip-flop 545. Judgment circuit that determines whether or not the output of "1" is 547, and an AND gate AND3 that calculates the logical product of the outputs of the determination circuit 546 and the determination circuit 547 and outputs the result as an update timing signal.
  • the enable terminal of the update counter 542 receives a signal obtained by ORing the start signal and the update signal and the output of the determination circuit 544 via the OR gate OR4. Therefore, the update counter 542 reads the value of the update register UPDATE-i (one of UPDATE-1 to n) as the initial value when the start signal or update signal is enabled. Since the determination circuit 544 outputs a high-level signal until the count value of the update counter 542 reaches “0”, the value of the update counter 542 is decremented every cycle, and the value of the update counter 542 becomes “ When it reaches 0, the update_timing signal output from the AND gate AN D3 is enabled.
  • the timing chart of FIG. 21 shows the operation timing when input data having a burst length of “4” and a processing latency of “4” is input to the reconfigurable circuit 81 shown in FIG.
  • the cycle of updating the addresses of the configuration information memories 84 and 85 is the value of the update register UPDATE—i that holds the update cycle. Becomes “4 + 2 ⁇ 2” and becomes “4”. Since the processing latency is “4”, the value of the transfer burst length register BST-i is “3”.
  • the update counter 542 of the update timing signal generation circuit 407 shown in FIG. 20 loads “4” as an initial value from the update register UPDATE—i when the star t signal is enabled, and the loaded value Decrement every cycle until becomes "0".
  • the update timing signal generation circuit 407 will be described with reference to the timing chart of FIG. 21.
  • the start signal When the start signal is enabled, the initial value “4” is latched in the update counter 542. The value is decremented every cycle, and the count value becomes “0” in the fifth cycle.
  • the output of the judgment circuit 546 becomes “No” or “I” level.
  • the output of the determination circuit 547 becomes high level. Therefore, when the value of the update counter 542 becomes “0”, the update timing signal output from the AND gate AND3 becomes high level (enabled).
  • the repeat counter 532 of the update signal generation circuit 406 shown in Fig. 19 loads "1" as the initial value of the repeat register RPT— specified by the channel selection signal when the start signal is enabled. To do. If the determination circuit 534 determines that the value of the repeat counter 532 is not “0”, it outputs a high-level signal. At this time, when the update_timing signal becomes high (enabled), the AND gate AND2 outputs a high level (enable). Enable) update signal is output. As a result, as shown in FIG. 21, the update timing signal and the update signal are enabled in the fifth cycle.
  • the enable terminal of repeat counter 532 is enabled, the value of repeat counter 532 is decremented at the timing synchronized with the cycle, and the value of repeat counter 532 is set to "0". Change.
  • the value of the repeat counter 532 becomes “0”, the output of the determination circuit 534 becomes low level, and thereafter, the update signal remains disabled even if the update_timing signal is enabled.
  • the initial value “1” is latched in the flip-flop (sel flag) 512, and the value of the sel flag is “1”. It becomes.
  • the update_timing signal becomes enabled in the fifth cycle, the value of the sel flag is decremented and the value of the sel flag becomes “0” (see FIG. 21).
  • the value of the transfer burst length register BST-i is “3” and the output of the determination circuit 516 is “1”
  • the value of the lower bit of the sel control signal is “1”.
  • the upper bit of the sel control signal is “1” and the lower bit is “1” for the first five cycles.
  • the update_timing signal and update signal are enabled, the upper bit of the sel control signal is “0” and the lower bit is “1” for the last five cycles.
  • the input selection circuit 86 in FIG. 9 selects the input data 1 to 4 and outputs them to the reconfigurable combinational circuit 82 in stage 1 in the first five cycles. Also, the second 5 cycles The data selects the data 1 to 4 being processed stored in the intermediate buffer 88 and outputs the selected data to the reconfigurable combinational circuit 82 in stage 1.
  • FIG. 22 is a block diagram of the image processing LSI 601.
  • the image processing LSI 601 includes a preprocessing circuit 602 for preprocessing an input signal from a CCD (Charge Coupled Device), an image quality processing circuit 603 for performing image quality improvement processing, a resolution conversion circuit 604 for converting resolution, A color space conversion circuit 605 for converting the color space is required, and these circuits need to be provided inside the LSI.
  • CCD Charge Coupled Device
  • an image quality processing circuit 603 for performing image quality improvement processing
  • a resolution conversion circuit 604 for converting resolution
  • a color space conversion circuit 605 for converting the color space is required, and these circuits need to be provided inside the LSI.
  • various hardware circuits can be realized by the reconfigurable circuit 703 provided in the DMA controller 702 of the LSI 701 for image processing, so that the circuit area is reduced. can do.
  • the present invention is not limited to the embodiment described above, and may be configured as follows, for example.
  • the configuration of the reconfigurable circuit provided in the DMA controller is not limited to the number of stages shown in the embodiment. It can be arbitrarily determined according to the number of processing cycles required.
  • control circuit 43 such as the sel control signal generation circuit 402, the update-timing signal generation circuit 407, etc. is not limited to that shown in the embodiment, and other configurations may be used.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

L'efficacité du transfert de données d'un contrôleur DMA monté sur un circuit intégré semi-conducteur est améliorée. Un circuit reconfigurable (51), fourni à l'intérieur du contrôleur DMA, comprend un circuit combinatoire reconfigurable (52) et une mémoire de configuration (53) pour mémoriser les informations de configuration sur le circuit. Un signal de commande CM pour spécifier les informations de configuration est fourni à la mémoire de configuration (53) à partir d'un circuit de commande. Le contrôleur DMA traite les données d'entrée transmises à partir d'un processeur à l'aide du circuit combinatoire reconfigurable (52) à l'intérieur du contrôleur DMA et transmet les données concernant le résultat du traitement au processeur.
PCT/JP2006/317191 2006-08-31 2006-08-31 Contrôleur dma WO2008026273A1 (fr)

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
US9323700B2 (en) 2012-03-27 2016-04-26 Socionext Inc. Semiconductor integrated circuit and DMA control method of the same
JP2019159437A (ja) * 2018-03-08 2019-09-19 富士通株式会社 情報処理装置、転送制御方法および転送制御プログラム

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JPH01201760A (ja) * 1988-02-08 1989-08-14 Fujitsu Ltd Ｄｍａ制御装置
JPH04369245A (ja) * 1991-06-18 1992-12-22 Kawasaki Steel Corp プログラマブルロジックデバイス
JP2005011287A (ja) * 2003-06-23 2005-01-13 Konica Minolta Holdings Inc コンピュータシステム及びデータ転送方法

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JP3365581B2 (ja) * 1994-07-29 2003-01-14 富士通株式会社 自己修復機能付き情報処理装置
JPH10334038A (ja) * 1997-05-30 1998-12-18 Nec Corp データ転送装置
JPH11307725A (ja) * 1998-04-21 1999-11-05 Mitsubishi Electric Corp 半導体集積回路
JP3587095B2 (ja) * 1999-08-25 2004-11-10 富士ゼロックス株式会社 情報処理装置

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Publication number Priority date Publication date Assignee Title
JPH01201760A (ja) * 1988-02-08 1989-08-14 Fujitsu Ltd Ｄｍａ制御装置
JPH04369245A (ja) * 1991-06-18 1992-12-22 Kawasaki Steel Corp プログラマブルロジックデバイス
JP2005011287A (ja) * 2003-06-23 2005-01-13 Konica Minolta Holdings Inc コンピュータシステム及びデータ転送方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9323700B2 (en) 2012-03-27 2016-04-26 Socionext Inc. Semiconductor integrated circuit and DMA control method of the same
JP2019159437A (ja) * 2018-03-08 2019-09-19 富士通株式会社 情報処理装置、転送制御方法および転送制御プログラム

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