Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
  • H04L25/03006—Arrangements for removing intersymbol interference
  • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
  • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
  • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B7/00—Radio transmission systems, i.e. using radiation field
  • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
  • H04B7/10—Polarisation diversity; Directional diversity

Definitions

• the present invention relates generally to modems for wireless communications, and particularly to methods and systems for controlling the modem using cross-channel interference level estimation.
• Polarization diversity can be used in communication systems for providing two parallel communication channels having orthogonal polarizations over the same link, thus doubling the link capacity. Separate and independent signals are transmitted using the two orthogonal polarizations. Despite the orthogonality of the channels, however, some interference between the signals occurs almost inevitably.
• the receiver may comprise a cross-polarization interference canceller (XPIC), which processes and combines the two signals in order to recover the original, independent signals.
• XPIC cross-polarization interference canceller
• XPIC circuits are known in the art. XPIC circuits are described, for example, in U.S. Patents 4,914,676, 5,920,595, 5,710,799, in European Patent Application EP 1365519 Al, and in PCT Patent Application WO 00/77952 Al, whose disclosures are all incorporated herein by reference.
• the interference cancellation process varies the phase of the interference signal.
• U.S. Patent 6,236,263 whose disclosure is incorporated herein by reference, describes a demodulator with a cross-polarization interference canceling function for canceling interference of cross polarization in the main polarization.
• the demodulator includes a demodulating unit for demodulating a baseband signal of the main polarization and a phase control unit which controls the phase of an interference signal of cross polarization, based upon an error in the demodulated signal.
• An interference cancellation unit cancels an interference signal component from the demodulated signal of the main polarization.
• a phase rotator such as a mixer or multiplier controlled by a phase-locked loop (PLL), that adjusts the phase and frequency offset of the interference correction signal with respect to the desired signal being corrected.
• PLL phase-locked loop
• Embodiments of the present invention provide methods and devices for controlling the phase and/or frequency of this phase rotator, referred to herein as a "slave PLL.”
• a control module in the XPIC circuit estimates signal characteristics, such as a cross-polarization interference ratio (XPD) of the received symbols.
• the control module sets parameters of the slave PLL, such as its loop bandwidth and gain, responsively to the estimated signal characteristics. For this purpose, in some embodiments, the control module evaluates a metric function that depends on the estimated XPD values.
• XPD cross-polarization interference ratio
• Another disclosed method addresses the problem of unlocked slave PLL under conditions of high XPD (low interference level).
• the control module in the XPIC circuit detects situations in which the XPD falls below a predetermined threshold, searches for an appropriate frequency setting of the slave PLL, and loads the PLL with the appropriate frequency setting. This method ensures that the slave PLL locks on a correct frequency in cases in which the XPD deteriorates from high values to lower values, thus avoiding undesired transient events when the XPD value deteriorates.
• a method for estimating the XPD value based on equalizer coefficient values in the XPIC circuit is also described.
• the estimation method is used in conjunction with the PLL parameter setting method and/or the PLL locking method described herein.
• the disclosed methods and systems can also be used for canceling interference types other than cross-polarization interference.
• a receiver including: an input circuit, which is coupled to at least one antenna so as to receive, process and digitize first and second signals, thus generating first and second streams of input samples; and an interference cancellation circuit, including: first and second adaptive filters, which are respectively coupled to filter the first and second streams of input samples using respective first and second .coefficients to generate respective first and second filter outputs; a phase rotator, which is adapted to apply a variable phase shift compensating for a phase deviation between the first and second signals, the phase rotator having at least one configuration parameter; and a control module, which is operative to estimate signal characteristics of the interference cancellation circuit, and to set the at least one configuration parameter of the phase rotator responsively to the estimated signal characteristics.
• the first signal contains interference due to the second signal
• the interference cancellation circuit is operative to produce responsively to the first and second streams of input samples a third stream of output samples representative of the first signal and having a reduced level of the interference
• control module is operative to identify an increase of a level of the interference and to set the at least one configuration parameter responsively to the identified increase.
• the phase rotator includes a phase-locked loop (PLL)
• the at least one configuration parameter includes a frequency setting of the PLL
• the control module is operative, subsequent to identifying the increase of the level of the interference, to search over a predefined range of frequency settings for a best frequency setting determined responsively to the estimated signal characteristics, and to load the best frequency setting to the PLL.
• PLL phase-locked loop
• the first and second signals are transmitted with respective first and second, mutually orthogonal polarizations, and the interference cancellation circuit is operative to reduce cross-polarization interference coupled from the second signal to the first signal.
• the phase rotator includes a phase-locked loop (PLL) and the at least one configuration parameter includes at least one of a loop bandwidth and a loop gain of the PLL.
• the control module is operative to calculate the variable phase shift using at least one of a pilot-based and a batch-based phase estimation method.
• the signal characteristics include a level of a cross-coupling between the first and second signals.
• the first and second coefficients are determined adaptively in response to conditions on a communication channel over which the first and second signals are received, and the control module is operative to estimate the level of the cross-coupling by performing a calculation based on at least some of .the first and second coefficients. .
• control module is operative to store two or more predefined control sets of the at least one configuration parameter, to evaluate a metric function responsively to the estimated signal characteristics, to choose a selected control set out of the two or more predefined control sets responsively to the evaluated metric function, and to load the chosen control set into the phase rotator. Additionally or alternatively, the control module is operative to adaptively calculate the at least one configuration parameter responsively to the estimated signal characteristics.
• the second signal contains interference due to the first signal, and the interference cancellation circuit is further operative to produce responsively to the first and second streams of input samples a fourth stream of output samples representative of the second signal and having a reduced level of the interference.
• a wireless communication system including: a transmitter, which is operative to transmit first and second signals over the air; and a receiver, which includes: an input circuit, which is coupled to at least one antenna so as to receive, process and digitize the first and second signals, thus generating first and second streams of input samples; and an interference cancellation circuit, including: first and second adaptive filters, which are respectively coupled to filter the first and second streams of input samples using respective first and second coefficients to generate respective first and second filter outputs; a phase rotator, which is adapted to apply a variable phase shift compensating for a phase deviation between the first and second signals, the phase rotator having at least one configuration parameter; and a control module, which is operative to estimate signal characteristics of the interference cancellation circuit, and to set the at least one configuration parameter of the phase rotator responsively to the estimated signal characteristics.
• an interference cancellation circuit for processing first and second streams of input samples representing respective first and second signals
• the circuit including: first and second adaptive filters, which are respectively coupled to filter the first and second streams of input samples using respective first and second coefficients to generate respective first and second filter outputs; a phase rotator, which is adapted to apply a variable phase shift .compensating for. a phase deviation between the first and second signals, the phase rotator having at least one configuration parameter; and a control module, which is operative to estimate signal characteristics of the interference cancellation circuit, and to set the at least one configuration parameter of the phase rotator responsively to the estimated signal characteristics.
• a method for wireless communications including: receiving, processing and digitizing first and second signals transmitted over the air so as to generate first and second streams of input samples; filtering the first and second streams of input samples using respective first and second coefficients to generate respective first and second filtered outputs; applying a variable phase shift to one of the first and second filtered outputs using a phase rotator having at least one configuration parameter so as to generate a phase-shifted output compensating for a phase deviation between the first and second signals; summing the first and second filtered outputs so as to generate a third stream of output samples, which is representative of the first signal; estimating signal characteristics of the interference cancellation circuit; and setting the at least one configuration parameter of the phase rotator responsively to the estimated signal characteristics.
• a method for estimating an interference level including: receiving, processing and digitizing first and second signals so as to generate first and second streams of input samples; filtering the first and second streams of input samples using respective first and second coefficients to generate respective first and second filtered outputs; estimating a level of interference contained in the first signal due to the second signal based on the first and second coefficients.
• filtering the first and second streams of input samples includes filtering the samples using respective first and second adaptive equalizers.
• Fig. 1 is a schematic side view of a system for wireless data transmission over orthogonally-polarized channels, in accordance with an embodiment of the present invention
• Fig. 2 is a block diagram that schematically illustrates a receiver used in the system of Fig. 1, in accordance with an embodiment of the present invention
• Fig. 3 is a block diagram that schematically illustrates details of a communication channel and of a cross-polarization interference canceller (XPIC) 5 in accordance with an embodiment of the present invention
• XPIC cross-polarization interference canceller
• Fig. 4A is a diagram that schematically illustrates a metric function for setting operational modes of a phase-locked loop (PLL) circuit, in accordance with an embodiment of the present invention
• Fig. 4B is a state diagram that schematically illustrates transitions between operational modes of a PLL circuit, in accordance with an embodiment of the present invention.
• Fig. 5 is a flow chart that schematically illustrates a method for controlling a PLL circuit, in accordance with an embodiment of the present invention.
• Fig. 1 is a block diagram that schematically illustrates a wireless data transmission system 20, in accordance with an embodiment of the present invention.
• System 20 comprises a transmitter 22 that transmits two signals simultaneously via a transmit antenna 24 using polarization diversity.
• Transmitter 22 and antenna 24 are coupled to transmit the two signals as orthogonally-polarized electromagnetic waves.
• symbols denoted H are transmitted using horizontal polarization
• symbols denoted V are transmitted using vertical polarization.
• the signals may be transmitted using clockwise and counterclockwise circular polarizations, +45° and -45° polarizations, or any other suitable orthogonal polarization configuration known in the art.
• separate transmit antennas and/or separate receive antennas may be used for the two polarizations.
• H and V represent symbols, which are modulated in accordance with a suitable modulation scheme and upconverted to a predetermined radio frequency (RF) range for transmission, as is known in the art.
• the signals pass through a wireless communication channel 26, which is defined and modeled below.
• the signals are received by a receive antenna 28.
• the signals received by antenna 28 are downconverted and processed by a receiver 32, in order to recover the transmitted symbols (and later on the digital data), represented as H, V at the receiver output.
• Fig. 2 is a block diagram showing elements of receiver 32, in accordance with an embodiment of the present invention.
• the signals received by antenna 28 are separated into two orthogonal polarization components by an orthogonal mode transducer (OMT) 38.
• system 20 may comprise two separate receive antennas 28, one antenna for receiving each orthogonal component.
• the two orthogonal components are input to respective RF receiver circuits 40 and 41, which perform analog processing and downconvert the signal to a suitable baseband or intermediate frequency (IF).
• IF intermediate frequency
• Downconversion of the received signals is performed by mixing the signals received by receiver circuits 40 and 41 with respective local oscillators (LOs) 42 and 43.
• receiver circuits 40 and 41 can use a single common local oscillator.
• the downconverted signals are digitized by respective analog-to-digital converters (ADCs) 44 and 45.
• ADCs analog-to-digital converters
• FE modem front end
• the detailed functionality of front end 47 is not essential to the explanation of the present invention and may vary from one embodiment to another.
• front end 47 comprises circuitry that performs functions such as automatic gain control (AGC), sampling rate conversion and timing recovery.
• AGC automatic gain control
• the modem front end generates two streams of digital input samples denoted Xfj and xy, representing the received signals.
• a cross-polarization interference canceller (XPIC) 46 filters and combines the sample streams XH and xy in order to generate streams of corrected output samples.
• Respective decoders 48 and 49 such as slicers, process each of the streams of output samples in order to generate respective sequences of symbol estimates denoted H, V . These symbols are then demodulated to recover estimates of the transmitted data .
• Fig. 3 is a block diagram that schematically illustrates details of communication channel 26 and of cross-polarization interference canceller (XPIC) 46, in accordance with an embodiment of the present invention.
• Communication channel 26 between transmit antenna 24 and receive antenna 28 is modeled as having a horizontal polarization channel and a vertical polarization channel, respectively defining the transfer characteristics of the signals as they pass through channel 26.
• Communication channel 26 is subject to fading and additive noise within each polarization component, as well as to coupling, or cross-polarization interference, between the polarization components (In the description that follows, elements of system 20 not essential to the explanation were omitted for the sake of clarity. For example, RF receiver circuits 40 and 41, ADCs 44 and 45 and front end 47 are not shown in Fig. 3).
• Channel 26 is modeled using four channel transfer functions 60 denoted Hi,...,H4, wherein Hi defines the transfer function of the horizontal polarization component and H4 defines the transfer function of the vertical polarization component.
• Hi defines the transfer function of the horizontal polarization component
• H4 defines the transfer function of the vertical polarization component.
• Transfer function H2 defines the cross-coupling of the horizontal signal into the vertical component
• transfer function H3 defines the coupling of the vertical signal into the horizontal component.
• thermal noise is also added to the two polarization components, as part of communication channel 26.
• the communication channel described by functions Hi,...,H4 may comprise a time- varying, frequency-selective dispersive channel.
• Functions H2 and H3 define the cross-polarization interference between the horizontal and vertical channels.
• Receiver 32 and in particular XPIC 46, adaptively cancels this interference.
• a cross-polarization interference ratio denoted XPD, is defined as
• XPD 10 log [P de s / Pi n tL wherein P des denotes the average power of the desired component and P j _ nt denotes the average power of the interference component in each receiver channel.
• XPD is usually represented on a logarithmic scale. For example, high XPD values, on the order of 35 dB, correspond to low interference levels that usually have a negligible effect on the receiver performance. XPD values smaller than about 10 dB often cause significant degradation in the receiver performance. In some cases, XPD takes different values in the horizontal and vertical channels. In other words, the cross-polarization interference from the vertical channel to the horizontal channel may be different (either higher or lower) from the interference from the horizontal channel to the vertical channel.
• XPIC 46 comprises two digital processing channels (referred to herein as the horizontal and vertical processing channels) for processing the two polarization components.
• Fig. 3 shows only the horizontal channel that decodes symbols H.
• Each digital processing channel comprises two pipelines, each comprising a feed-forward equalizer (FFE).
• the horizontal processing channel shown in Fig. 3 comprises a main pipeline, which processes the Xfj sample stream, and an auxiliary pipeline, which processes the xy sample stream.
• the vertical processing channel uses XH and xy to decode symbol V using a similar configuration.
• XPIC 46 filters sample streams XH and xy using respective filters, such as FFEs 64 and 66, denoted FFEl and
• the equalizers are implemented using multi-tap, time-domain finite impulse response (FIR) digital filters, as are known in the art.
• the filters can be implemented using any other suitable digital filtering method, such as infinite impulse response (IIR) and frequency-domain filtering methods.
• FFEl and FFE2 each comprise multiple coefficients that define the transfer function of the equalizer.
• a control module 67 adaptively modifies the coefficients of FFEl and FFE2, thereby modifying the transfer functions of the two equalizers. In general, module 67 determines the optimum coefficient values that compensate for the interference from the vertical polarization component to the horizontal polarization component (modeled by function H3 in channel 26).
• Control module 67 adjusts the phase of the output of the auxiliary pipeline by controlling a phase rotator provided at the output of FFE2.
• the phase rotator comprises a phase-locked loop (PLL) 68, referred to as a "slave PLL.”
• PLL phase-locked loop
• the output of slave PLL 68 is mixed with the output of FFE2 using a mixer 71, so as to rotate the phase of the auxiliary pipeline.
• the phase-adjusted signal is combined with the output of the main pipeline using an adder 69.
• control module 67 calculates the desired phase rotation and controls the phase rotator (comprising mixer 71) so as to apply the rotation to the output of the auxiliary pipeline.
• the phase rotation introduced by slave PLL 68 ensures that the outputs of the main and auxiliary pipelines are combined with the appropriate phase offset, so as to minimize the residual cross-polarization interference in the horizontal channel.
• This phase offset may change, for example, because of phase noise or because of changes in the wave propagation characteristics of communication channel 26.
• the phase rotation introduced by slave PLL 68 is also used to compensate for frequency offsets between the two LOs.
• the combined output signal is phase-rotated by another phase rotator, referred to as a master PLL 70, and a mixer 73.
• the phase-rotated combined output signal is provided to decoder 48 that determines estimates H of the transmitted symbols.
• master PLL 70 and mixer 73 are located before adder 69. In these embodiments, the output of the main pipeline is first phase-rotated by master PLL 70, and then combined with the output of the auxiliary pipeline adder 69.
• XPIC 46 including equalizers 64 and 66 and PLLs 68 and 70, are typically implemented as digital hardware circuits in an integrated circuit, such as an application-specific integrated circuit (ASIC).
• ASIC application-specific integrated circuit
• the phase adjustment operations shown as multiplications in Fig. 3, are implemented as digital arithmetic operations on the relevant sample streams.
• Control module 67 can be implemented in hardware, in software running on a suitable microprocessor, or as a combination of hardware and software functions.
• Fig. 3 shows only one digital processing channel that decodes the horizontal polarization signal with reduced cross-polarization interference.
• XPIC 46 comprises an additional vertical processing channel, similar in structure to the configuration shown in Fig. 3, which similarly receives sample streams xj-[ and xy and decodes the vertical polarization signal.
• an equalizer denoted FFE4 is analogous with FFEl
• an equalizer denoted FFE3 is analogous with FFE2.
• a single control module 67 controls all four pipelines.
• FFEl and FFE2 are controlled by one control module 67, while another such module controls FFE3 and FFE4.
• PLLs as are known in the art, comprise a closed control loop, whose gain and bandwidth settings determine the performance of the PLL. For example, a wide bandwidth enables rapid phase changes and faster stabilization time, but sometimes produces a higher level of residual phase noise. A narrow bandwidth, on the other hand, often provides smoother but slower dynamic performance.
• PLL loop setting that maximizes the MTLL.
• PLL design is described, for example, by Best in "Phase Locked Loops: Design, Simulation, And
• module 67 sets configuration parameters of slave PLL 68, such as its loop bandwidth and loop gain, so as to improve the performance of receiver 32.
• module 67 determines the desired PLL parameter values of slave PLL 68 responsively to an estimated value of the cross-polarization interference level, or XPD, as will be described in detail below.
• control module 67 estimates the current XPD value based on the known coefficient values of equalizers
• XPD ESTIMATION METHOD Following the notation of Fig. 3, XPD can be written as:
• signal y is the desired horizontal polarization signal, produced by a convolution of symbols H with the (time domain) channel transfer function HJ .
• Signal z is the interference component of symbols V that are coupled into the horizontal channel. Therefore, z is produced by convolving symbols V with channel transfer function H3.
• Ryy[0] denotes the autocorrelation function of signal y, evaluated at offset 0, which is equal to the average power of signal y.
• R zz [0] is equal to the average power of the interference signal z.
• Hj and H3 are represented as two FIR filters having coefficients H ⁇ [m] and H3[m], respectively.
• XH and Xy are the frequency-domain representations of sample streams Xy and xpj at the input to XPIC 46, respectively.
• H and V are the frequency-domain representations of symbols H and V, respectively.
• H 1 , ... , H4 denote the frequency-domain representations of channel transfer functions H j5 ...JH4, respectively.
• receiver 32 reconstructs signal H with perfect cancellation of the cross-polarization interference.
• a similar derivation provides:
• Equations [12]-[15] (zero forcing solution) can be solved together to provide H 1 , H 2 , H 3 and H 4 as a function of FFEl, FFE2, FFE3 and FFE4.
• T FFEl • FFE4 - FFE2 • FFE3 which gives:
• simplifying assumptions can be used to further simplify the estimation process.
• equations [12]-[15] can be reduced to two equations that only use FFEl and FFE2 .
• the zero forcing assumption may be relaxed.
• equations [12]-[15] are not valid and should include the effect of the thermal noise.
• slave PLL 68 it is desirable to adjust parameters of slave PLL 68 in accordance with signal characteristics of the XPIC circuit, such as the current XPD value.
• signal characteristics of the XPIC circuit such as the current XPD value.
• optimization of slave PLL parameters improves the mean square error (MSE) and/or the bit error rate (BER) at decoder 48.
• MSE mean square error
• BER bit error rate
• Optimization of PLL parameters based on XPD also increases the "mean time to lose lock" (MTLL) of the PLL.
• receiver 32 operates in the presence of two types of noise: thermal white noise and phase noise.
• thermal white noise When the thermal noise is dominant, it is usually desirable to average over a relatively long time interval. Averaging of this sort corresponds to having a narrow loop bandwidth.
• phase noise When the phase noise is dominant, on the other hand, it is often desirable to try and track the phase error. Tracking of this sort corresponds to having a wide loop bandwidth.
• control module 67 loads slave PLL 68 with one of several predetermined sets of configuration parameters (sometimes referred to as control sets) responsively to estimated XPD.
• three parameter sets denoted PLLJL, PLLJVI and PLL_H.
• PLLJL three parameter sets, denoted PLLJL, PLLJVI and PLL_H.
• PLLJL three parameter sets, denoted PLLJL, PLLJVI and PLL_H, are defined.
• PLLJL three parameter sets, denoted PLLJL, PLLJVI and PLL_H, are defined.
• PLLJL When loaded with the PLLJL parameter set, slave PLL 68 operates with relatively low loop gain.
• the PLLJH set comprises relatively high loop gain and the PLLJVI set comprises an intermediate value.
• control module 67 estimates the current value of XPD based on the FFE1,...,FFE4 equalizer coefficients, using the estimation method described above. The estimated XPD value is then used to determine which
• Fig. 4A is a diagram that schematically illustrates an exemplary metric function denoted f(XPD) for setting operational modes of slave PLL 68, in accordance with an embodiment of the present invention.
• f(XPD) the range of values taken by f(XPD), shown by the horizontal axis of the figure, is divided into three regions, wherein each region corresponds to one of the three predefined parameter sets.
• Control module 67 compares f(XPD) to two thresholds denoted TH_L and THJH, in order to determine the appropriate parameter set to be loaded to slave PLL 68.
• a hyteresis interval denoted ⁇ is used near each of the thresholds, to avoid excessive parameter switching when the value of f(XPD) is close to one of the thresholds.
• any other suitable arrangement of thresholds and parameter values can be used.
• Fig. 4B is a state diagram that schematically illustrates transitions between the operational modes of slave PLL 68, in accordance with an embodiment of the present invention.
• the operation of slave PLL 68 is described in terms of three states 80, 82 and 84.
• the three states correspond with the parameter sets PLL_L, PLL_M and PLLJH, respectively.
• State transitions are represented by arrows, with the corresponding condition for transition attached to each arrow. For example, when the slave PLL is in PLL_L state 80 (i.e., loaded with the PLLJL parameter set), control module 67 periodically evaluates f(XPD).
• module 67 loads slave PLL 68 with the PLLJH parameter set, thereby moving to PLL_H state 84. If, on the other hand, THJL+ ⁇ f(XPD) ⁇ TH_H, module 67 loads slave PLL 68 with the PLL_M parameter set, moving to PLL_M state 82. Otherwise, the PLL remains in PLLJL state 80.
• the state diagram also demonstrates the use of hysteresis interval ⁇ . For example, consider a scenario in which the value of f(XPD) is close to THJL. In order to move from PLL_L state 80 to PLL JM state 82, f(XPD) has to be larger than THJL+ ⁇ .
• f(XPD) has to be smaller than THJL.
• Fig. 4B shows the states and state transitions when receiver 32 is in steady-state operation, after all acquisition processes between transmitter 22 and receiver 32 have ended. In some embodiments, after the receiver initially acquires the transmitter signals, control module
• module 67 evaluates the current XPD value. Based on this estimate, module 67 determines whether to begin steady-state operation from state PLL_L, PLLJVi or PLL_H.
• Figs. 4A and 4B described three sets of configuration parameters and two thresholds.
• any number of slave PLL states, parameters and/or parameter sets can be defined. Any other suitable mechanism can be used to determine the desired slave PLL configuration parameters based on estimated XPD values.
• module 67 may also adaptively calculate the values of the configuration parameters based on the estimated XPD value, without using predetermined parameter sets.
• Fig. 5 is a flow chart that schematically illustrates a method for controlling slave PLL 68, in accordance with an embodiment of the present invention.
• the phase rotation introduced by slave PLL 68 may depend on the phase noise, on the wave propagation characteristics of channel 26, as well as on the frequency offset between the local oscillators of receiver circuits 40 and 41.
• the level of cross-polarization interference i.e., XPD is high
• the effect of the cross-polarization correction signal i.e., the output of FFE2
• slave PLL 68 may not be locked, however this has no effect on the performance of receiver 32.
• Control module 67 defines a flag denoted XPDFLAG and sets it to zero, at an initialization step 90.
• Module 61 estimates the value of XPD, at an XPD estimation step 92. In some embodiments, control module 67 estimates XPD based on the FFE1,...,FFE4 equalizer coefficients, using the estimation method described above. Alternatively, any other suitable method for estimating XPD can also be used. Module 67 compares the estimated XPD value to a predetermined XPD threshold, at a threshold checking step 94.
• the threshold is chosen to be an intermediate value, in which the effect of cross-polarization interference on the performance of decoder 48 is noticeable, but not yet harmful.
• Control module 67 initializes the slave PLL frequency, typically to a frequency at the center of the search range, at a search initialization step 98. Module 67 checks whether the entire range has been searched, at a completion checking step 100. If the search has not yet been completed, module 67 loads the slave PLL with the next frequency setting in the range, at a frequency setting step 102.
• the search range is covered in a back-and-forth manner.
• the search begins at the center of the search range.
• the control module loads frequency settings that gradually move away from the center of the search range of both sides of the center frequency.
• any other suitable search strategy can be used to apply frequency setting step 102.
• module 67 allows the newly-programmed slave PLL to stabilize after each frequency setting by waiting for a predetermined time duration, or by verifying that the PLL is locked. Once the PLL frequency stabilizes at the next frequency setting, module 67 queries the
• MSE value that corresponds to the current PLL frequency setting, at an MSE measurement step 104.
• the MSE is measured by decoder 48 and provided to module 67.
• Module 67 checks whether the current MSE value is the best (lowest) MSE value measured so far during the present search, at a best MSE updating step 106. If the current MSE is the best value so far, module 67 temporarily records this value together with the corresponding PLL frequency setting. The method then loops back to completion checking step 100 to continue searching over the predetermined search range.
• the main purpose of the XPDFLAG mechanism is to avoid updating the PLL frequency when not necessary. For example, if an update has been performed, and XPD is smaller than the XPD threshold, it is not necessary to perform an update. Under these conditions, it is assumed that the cross-polarization interference is strong enough to enable FFE2 to output a valid correction signal, implying that slave PLL 68 is locked on a correct frequency. In this case, the method loops in steps 92-96 until the estimated XPD crosses the threshold.
• the principles of the present invention may more generally be applied to reducing interference in signals received by multi-channel wireless receivers of other types.
• a system could use one antenna to collect a desired signal, which is perturbed by an interfering signal.
• a second antenna could be used to collect the interfering signal. Feeding the two signals into a digital processing channel will result in attenuation of the interfering signal content at the decoder.
• the receiver design described herein is also useful in improving the signal-to-noise ratio of a communication system by means of polarization diversity, even when the transmitter does not transmit signals at orthogonal polarizations.

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