Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/157—Impurity concentrations or distributions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide

Definitions

• the present invention relates to a field effect transistor (hereinafter referred to as MOSFET) having a metal-oxide-silicon film gate, and more specifically, for high power use with improved on-resistance and breakdown voltage.
• MOSFET field effect transistor
• the present invention relates to a MOSFET and its manufacturing method.
• SiC silicon carbide
• Si has a dielectric breakdown electric field strength approximately 10 times that of silicon (hereinafter referred to as Si), so it has low on-state. Resistive is possible, and it has a wide bandwidth of 3 eV or more, so it can operate at high temperatures.
• metal-acid-semiconductor MOSFETs using SiC are promising as next-generation high-voltage, low-loss switching devices.
• MOS structure is a well-known structure in Si.
• SiC when a thermal oxide film is used as an oxide, the level density of the oxide semiconductor interface is large! There was a problem of a decrease. Therefore, in Patent Document 1, a drift layer is formed on a SiC substrate, a p-type base region and an n-type source region are formed by photolithography and ion implantation technology, and then an n-type layer is formed as a channel layer. Thereafter, a gate structure composed of a gate insulating film such as a thermal oxide film and a gate electrode is formed to manufacture a MOSFET. This makes it possible to reduce the influence of the oxide-semiconductor interface level on the channel layer carriers.
• the ion implantation mask has a two-layer structure, and by using the implantation spread at the time of ion implantation, instead of using two independent implantation masks, one implantation mask is used. The process can be controlled even if the channel length is as small as 1 ⁇ m or less.
• Patent Document 1 Japanese Patent Laid-Open No. 10-308510 (pages 5-6, FIG. 1)
• Patent Document 2 Japanese Patent Laid-Open No. 2000-150866 (pages 3 to 4, FIG. 1)
• Patent Document 3 Japanese Patent Application Laid-Open No. 2004-363515 (4 pages, Fig. 1)
• the p-type impurity concentration force source region under the p-type impurity concentration force source region in the p-type base region immediately below the channel layer In many cases, the value is smaller than the p-type impurity concentration. In such a case, when a high voltage is applied between the source and drain, the p-type region immediately below the channel layer is depleted, which may reduce the breakdown voltage. In particular, as in Patent Document 1, when the channel layer is an n-type layer, the p-type region immediately below the channel layer is depleted with the upper channel layer, which further deteriorates the characteristics. There was a problem.
• a semiconductor device includes a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on a main surface of the semiconductor substrate, and a predetermined portion of a surface layer portion of the drift layer.
• a second conductivity type base region having a predetermined depth, a first conductivity type source region formed at a predetermined location on a surface layer portion of the base region and shallower than the depth of the base region;
• a channel layer of a second conductivity type formed on the surface of the source region and the drift layer and connecting the source region and the drift layer; an insulating film formed on the surface of the channel layer;
• a gate electrode formed on the surface of the film, a source electrode formed on the surface of the base region and the source region, and a drain electrode formed on the lower surface of the semiconductor substrate.
• the channel layer and the base region immediately below the channel layer are configured with the same conductivity type, so that a depletion layer generated in the base region immediately below the channel layer is reduced and high. A breakdown voltage can be obtained.
• the elements can be formed in a self-aligned manner, the elements can be reduced in size, thereby increasing the number of elements that fall within a certain area and reducing on-resistance.
• FIG. 1 is a sectional view of a MOSFET according to a first embodiment of the present invention.
• FIG. 2 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 3 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 4 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 5 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 6 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 7 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 8 is a diagram showing a part of the MOSFET manufacturing method according to the first embodiment of the present invention.
• FIG. 9 is a sectional view of a MOSFET according to the first embodiment of the present invention.
• FIG. 10 is a diagram showing a part of the MOSFET manufacturing method according to the second embodiment of the present invention.
• FIG. 11 is a diagram showing a part of the MOSFET manufacturing method according to the second embodiment of the present invention.
• FIG. 12 shows a part of the method for manufacturing the MOSFET according to the second embodiment of the present invention.
• FIG. 13 shows a part of the method for manufacturing the MOSFET according to the second embodiment of the present invention.
• FIG. 14 shows a part of the method for manufacturing the MOSFET according to the second embodiment of the present invention.
• FIG. 15 is a diagram showing a part of the MOSFET manufacturing method according to the second embodiment of the present invention.
• FIG. 16 shows a part of the method for manufacturing the MOSFET according to the second embodiment of the present invention. Explanation of symbols
• FIG. 1 is a cross-sectional view of the MOSFET in the first embodiment.
• the actual MOSFET configuration is a configuration in which a plurality of structures folded symmetrically about the right side of the cross-sectional structure in Fig. 1 are arranged horizontally and the same type of electrodes are connected in parallel.
• n-type SiC substrate 1 which is the first conductivity type semiconductor substrate, is a first conductivity type drift layer for maintaining the withstand voltage when voltage is applied between the source and drain of the MOSFET.
• the n-type SiC drift layer 2 has been epitaxially grown.
• a p-type SiC base region 3 that is a second conductivity type base region having a predetermined depth is formed at a predetermined portion of the surface layer portion of the n-type SiC drift layer 2.
• n-type SiC source region 4 which is a source region of the first conductivity type shallower than the depth of the p-type SiC base region 3, is formed at a predetermined position on the surface layer portion of the p-type SiC base region 3. Has been.
• Part of the surface of the n-type SiC source region 4 is a p-type SiC that is a channel layer of the second conductivity type that connects the n-type SiC source region 4 and the n-type SiC drift layer 2.
• the channel layer 5 is formed by epitaxial growth.
• a silicon oxide film or a silicon oxynitride film is formed by thermal oxidation, nitridation, formation of an insulating film deposit, or a combination thereof, and the insulating film 6 is formed. Yes.
• a gate electrode 7 is formed on the insulating film 6, a source electrode 8 is formed on the other surface of the n-type SiC source region 4, and a back surface of the n-type SiC substrate 1 is
• the MOSFET 10 is formed by forming the drain electrode 9.
• the p-type SiC base region 3 is located under the source electrode 8 and has a high concentration at least on the surface.
• P-type SiC region 3b which is directly under the n-type SiC source region 4, and a p-type SiC region 3b in which the impurity concentration is lower than that of the p-type SiC region 3a. It consists of p-type SiC region 3c, which has a lower impurity concentration than p-type SiC region 3b.
• MOSFET 10 of the first embodiment when a positive voltage is applied to the gate electrode 7, the surface of the p-type SiC channel layer 5 is inverted to form a channel, where a current path is created.
• the n-type SiC source region 4 and the n-type SiC drift layer 2 become conductive, and the source electrode 8 and the drain electrode 9 Current flows between the two. Therefore, the switching operation of the MOSFET 10 can be performed by turning on and off the voltage of the gate electrode 7.
• MOSFET 10 of the first embodiment a method for manufacturing MOSFET 10 of the first embodiment will be described with reference to FIGS.
• n-type SiC substrate 1 by CVD growth, etc., for example, n-type by epitaxial growth with a doping concentration of 1 ⁇ 10 15 to 2xl0 16 Zcm 3 and a layer thickness of 4 to 15 ⁇ m.
• the SiC drift layer 2 is formed (Fig. 2).
• a doping concentration of 5xl0 17 to 2xl0 18 Zcm 3 0.7 to: p of the p-type SiC base region 3 with a layer thickness of about L m Form SiC regions 3b and 3c (Fig. 3).
• an n-type SiC source region 4 is formed so as to have a doping concentration of lxl0 19 to 3xl0 19 Zcm 3 and a layer thickness of about 0.2 to 0.4 m. (Fig. 4).
• a p-type SiC base region 3 is formed so as to have a doping concentration of 5xl0 18 to lxl0 2 ° Zcm 3 and a layer thickness of about 0.7 to 1 / ⁇ ⁇ .
• a P-type SiC region 3a that contacts the source electrode 8 is formed (Fig. 5).
• These p-type SiC base regions 3a, 3b, 3c, and n-type SiC source region 4 are formed by ion implantation and activation heat treatment.
• the p-type SiC regions 3b and 3c and the n-type SiC source region 4 may be formed using different implantation masks. However, a two-layer implantation mask or oblique ion implantation may be used. Can be formed in a self-aligned manner using a single mask or a configuration in which processing is integrated into a single mask. In particular, when the channel length A shown in FIG. 1 is about 1 m or less, it is more desirable to form these regions in a self-aligned manner because they can be formed with high accuracy. In this case, p-type SiC region 3c of p-type SiC base region 3 is p-type The SiC region 3b is formed to have a lower concentration, a lower concentration, or a lower layer thickness than the doping concentration.
• a p-type channel layer 5 is formed by epitaxial growth on this structure with a doping concentration of lxl0 15 to 5xl0 16 Zcm 3 and a layer thickness of about 0.1 to 1 ⁇ m. This surface is flattened to a roughness of less than 2 nm by being formed by epitaxial growth (Fig. 6).
• a gate insulating film 6 is formed on the p-type channel layer 5 by thermal oxidation, nitridation, deposition of an insulating film, or a combination thereof, such as a silicon oxide film or a silicon oxide nitride film.
• a gate electrode 7 is formed thereon (FIG. 7).
• the source electrode 8 is formed on the other surface of the n-type SiC source region 4 and the drain electrode 9 is formed on the back surface of the n-type SiC substrate 1, thereby completing the MOSFET 10 (FIG. 8).
• the p-type SiC base region 3 is not formed, and the n-type depletion region 11, which is a region, may be left as it is. Force The n-type depletion region 11 with an increased n-type doping concentration can be obtained by performing ion implantation separately.
• the distance between the end C of the insulating film 6 and the pn junction end B composed of the p-type SiC region 3c and the n-type SiC drift layer 2 is increased to From the viewpoint of lowering the electric field value at the edge C, it is possible to consider a configuration in which the depth of the p-type SiC base region 3 is increased by the thickness of the channel layer 5 of the first embodiment. Resistance component force in the depletion region 3 ⁇ 4-type SiC base region 3 increases in depth to increase device resistance, that is, steady loss. In addition, when the thickness of the p-type SiC base region 3 is deeper than 1 ⁇ m, a MeV-class acceleration voltage is required for ion implantation. This is preferable because the additional process for making it a self-aligned process becomes complicated!
• the concentration of the p-type region 3c immediately below the channel layer 5 is about 5 to 20% of the concentration of the p-type SiC region 3b, which is about lxl0 17 Zcm 3 or more. Then, even if a voltage is applied close to the ideal breakdown voltage (about 500-20 OOV) determined by the thickness and doping of the n-type SiC drift layer 2, a breakdown voltage close to the ideal breakdown voltage can be obtained without depletion. Can do.
• the channel layer 5 is different from that in the first embodiment.
• the concentration of the p-type SiC region 3c directly below the channel layer is about 15 to 50% of the concentration of the p-type SiC region 3b below the n-type SiC source region 4 3xl0 17 Zcm 3 Therefore, it is necessary to strictly control the mask shape and ion implantation angle range in the formation of the self-aligned p-type SiC base region 3 and n-type SiC source region 4. The cost will be high.
• the p-type channel layer 5 is epitaxially grown to flatten the semiconductor surface before forming the gate structure, so that the vicinity of the SiC surface is obtained.
• a MOS structure capable of forming a good inversion channel without lowering the electron mobility of the channel layer due to scattering caused by roughness of the channel can be obtained, and sufficiently low resistance channel characteristics can be obtained. Since the force is also an inversion channel, it is easy to obtain a zonal-off operation with no current flowing between the source and drain when the gate voltage is open.
• the electric field distribution in the element is the end B of the pn junction consisting of the p-type SiC base region 3 and the n-type SiC drift layer 2 and A high electric field is formed between the end C of the insulating film 6 and the insulating film 6.
• the electric field value at the edge C of the insulating film 6 is that when the channel layer 6 is n-type, compared to the normal inverted MOS configuration without the channel layer, the pn junction edge B to the edge of the insulating film 6 Since the distance of C increases, it is reduced to about 70%.
• the channel layer 5 and the p-type SiC base region immediately below it are configured to have the same conductivity type as in the first embodiment, the electric field value at the end C of the insulating film 6 is further reduced, and the channel layer Therefore, the reliability of the insulating film 6 can be further improved.
• the device size is miniaturized to increase the number of MOSFETs per unit area, but the n-type depletion region 11 The device resistance can be reduced, and the overall device resistance can be reduced.
• the process up to forming the n-type SiC drift layer 2 on the main surface of the n-type SiC substrate 1 by epitaxial growth is the same as in the first embodiment.
• the p-type SiC layer 20 is grown over the entire surface of the n-type SiC drift layer 2 at a doping concentration of about lxl0 17 Zcm 3 (FIG. 10).
• a p-type SiC base region has a doping concentration of 5xl0 17 to 2xl0 18 Zcm 3 and a layer thickness of about 0.7 to 1 ⁇ m at a predetermined portion of the surface layer portion of the p-type SiC layer 20.
• the p-type SiC region 21 b of 21 is formed.
• the p-type SiC region 21 c in the p-type base region 21 is still doped in the original p-type SiC layer 20 and thus has a lower concentration than the p-type SiC region 21b (FIG. 11).
• n-type SiC source region 23 is formed to a layer thickness of about 0 (Fig. 12).
• an n-type SiC depletion region 22 is formed so as to reach the drift layer 2 at a predetermined position on the surface layer portion of the p-type SiC layer 20 (FIG. 13).
• ion implantation and activation heat treatment are performed in a region adjacent to the n-type source region 23 to a doping concentration of 5xl0 18 to lxl02 2 Zcm 3 and a layer thickness of about 0.7 to 1 m, and p A P-type SiC region 21a in contact with the source electrode 8 is formed in the mold base region 21 (Fig. 14).
• the base regions 21a and 21b, the source region 23, and the n-type SiC depletion region 22 are formed by ion implantation and activation heat treatment.
• the p-type channel layer 5 is formed by epitaxial growth on this structure with a doping concentration of lxl0 15 to 5xl0 16 Zcm 3 and a layer thickness of about 0.1 to 1 ⁇ m. This surface is flattened to a roughness of less than 2 nm ( Figure 15).
• an insulating film 6 is formed on the p-type channel layer 5 by thermal oxidation, nitridation, formation of an insulating film deposit, or a combination thereof, such as a silicon oxide film or a silicon oxynitride film.
• a gate electrode 7 is formed thereon.
• the source electrode 8 is formed on the other surface of the n-type SiC source region 23, and the drain electrode 9 is formed on the back surface of the n-type SiC substrate 1, thereby completing the MOSFET 24 (FIG. 16).
• the process of (1) is self-aligned.
• the process of ion implantation is required for each of the contact region and (3) n-type SiC depletion region. If this was not the case, the mask formation step (1) had to be performed twice, and the number of photolithography processes for forming the implantation mask was 3 to 4 times.
• MOSFET 24 of Embodiment 2 it is not necessary to separate the p-type SiC base region and the n-type SiC source region in step (1).
• the number of times of forming photolithography is always 3, and the effect of not requiring a self-aligned process can be obtained.
• the MOSFET 24 manufactured by the manufacturing method described in the second embodiment can obtain the same characteristics as the MOSFET 10 described in the first embodiment.
• the MOSFET described in the first and second embodiments may have a configuration in which p-type SiC and n-type SiC are interchanged.
• the MOSFET described in Embodiments 1 and 2 has the same effect even when a GaN, ZnO, diamond, or the like, which is a wide band gap semiconductor material having a force band gap of about 2 eV or more, composed of a SiC semiconductor, is used. The performance of semiconductor devices can be improved.

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