Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
  • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
  • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/931—Silicon carbide semiconductor

Definitions

• the present invention relates to a method for manufacturing a semiconductor device.
• SiO 2 silicon oxide film
• the thickness of the silicon oxide film is 2 nm or less, the insulation performance will be reduced and the leakage current will increase. As the gate leakage current increases, the power consumption also increases significantly. For this reason, when such a gate insulating film is applied to a mopile product, the battery usable time of the mopile product is shortened.
• an impurity such as boron may be diffused into the gate insulating film as well as an impurity such as boron. This degrades the performance and reliability as a transistor.
• the high-k film functions as an etching stopper.
• a thin film of an anti-reflection film (ARC) used for etching and a photoresist film is used to make the gate electrode finer. ⁇ is progressing.
• ARC anti-reflection film
• a photoresist film is used to make the gate electrode finer. ⁇ .
• a method of introducing a hard mask under the photoresist film Z ARC is used. This improves the pattern transfer Z resolution during etching.
• the conventional method of introducing a hard mask under the ARC does not necessarily have sufficient antireflection function, so the resolution may not be sufficient for the lithography process.
• FIG. 9A to FIG. 9H are schematic views showing a part of steps in a conventional gate electrode formation process in which a hard mask is introduced under the photoresist film Z ARC.
• FIG. 9A shows the gate stack before etching.
• a high-k film such as HfO or HfSiO is used as a gate insulating film.
• a polysilicon film 203 is formed on the high-k film 202.
• a hard mask 204 and an ARC 205 that have strength such as, for example, an oxide layer or a nitride layer are formed.
• a patterned photoresist film 210 is formed on the ARC 205.
• the ARC film 205 and the hard mask film 204 are etched using the photoresist film 210 as a mask.
• the photoresist film 210 is removed.
• the polysilicon film 203 is etched using the ARC film 205 and the node mask film 204 as a mask. By this etching, as shown in FIG. 9D, the ARC film 205 is also removed (the thickness of the node mask film 204 is also reduced).
• a plasma treatment is performed on the high-k film 202 exposed by etching the polysilicon film 203.
• the high-k film 202 is modified into a porous material mainly by the action of ions contained in the plasma.
• the exposed portion of the high-k film 202 is peeled off and removed by wet cleaning (wet etching) using a chemical solution such as HF.
• a chemical solution such as HF.
• sidewalls 207 are formed in the gate stack.
• the remaining hard mask 204 is peeled off and removed by a combination of plasma modification treatment and wet cleaning. As a result, a gate structure as shown in FIG. 9H is obtained.
• the gate electrode is formed by a series of steps as described above.
• the removal of the high-k film 202 and the removal and force of the hard mask 204 are performed by independent processes. This means that plasma treatment and wet cleaning are repeated twice. For this reason, the number of processes is large, and the problems such as device deterioration due to plasma damage and side etching of the gate insulating film in the wet cleaning process and the reduction of the buried insulating film are not small.
• the present invention has been devised in order to effectively solve the above-mentioned problems.
• the object of the present invention is to efficiently and reliably remove a multilayered SiC film that has both an antireflection function and a hard mask function, simplify the film removal process in the gate electrode formation process, and adversely affect the device.
• the object is to provide a method of manufacturing a semiconductor device that can be reduced as much as possible.
• the present invention relates to a semiconductor substrate, a high dielectric film formed on the semiconductor substrate, and an SiC-based film having an antireflection function and a hard mask function formed above the high dielectric film.
• a method for manufacturing a semiconductor device having a stacked body strength comprising: a plasma processing step in which plasma is applied to the SiC-based film and the high dielectric film, and a modification in the plasma processing step. And a cleaning process for removing the SiC-based film and the high dielectric film collectively by wet cleaning.
• the present invention provides a semiconductor substrate, a high dielectric film formed on the semiconductor substrate, a polysilicon film formed on the high dielectric film, and an upper layer than the polysilicon film.
• a plasma processing step for modifying by applying plasma, and the SiC-based film and the high dielectric film modified in the plasma processing step by wet cleaning at a time Is a manufacturing method of a semiconductor device is characterized in that and a cleaning treatment step of removing Te.
• the combination of the plasma treatment step and the cleaning treatment step enables the SiC-based film to be removed efficiently and reliably, and the removal of the SiC-based film can be performed by removing the high-k film. It is possible to carry out in one step at a time. As a result, the number of steps is reduced, so that the throughput of a process for forming a gate electrode such as a transistor can be improved, and the manufacturing cost can be reduced. In addition, since two types of films having different functions can be removed in a single removal step, device degradation due to plasma damage can be minimized. In addition, the side edge of the gate insulating film can be reduced to a minimum with respect to the buried insulating film (BOX). As a result, the deterioration of device characteristics and the yield can be remarkably suppressed.
• BOX buried insulating film
• a processing gas containing O 2 is used.
• the processing gas containing O 2 is a gas containing O and CF.
• a chemical solution containing hydrofluoric acid is used.
• the chemical solution containing hydrofluoric acid contains hydrofluoric acid and Daricols such as ethylene glycol and propylene glycol.
• the present invention includes an ashing device that performs a plasma modification process on a semiconductor substrate, a cleaning device that performs wet cleaning on the semiconductor substrate, and a method for manufacturing a semiconductor device having the above characteristics.
• the semiconductor device manufacturing system includes a control unit that controls the ashing device and the cleaning device.
• a program for controlling a method of manufacturing a semiconductor device having the above characteristics and a computer-readable recording medium including the program are also subject to protection in this case.
• FIG. 1A to FIG. 1G are schematic views showing states of wafer cross sections in the order of steps of a gate electrode forming process according to an embodiment of the present invention.
• FIG. 2 is a flowchart showing main steps in the gate electrode formation process of FIGS. 1A to 1G.
• FIG. 3A to FIG. 3H are schematic views showing states of wafer cross sections in the order of steps of a gate electrode formation process according to another embodiment of the present invention.
• FIG. 4 is a flowchart showing main steps in the gate electrode formation process of FIGS. 3A to 3H.
• FIG. 5 is a schematic block diagram showing a semiconductor device manufacturing system suitable for implementing the present invention.
• FIG. 6 is a schematic view showing an example of an etching apparatus.
• FIG. 7 is a schematic view showing an example of a spin cleaning apparatus.
• FIG. 8 is a schematic view showing an example of a dip type cleaning apparatus.
• FIGS. 9A to 9H are schematic views showing states of wafer cross sections in the order of steps of a conventional gate forming process.
• FIG. 1A to FIG. 1G are schematic views showing states of wafer cross sections in the order of steps of a MOS transistor gate electrode forming process according to an embodiment of the present invention.
• FIG. 2 is a flowchart showing main steps in the gate electrode formation process of FIGS. 1A to 1G.
• FIG. 1A shows a stacked structure of a gate formation site before etching.
• a gate insulating film for example, HfO, HfSiO
• a high-k film 102 such as 2 x is formed.
• the high-k film 102 can be formed by, for example, CVD.
• a polysilicon film 103 is formed on the high-k film 102 by, for example, CVD.
• a SiC-based film 106 made of, for example, SiCH or SiCOH is formed.
• a patterned photoresist film 110 is formed on the SiC film 106.
• the SiC-based film 106 has a two-layer laminated structure of a mask functional film 104 that functions as a hard mask with SiCH material force and an ARC film 105 that functions as ARC with SiCOH material force. Yes.
• a SiC film 106 is disclosed in Non-Patent Document 1 and is provided by IBM under the name “TERA”.
• This SiC-based film 106 is a multi-layered film formed by plasma CVD, and exposure light having a predetermined wavelength depends on the material of the base film (here, the polysilicon film 103) and the photoresist film 110.
• the complex refractive index represented by n + ik (where n is the refractive index and k is the extinction coefficient) of each film is adjusted.
• n of each film at a wavelength of 193 nm is adjusted to about 1.62-2.26, and k is adjusted to about 0.045 to 0.75.
• These values can be adjusted by changing film formation conditions such as film formation temperature, pressure, flow rate, gas composition, and the like.
• an ARC film 105 having a SiCOH composition adjacent to the photoresist film 110 and The mask function film 104 having a SiCH composition adjacent to the polysilicon film 103 to be etched can have a two-layer structure in which n and k are different from each other.
• n and k are different from each other.
• this SiC-based film is an inorganic film, it can be etched with a high selectivity with respect to the photoresist film 110. Further, a high selection ratio can be obtained for the polysilicon film 103 which is a film to be etched. In other words, this SiC film can exhibit an excellent hard mask function.
• FIG. 1B shows a state after the ARC film 105 and the mask functional film 104 are etched using the photoresist film 110 as a mask in step S301 (see FIG. 2).
• Etching of the ARC film 105 and the mask functional film 104 is performed by dry etching using, for example, SF gas.
• FIG. 1C shows the state after the photoresist film 110 is removed in step S302 (see FIG. 2) but before the polysilicon film 103 is etched.
• FIG. 1D shows a state after step S303 (see FIG. 2), that is, after the polysilicon film 103 is etched using the ARC film 105 and the mask function film 104 as a mask. At this stage, the ARC film 105 is also removed by etching, and the mask functional film 10
• the film thickness of 4 is also reduced.
• FIG. 1E shows a state in which plasma processing is performed on the high-k film 102 and the mask function film 104 exposed by etching the polysilicon film 103 (step S3).
• the high-k film 102 and the mask function film 104 are oxidized by the action of ions in the plasma and modified to a porous material.
• the plasma treatment conditions for the modification treatment will be described in detail later.
• FIG. 1F shows a state after the high-k film 102 and the mask functional film 104 are removed by wet cleaning (wet etching) in step S305 (see FIG. 2).
• the bra Since the high-k film 102 and the mask functional film 104 are made porous by the Kursa treatment, they can be removed in a single step in this way. As will be described later, the wet cleaning can be performed under predetermined conditions using a dip cleaning device or a spin cleaning device.
• FIG. 1G shows a state in which the sidewall 107 is formed by CVD in step S306 (see FIG. 2) on the gate stacked body obtained as described above.
• the source region is formed, the drain region is formed, the interlayer insulating film is deposited, the contact hole is formed, etc.
• a gate electrode is produced.
• FIGS. 3A to 3H are schematic views showing the states of the wafer cross sections in the order of the gate electrode formation process of the MOS transistor according to another embodiment of the present invention.
• FIG. 4 is a flowchart showing main steps in the gate electrode formation process of FIGS. 3A to 3H.
• FIG. 3A shows a stacked structure of a gate formation site before etching.
• a gate insulating film for example, HfO, HfSiO
• a high-k film 102 such as 2 x is formed.
• the high-k film 102 can be formed by, for example, CVD.
• a polysilicon film 103 is formed on the high-k film 102 by, for example, CVD.
• silicon nitride (SiO 2) is nitrided key.
• a hard mask film 111 such as silicon (Si N) is formed. On the hard mask film 111
• a SiC-based film 114 having a SiCH material and a SiCOH material force is formed. Further, a patterned photoresist film 110 is formed on the SiC-based film 114.
• the SiC-based film 114 has a two-layer structure of a first ARC film 112 having a hard mask function and a second ARC film 113 having a composition different from that of the first ARC film 112. ing.
• the first ARC film 112 is a film containing SiCH as a main component, for example, and has a composition mainly focused on the hard mask function.
• the second ARC film 113 is a film mainly composed of, for example, SiCOH.
• FIG. 3B shows the first step using the photoresist film 110 as a mask in step S311 (see FIG. 4).
• the state after the ARC film 112 and the second ARC film 113 are etched is shown!
• the first ARC film 112 and the second ARC film 113 are etched using, for example, SF gas.
• FIG. 3C shows a step S312 (see FIG. 4) in which the first ARC film 112 and the second ARC film 113 are used as a mask and the hard mask film 111 is dry-etched using a CF-based gas.
• FIG. 3D shows a step S313 (see FIG. 4) in which the first ARC film 112 and the hard mask film 111 are used as a mask, and the polysilicon film 103 is dry-etched using HBr or C12 gas. It is the state after.
• FIG. 3E shows a state in which the high-k film 102, the first ARC film 112, and the node mask film 111 exposed by etching the polysilicon film 103 are subjected to plasma treatment.
• Step S314 the high-k film 102 and the first ARC film 112 are oxidized by the action of ions in the plasma and modified to a porous material.
• the plasma treatment conditions for the modification treatment will be described in detail later.
• FIG. 3F shows a state after the high-k film 102 and the first ARC film 112 are removed by wet cleaning (wet etching) in step S315 (see FIG. 4). Since the high-k film 102 and the first ARC film 112 are made porous by the plasma treatment, they can be removed in a single step in this way. As will be described later, the wet cleaning can be performed under predetermined conditions using a dip cleaning device or a spin cleaning device.
• FIG. 3G shows a state in which the sidewall 107 is formed by CVD in step S316 (see FIG. 4) on the gate stacked body obtained as described above.
• FIG. 3H shows a state after the remaining hard mask 111 is removed in step S317 (see FIG. 4).
• the hard mask 111 is removed by dry etching using CHF or CF gas when etching the sidewall 107, or It can be performed by performing wet etching with an HF chemical solution.
• FIG. 5 is a schematic block diagram showing a semiconductor device manufacturing system 200 suitable for implementing the present invention.
• the semiconductor device manufacturing system 200 includes a processing unit 100 including an etching apparatus 1 that performs an etching process using plasma, an ashing apparatus 60 that performs a modification process using plasma, and a cleaning apparatus 70 that performs wet cleaning. ing.
• a process controller 90, a storage unit 92, and a user interface 91 are provided. (Here, only the parts related to the plasma etching process (dry etching), the modification process (plasma ashing), and the wet cleaning process (wet etching) will be described.)
• Each device of the processing unit 100 includes a CPU. Is connected to the process controller 90 and is controlled by the process controller 90! /.
• the process manager visualizes and displays the operation status of each device of the processing unit 100 and a keyboard for performing a command input operation and the like in order to manage each device of the processing unit 100
• an arbitrary recipe is called from the storage unit 92 based on an instruction from the user interface 91 and executed by the process controller 90.
• various desired processes are performed in the processing unit 100 under the control of the process controller 90.
• the recipe for example, a recipe stored in a readable storage medium such as a CD-ROM, a hard disk, a flexible disk, or a nonvolatile memory is used.
• the processing unit 100 can be used on-line between each device or an external device power via a dedicated line or the like.
• FIG. 6 is a schematic view showing an example of an etching apparatus that can be used in the method of the present invention.
• this etching apparatus 1 the upper and lower parallel electrode plates face each other, and a high frequency power It is a connected capacitively coupled parallel plate type etching apparatus.
• This etching apparatus 1 has a chamber 1 formed into a cylindrical shape made of aluminum having a surface anodized (anodized), for example. This chamber 1 is grounded. In the chamber 12, for example, a susceptor 5 having a silicon force is provided in a state of being supported by a susceptor support 4. On the susceptor 5, a wafer W on which a predetermined film is formed is placed horizontally as an object to be processed. The susceptor 5 functions as a lower electrode and is connected to a no-pass filter (HPF) 6.
• HPF no-pass filter
• a temperature control medium chamber 7 is provided inside the susceptor support 4.
• a temperature control medium is introduced into the temperature control medium chamber 7 and circulated through the introduction pipe 8. Thereby, the susceptor 5 can be controlled to a desired temperature.
• the central portion of the upper surface of the susceptor 5 is formed in a convex disk shape, and an electrostatic chuck 11 having substantially the same shape as Ueno and W is provided on the upper surface.
• the electrostatic chuck 11 has a configuration in which an electrode 12 is interposed between insulating materials. For example, a DC voltage of 1.5 kV is applied to the electrode 12 from a DC power source 13 connected to the electrode 12. Thereby, the wafer W is electrostatically attracted by the Coulomb force.
• the insulating plate 3, the susceptor support 4, the susceptor 5 and the electrostatic chuck 11 are supplied with a heat transfer medium such as He gas on the back surface of the wafer W, which is the object to be processed, at a predetermined pressure (back pressure).
• the gas passage 14 is formed to supply the gas at 14). Heat is transferred between the susceptor 5 and the wafer W through this heat transfer medium. As a result, the wafer W is maintained at a predetermined temperature.
• An annular focus ring 15 is arranged at the upper peripheral edge of the susceptor 5 so as to surround the Ueno and W mounted on the electrostatic chuck 11.
• the focus ring 15 is made of an insulating material such as ceramic or quartz, and acts to improve the uniformity of the etching process.
• An upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5 in parallel.
• the upper electrode 21 is supported on the upper portion of the chamber 12 through an insulating material 22.
• the upper electrode 21 includes an electrode plate 24 that has a surface facing the susceptor 5 and has a large number of discharge holes 23, and an electrode support 25 that supports the electrode plate 24. Electric
• the electrode plate 24 is made of, for example, an aluminum cable.
• the electrode support 25 is made of a conductive material, for example, aluminum whose surface is anodized. The distance between the susceptor 5 and the upper electrode 21 can be adjusted.
• a gas inlet 26 is provided at the center of the electrode support 25 in the upper electrode 21.
• a gas supply pipe 27 is connected to the gas inlet 26.
• a processing gas supply source 30 is connected to the gas supply pipe 27 via a valve 28 and a mass flow controller 29. As a result, the etching gas for plasma etching is supplied from the processing gas supply source 30 to the gas inlet 26.
• FIG. 6 only one processing gas supply source 30 is shown as a representative, and a plurality of force processing gas supply sources 30 are usually provided.
• an exhaust pipe 31 is connected to the bottom of the chamber 12.
• An exhaust device 35 is connected to the exhaust pipe 31.
• the exhaust device 35 includes a vacuum pump such as a turbo molecular pump. Thereby, the inside of the chamber 12 can be evacuated to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 1 Pa or less.
• a gate valve 32 is provided on the side wall of the chamber 12. With the gate valve 32 opened, the wafer W is transported between adjacent load lock chambers (not shown).
• a first high-frequency power source 40 is connected to the upper electrode 21, and a matching unit 41 is provided on the feeder line.
• a low pass filter (LPF) 42 is connected to the upper electrode 21.
• the first high frequency power supply 40 has a frequency in the range of 50 to 150 MHz. By applying such a high frequency to the upper electrode 21, it is possible to form a plasma with a favorable LV, dissociated state and high density in the chamber 12, and it is possible to perform plasma processing under low pressure conditions. Become.
• the frequency of the first high frequency power supply 40 is particularly preferably 50 to 80 MHz. Typically, as shown in FIG. 6, a value of 60 MHz or its vicinity is adopted.
• a second high-frequency power supply 50 is connected to the susceptor 5 as the lower electrode, and a matching unit 51 is provided on the power supply line.
• the second high frequency power supply 50 has a frequency in the range of several hundred kHz to several tens of MHz.
• the lower electrode has power in this range of frequencies. By being applied, an appropriate ion action can be given without damaging the wafer W.
• As the frequency of the second high frequency power supply 50 for example, a value such as 2 MHz or 800 kHz is adopted as shown in FIG.
• the gate valve 32 is opened, and the wafer W is loaded into the load lock chamber force chamber 2 (not shown) and placed on the electrostatic chuck 11. Then, a DC voltage is applied from the high-voltage DC power source 13, and Ueno and W are electrostatically attracted onto the electrostatic chuck 11.
• the gate valve 32 is closed, and the inside of the chamber 12 is evacuated to a predetermined vacuum level by the exhaust device 35.
• the valve 28 is opened, and the processing gas supply source 30 supplies a processing gas for etching, for example, by CF force mass flow controller 29.
• the process gas supply pipe 27, the gas introduction port 26, the hollow portion of the upper electrode 21, and the discharge hole 23 of the electrode plate 24 are indicated by arrows in FIG.
• the wafer W is uniformly discharged.
• the pressure in the chamber 12 is maintained at a predetermined pressure, for example, about 1.3-13. Also, a 200 W high frequency voltage force is applied from the first high frequency power supply 40 to the upper electrode 21, and a 200 W high frequency voltage force is applied from the second high frequency power supply 50 to the susceptor 5 as the lower electrode. As a result, the etching gas is turned into plasma, and the wafer W is etched.
• the ashing device 60 will be described. Capacitively coupled parallel plate type plasma processing apparatus force ashing apparatus 60 configured in the same manner as etching apparatus 1 in FIG. 6 can be used. In other words, the modification treatment of the SiC-based film and the high-k film by plasma can be performed by an apparatus having the same configuration as the etching apparatus 1 in FIG. 6 except that the processing gas supplied from the processing gas supply source 30 is changed. . For this reason, the illustration and description of the configuration of the ashing device 60 are omitted, and only the conditions for the reforming process will be described below. It should be noted that the etching process and the modification process may be performed in the same chamber by an apparatus that combines the etching apparatus 1 and the ashing apparatus 60.
• the conditions for the reforming process in the ashing device 60 are as follows.
• processing gas For example, a gas containing O 2 can be used.
• a mixed gas of O and CF is used.
• the mass flow controller 29 mixes O and CF.
• the temperature of the wafer W is maintained at about 250 ° C., for example.
• the pressure in the chamber 1 is maintained at, for example, about 1.3 to 13.3 Pa, preferably 2.7 to 8 Pa.
• a high frequency voltage of 10 to 2500 W is applied from the first high frequency power supply 40 to the upper electrode 21, and a high frequency voltage of 10 to 2500 W is applied from the second high frequency power supply 50 to the susceptor 5 as the lower electrode.
• the processing gas is turned into plasma and applied to the SiC film and high-k film.
• the SiC-based film and the high-k film are oxidized and made porous.
• the porous SiC-based film and the high-k film can be easily separated and removed by wet cleaning performed under the predetermined conditions described below.
• FIG. 7 is a schematic view of a spin cleaning device 71 that can be used as the cleaning device 70.
• the spin cleaning apparatus 71 includes a cup CP, a spin chuck 72 that is provided in the cup CP and horizontally holds the wafer W by suction, a motor 73 that rotates the spin chuck 72, a nozzle 74 that supplies a chemical solution 88, have.
• This spin cleaning apparatus 71 rotates the spin chuck 72 and the wafer W adsorbed and held by the motor 73 while rotating the wafer W while spraying the chemical solution 88 from the nozzle 74 to the center of the wafer W.
• the chemical solution 88 is spread over the entire surface and wet cleaning of wafer W is performed.
• FIG. 8 is a schematic diagram of a dip type cleaning device 80 which is another example of the cleaning device.
• This dip type cleaning device 80 includes an outer tub 81 and an inner tub 82 that constitute a double-structured container, a jig-like jig 83, a chemical circulation path 84, a pump 85, and a foino letter 86. And heat exchange. Then, the inner tank 82 is filled with the chemical solution 88, and the jig 83 is used to immerse the plurality of wafers W in the inner tank 82 (in the chemical solution 88) while keeping them separated from each other vertically. By doing so, the wet cleaning process of the wafer W is performed.
• the chemical solution overflowed from the inner tank 82 is circulated through the circulation path 84 by the pump 85. Foreign matter is removed from the chemical solution 88 in the circulation path 84 by the filter 86, the temperature is adjusted by the heat exchanger 87, and then returned to the inner tank 82.
• a capacity-coupled parallel plate type plasma processing apparatus is used as the etching apparatus 1 and the ashing apparatus 60! /, But plasma is formed with a predetermined gas pressure. If it can, the type of plasma processing equipment is not questioned. For example, various inductively coupled plasma processing apparatuses can be used. Further, different types of apparatuses can be used as the etching apparatus 1 and the ashing apparatus 60.

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• Drying Of Semiconductors (AREA)
• Electrodes Of Semiconductors (AREA)
• Weting (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2004
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