TW200629404A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
TW200629404A
TW200629404A TW094146529A TW94146529A TW200629404A TW 200629404 A TW200629404 A TW 200629404A TW 094146529 A TW094146529 A TW 094146529A TW 94146529 A TW94146529 A TW 94146529A TW 200629404 A TW200629404 A TW 200629404A
Authority
TW
Taiwan
Prior art keywords
mentioned
high dielectric
dielectric film
manufacturing
semiconductor device
Prior art date
Application number
TW094146529A
Other languages
English (en)
Chinese (zh)
Other versions
TWI368944B (https=
Inventor
Glenn Gale
Yoshihiro Hirota
Yusuke Muraki
Genji Nakamura
Masato Kushibiki
Naoki Shindo
Akitaka Shimizu
Shigeo Ashigaki
Yoshihiro Kato
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200629404A publication Critical patent/TW200629404A/zh
Application granted granted Critical
Publication of TWI368944B publication Critical patent/TWI368944B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326Aspects related to lithography, isolation or planarisation of the conductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/71Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/73Etching of wafers, substrates or parts of devices using masks for insulating materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/931Silicon carbide semiconductor

Landscapes

  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094146529A 2004-12-28 2005-12-26 Manufacturing method of semiconductor device TW200629404A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004380704A JP4791034B2 (ja) 2004-12-28 2004-12-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200629404A true TW200629404A (en) 2006-08-16
TWI368944B TWI368944B (https=) 2012-07-21

Family

ID=36614678

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094146529A TW200629404A (en) 2004-12-28 2005-12-26 Manufacturing method of semiconductor device

Country Status (7)

Country Link
US (1) US7897498B2 (https=)
EP (1) EP1835529A4 (https=)
JP (1) JP4791034B2 (https=)
KR (1) KR100845453B1 (https=)
CN (1) CN100472730C (https=)
TW (1) TW200629404A (https=)
WO (1) WO2006070553A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8883653B2 (en) 2011-01-20 2014-11-11 SCREEN Holdings Co., Ltd. Substrate treatment method and substrate treatment apparatus

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021550A (ja) * 2007-07-12 2009-01-29 Panasonic Corp 半導体装置の製造方法
JP5801676B2 (ja) * 2011-10-04 2015-10-28 東京エレクトロン株式会社 半導体装置の製造方法
US20160020246A1 (en) * 2014-07-15 2016-01-21 United Microelectronics Corporation Method for fabricating cmos image sensors and surface treating process thereof
JP6046757B2 (ja) * 2014-09-30 2016-12-21 株式会社日立国際電気 基板処理装置、半導体装置の製造方法、プログラム
CN108885402B (zh) * 2016-02-29 2020-01-14 东京毅力科创株式会社 选择性SiARC去除
US20230028297A1 (en) * 2021-07-23 2023-01-26 Micron Technology, Inc. Methods of forming an apparatus comprising silicon carbide materials and related microelectronic devices and systems
JP7329021B2 (ja) * 2021-09-14 2023-08-17 株式会社Kokusai Electric 半導体装置の製造方法、基板処理方法、基板処理システム、およびプログラム

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3279016B2 (ja) * 1993-12-03 2002-04-30 ソニー株式会社 ドライエッチング方法
JP3257245B2 (ja) 1994-05-18 2002-02-18 ソニー株式会社 微細パターンの形成方法
US5762813A (en) * 1995-03-14 1998-06-09 Nippon Steel Corporation Method for fabricating semiconductor device
KR100309225B1 (ko) * 1996-01-26 2002-02-19 모리시타 요이찌 반도체장치의제조장치및드라이에칭방법
US6316167B1 (en) 2000-01-10 2001-11-13 International Business Machines Corporation Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof
US6599814B1 (en) * 1999-05-03 2003-07-29 Interuniversitair Microelektronica Centrum (Imec) Method for removal of sic
JP3430091B2 (ja) 1999-12-01 2003-07-28 Necエレクトロニクス株式会社 エッチングマスク及びエッチングマスクを用いたコンタクトホールの形成方法並びにその方法で形成した半導体装置
JP2002252211A (ja) 2001-02-23 2002-09-06 Nec Corp 半導体装置の製造方法
US6777171B2 (en) * 2001-04-20 2004-08-17 Applied Materials, Inc. Fluorine-containing layers for damascene structures
US6667246B2 (en) 2001-12-04 2003-12-23 Matsushita Electric Industrial Co., Ltd. Wet-etching method and method for manufacturing semiconductor device
JP3727299B2 (ja) * 2001-12-04 2005-12-14 松下電器産業株式会社 半導体装置の製造方法
US7887711B2 (en) 2002-06-13 2011-02-15 International Business Machines Corporation Method for etching chemically inert metal oxides
US6759286B2 (en) * 2002-09-16 2004-07-06 Ajay Kumar Method of fabricating a gate structure of a field effect transistor using a hard mask
JP2004165555A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8883653B2 (en) 2011-01-20 2014-11-11 SCREEN Holdings Co., Ltd. Substrate treatment method and substrate treatment apparatus

Also Published As

Publication number Publication date
JP4791034B2 (ja) 2011-10-12
US20080268655A1 (en) 2008-10-30
CN100472730C (zh) 2009-03-25
US7897498B2 (en) 2011-03-01
TWI368944B (https=) 2012-07-21
CN101107698A (zh) 2008-01-16
JP2006186244A (ja) 2006-07-13
EP1835529A1 (en) 2007-09-19
KR100845453B1 (ko) 2008-07-10
EP1835529A4 (en) 2008-10-22
KR20070086783A (ko) 2007-08-27
WO2006070553A1 (ja) 2006-07-06

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