WO2006046274A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2006046274A1 WO2006046274A1 PCT/JP2004/015774 JP2004015774W WO2006046274A1 WO 2006046274 A1 WO2006046274 A1 WO 2006046274A1 JP 2004015774 W JP2004015774 W JP 2004015774W WO 2006046274 A1 WO2006046274 A1 WO 2006046274A1
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- interlayer insulating
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 56
- 239000011574 phosphorus Substances 0.000 claims abstract description 56
- 239000011229 interlayer Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 23
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 154
- 230000015654 memory Effects 0.000 description 24
- 239000005380 borophosphosilicate glass Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 11
- 230000014759 maintenance of location Effects 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000002474 experimental method Methods 0.000 description 6
- 238000005247 gettering Methods 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a nonvolatile semiconductor memory having an ONO (Oxide / Nitride / Oxide) film and a method for manufacturing the same.
- ONO Oxide / Nitride / Oxide
- nonvolatile memories which are semiconductor devices capable of rewriting data
- technological development is underway to increase the amount of bits per unit area and reduce the cost per unit bit.
- NOR-type array-type floating gate flash memory has the feature that random access is possible, but on the other hand, it is necessary to provide a bit line contact for each cell. There is a problem that density is difficult.
- NAND-type floating gate type flash memory allows cells to be connected in series to reduce the number of bitline contacts, enabling high-density arrangement of cells, but not random access. There is a problem.
- a floating gate type flash memory is generally not easy to form a thin film of a tunnel insulating film, and this is a technical obstacle when a large capacity memory is used.
- Such a buried bit line type SONOS memory has a simple structure compared to a floating gate type cell, can be randomly accessed, and has an array structure that is contactless. In addition, it can store 2 bits of information at a high density and can store high-density information (the cell area can be reduced to about 1Z2), making it an extremely useful device in the industry.
- the buried bit line structure means that a bit line 'contact window is formed for each transistor even though it is a NOR type memory by forming a source / drain diffusion layer below the word line to be a bit line of a SONOS type memory.
- the array structure eliminates the need to provide
- a metal wiring layer is formed on the interlayer insulating film formed on the ONO film, and the contact hole formed in the interlayer insulating film and the ONO film is used. The metal wiring layer and the bit line are connected.
- an interlayer insulating film having a two-layer structure has been proposed for a floating gate type flash memory.
- the interlayer insulating film is formed on an oxide silicon film that does not contain an impurity covering the gate electrode, and has a lower layer portion with a high phosphorus concentration and a low boron concentration, and a boron concentration relatively low with respect to the lower layer portion. It consists of an upper layer with a high concentration.
- the upper BPSG film since the upper BPSG film has a low phosphorus concentration and is difficult to absorb moisture, the lower layer has a high phosphorus concentration and easily absorbs moisture. It is explained that the moisture cannot reach the device surface because it is fixed to the lower BPSG film. As a result, it is considered that when the gate oxide film is damaged by the invasion of water, the phenomenon that all charges accumulated in the floating gate formed of the conductor flow out can be prevented.
- Patent Document 1 Japanese Patent No. 2791090
- An object of the present invention is to improve a charge loss inherent to this structure and improve data retention characteristics in a flash memory having an ONO film.
- the present invention relates to a semiconductor substrate and an ON formed on the semiconductor substrate.
- the semiconductor device includes an O film and an interlayer insulating film formed directly on the ONO film, and the interlayer insulating film includes phosphorus.
- the semiconductor device may include a gate electrode formed on the ONO film, and the interlayer insulating film may be directly formed on the gate electrode.
- the semiconductor device has a gate electrode formed on the ONO film, and the interlayer insulating film is formed so as to be in contact with the silicide region formed on the gate electrode. I'll do it.
- the interlayer insulating film has a first portion in contact with the ONO film, and a second portion provided on the first portion, and the phosphorus concentration of the first portion is the first. It is above the phosphorus concentration in part 2.
- the second portion can include boron.
- the interlayer insulating film is, for example, a CVD oxide film or a SOD (SPIN ON DIELECTRIC) film, and the CVD oxide film may be either a TEOS oxide film or an HDP oxide film. Good.
- the present invention also includes a step of forming an ONO film on a semiconductor substrate in which a diffusion region is formed, a step of forming an interlayer insulating film containing phosphorus on the ONO film, and the interlayer insulating film and And a step of forming a contact hole in the ONO film and forming a metal wiring layer in contact with the diffusion region through the contact hole on the interlayer insulating film.
- the interlayer insulating film it is preferable that the interlayer insulating film is formed so as to contain 4.5 wt% or more of phosphorus at the interface with the ONO film.
- Phosphorus contained in the interlayer insulating film provided on the ONO film is considered to have an action of gettering mobile ions entering the contact hole force contact provided in the ONO film, and charge loss. And data retention characteristics can be improved.
- the interlayer insulating film containing phosphorus is directly formed on the ONO film, a special effect is obtained that mobile ions can be effectively gettered.
- FIG. 1 shows the results of experiments conducted by the present inventors, respectively.
- Fig. 1 (A) shows the growth conditions and boron concentration of the BPSG film.
- FIG. 1 (B) is a graph showing the relationship between the growth conditions of the BPSG film and the phosphorus concentration.
- FIG. 2 is a graph showing the results of an experiment conducted by the present invention, and is a graph showing the relationship between the initial layer phosphorus concentration (interface portion) of the BPSG film and the defect rate.
- FIG. 3A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention
- FIG. 3B is a cross-sectional view showing the structure of an ONO film of the semiconductor device.
- FIG. 5 (A) and FIG. 5 (B) are views showing a method of manufacturing a semiconductor device according to one embodiment of the present invention.
- the present inventor has experimentally identified one of the causes of the deterioration of the data retention characteristics in the flash memory having the ONO film.
- a BPSG film was grown on the ONO film, and the boron concentration and phosphorus concentration were measured.
- the boron concentration after film formation is almost constant without depending on the film thickness and is not much different from the design value, whereas the phosphorus concentration is not uniform in the film thickness direction and has a gradient.
- the phosphorus concentration at the interface became extremely low.
- Figures 1 (A) and (B) show the experimental results.
- the horizontal axis shows the three deposition methods described below, and the vertical axis shows the P concentration.
- BPSG with a film thickness of 0.6 m (6000 angstroms) was formed by the following three methods. In the first method, two 0.3 ⁇ m mOBPSG films were stacked. In the second method, four 1.5 m BPSG films were stacked. In the third method, six layers of 0.1 m BPSG film were stacked. All BPSG films were formed so that the boron concentration after deposition was 4.5 wt% and the phosphorus concentration was 4.5 wt%.
- Fig. 1 (A) shows the boron concentration
- Fig. 1 (A) shows the boron concentration
- FIG. 1 (B) shows the phosphorus concentration.
- the boron concentration was almost constant regardless of the thickness of the BPSG film, whereas the phosphorus concentration decreased with decreasing film thickness.
- the experimental results in Fig. 1 (B) show that when a 0.6 m BPSG film is formed, the concentration of the initial layer near the interface with the ONO film is low.
- Figure 2 is a graph showing the relationship between the phosphorus concentration in the initial layer of the BPSG film and the failure rate due to the charge loss.
- the failure rate was almost 0%, whereas when it was 4.1%, the failure rate increased.
- the data retention characteristics depended heavily on the phosphorus concentration of the interlayer insulating film at the interface of the ONO film. 4. It is readily expected that the defect rate will gradually increase at concentrations from 5 wt% to 4.1%, and it is clear that the defect rate is almost 0% at phosphorus concentrations exceeding 4.5 wt%. .
- the total concentration of impurities in the BPSG film is preferably 10 wt% or less. .
- the first part is a PSG film containing 4.5 wt% or more and 10. Owt% or less of phosphorus
- the second part is a B PSG film whose total of phosphorus concentration and boron concentration is 10. Owt% or less.
- the first part, the PSG film contacts the ONO film.
- the concentration of phosphorus does not have to be uniform in the first part, and there may be a concentration gradient within the range of 4.5 wt% or more and 10.0 ⁇ % or less.
- the phosphorus concentration decreases as the interfacial force with the ONO film increases.
- the phosphorus concentration in the first part may be equal to or higher than the phosphorus concentration in the second part.
- the film thickness of the interface portion where the phosphorus concentration is 4.5 wt% or more, that is, the first portion is preferably at least 0.02 ⁇ m or more. That is, if it is more than this thickness, it is considered that the influence of working ions can be eliminated, and good data retention characteristics can be obtained. More specifically, the film thickness of the first part is preferably in the range of 0.02 111 to 0.20 / zm. The thickness of the interface is preferably within a range in which phosphorus gettering action is effectively exhibited and voids are not generated. Alternatively, the upper limit of the thickness is preferably 1Z2 or less, which is the minimum interval between the electrodes embedded in the interlayer insulating film 10.
- FIG. 3A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
- the semiconductor device shown shows the core part of the flash memory.
- a well region 2 is formed on a surface portion of a semiconductor substrate 1 such as silicon, and a bit line region 3 is formed in the well region 2.
- An ONO film 4 is formed on the entire core portion of the semiconductor substrate 1.
- the ONO film 4 has an ONO structure in which a tunnel insulating film 4a, a storage nitride film 4b, and an oxide film 4c are stacked in order of force on the semiconductor substrate 1 side. This nitride film 4b accumulates trapped charges.
- a contact hole 11 is formed in the ONO film 4.
- a gate electrode 5 is formed on the ONO film 4, and a side wall 7 is formed on the side thereof. Further, a CoSi region 6 made of salicide is formed on the upper surface of the gate electrode 5. Of this silicide film Instead of Co, Ti, N, or Pt may be used.
- the interlayer insulating film 10 is directly formed.
- the interlayer insulating film 10 is the ONO film 4 or CoSi region.
- the interlayer insulating film 10 has the structure described in the best mode for carrying out the invention.
- the interlayer insulating film 10 shown in FIG. 3A is a CVD oxide film or SOD (SPIN ON DI ELECTRIC) film.
- Examples of the CVD oxide film include a TEOS oxide film or an HDP oxide film. It is.
- the interlayer insulating film 10 has a two-layer structure including a first portion 8 and a second portion 9.
- the first portion 8 is a PSG film
- the second portion 9 is a BPSG film.
- the phosphorus concentration of PSG film 8 (phosphorus concentration immediately after depositing the PSG film) is not less than 4.5 wt% and not more than 10.0 wt%, and has a thickness of 0.05 m.
- the BPSG film 9 has a phosphorus concentration (phosphorus concentration immediately after depositing the PSG film) of, for example, 2.9 wt%, and has a thickness of about 1.15 m immediately after the film formation. Therefore, the final device configuration has a thickness of about 0.8 m.
- the boron concentration of the BPSG film 9 is an arbitrary value of 7.1% or less and the force is too low, voids are generated, so an appropriate boron concentration is set.
- a contact hole 13 continuing from the contact hole 11 formed in the ONO film 4 is formed.
- the metal wiring layer 14 formed on the interlayer insulating film 10 and the bit line region 3 are electrically connected via contact holes 11 and 13 (they are filled with a conductor 12). ! Speak.
- FIG. 4 shows the defect rate of the present example and the defect rate of a comparative example in which the interlayer insulating film 10 is formed of BPSG (the phosphorus concentration in the interface portion is 2.9 wt%).
- the film thickness of the comparative example is 1.2 / ⁇ ⁇ immediately after the film formation and 0.8 m after the CMP process, as in this example. According to this example, it can be seen that the defect rate is improved as compared with the comparative example.
- One reason for this is that the mobile ions that have penetrated into the conductor 12 of the contact hole 11 (intruded into the contact) are also gettered by the phosphorus contained in the first portion 8 of the interlayer insulating film 10. I think that. At this time, since the first portion 8 is formed so as to be in direct contact with the ONO film 4, it is considered that the gettering force by phosphorus is more effectively performed.
- FIGS. 5A and 5B are diagrams showing a manufacturing process of the semiconductor device according to the above embodiment.
- FIG. 5 (a) shows a process until the ONO film 4 is formed on the semiconductor substrate 1.
- the tunnel insulating film 121, the storage nitride film 122, and the oxide film 123 are sequentially stacked to form the ONO structure film 4.
- An opening for forming the bit line region 3 is provided at a predetermined location by photolithography. These opening forces are also ion-implanted to form the bit line region 3.
- the main surface of the semiconductor substrate 100 from which the insulating film of the core portion and the peripheral circuit portion (not shown) is removed by HF treatment is thermally oxidized to form a 7 nm-thickness tunnel oxide film.
- a CVD nitride film having a thickness of lOnm is deposited on the tunnel oxide film, and a CVD oxide film is deposited on the CVD nitride film to form an ONO structure.
- OX 10 15 cm- 2 is ion-implanted at an acceleration voltage of 50 KeV from the opening for forming the bit line diffusion layer to form the bit line region 4.
- the ONO film 4 is a force that is formed not only in the core part but also in the peripheral circuit part. Since this ONO structure is not required in the peripheral circuit part, the ONO film 4 in the peripheral circuit part is obtained by resist patterning technology. Remove.
- a gate electrode conductive film is grown on the ONO film 4, and resist patterning and etching are performed on the conductive film for the gate electrode 5 (word line).
- the gate electrode conductive film is, for example, a polysilicon film having a thickness of 0.18 / zm grown by a thermal CVD method.
- sidewalls 7 are formed on the side surfaces of the gate electrode 5.
- a CoSi region 6 is formed using a salicide process using cobalt.
- a silicon oxide film by a CVD method such as TEOS or HDP is deposited to form an interlayer insulating film 10.
- the dose of phosphorus and boron is controlled to form the interlayer insulating film 10 having the above-described configuration.
- a contact hole 13 is formed in the interlayer insulating film 10
- a contact hole 11 is formed in the ONO film 4
- a conductor 12 is filled in the contact holes 11 and 13, and a metal wiring layer 14 is formed.
- the semiconductor device of the present invention includes not only a semiconductor memory device such as a flash memory but also various types of semiconductor devices including a flash memory and other semiconductor circuits.
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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DE112004003004T DE112004003004T5 (de) | 2004-10-25 | 2004-10-25 | Halbleiterbauelement und Verfahren zu dessen Herstellung |
CNA2004800446661A CN101088155A (zh) | 2004-10-25 | 2004-10-25 | 半导体装置及其制造方法 |
PCT/JP2004/015774 WO2006046274A1 (ja) | 2004-10-25 | 2004-10-25 | 半導体装置及びその製造方法 |
JP2006542151A JP5047625B2 (ja) | 2004-10-25 | 2004-10-25 | 半導体装置及びその製造方法 |
US11/258,823 US20060214218A1 (en) | 2004-10-25 | 2005-10-25 | Semiconductor device and method of fabricating the same |
GB0707819A GB2434486A (en) | 2004-10-25 | 2007-04-24 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2004/015774 WO2006046274A1 (ja) | 2004-10-25 | 2004-10-25 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/258,823 Continuation US20060214218A1 (en) | 2004-10-25 | 2005-10-25 | Semiconductor device and method of fabricating the same |
Publications (1)
Publication Number | Publication Date |
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WO2006046274A1 true WO2006046274A1 (ja) | 2006-05-04 |
Family
ID=36227526
Family Applications (1)
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PCT/JP2004/015774 WO2006046274A1 (ja) | 2004-10-25 | 2004-10-25 | 半導体装置及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20060214218A1 (ja) |
JP (1) | JP5047625B2 (ja) |
CN (1) | CN101088155A (ja) |
DE (1) | DE112004003004T5 (ja) |
GB (1) | GB2434486A (ja) |
WO (1) | WO2006046274A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102487057A (zh) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | 金属前介质层及其制造方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158289A (ja) * | 2005-11-11 | 2007-06-21 | Matsushita Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
DE202007001431U1 (de) * | 2007-01-31 | 2007-05-16 | Infineon Technologies Austria Ag | Halbleiteranordnung und Leistungshalbleiterbauelement |
JP2009049230A (ja) * | 2007-08-21 | 2009-03-05 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
US7691751B2 (en) * | 2007-10-26 | 2010-04-06 | Spansion Llc | Selective silicide formation using resist etchback |
US8669597B2 (en) | 2008-05-06 | 2014-03-11 | Spansion Llc | Memory device interconnects and method of manufacturing |
US7951704B2 (en) * | 2008-05-06 | 2011-05-31 | Spansion Llc | Memory device peripheral interconnects and method of manufacturing |
JP2010010260A (ja) * | 2008-06-25 | 2010-01-14 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
JP2010272649A (ja) * | 2009-05-20 | 2010-12-02 | Panasonic Corp | 半導体装置及びその製造方法 |
CN103545227B (zh) * | 2012-07-10 | 2016-08-17 | 无锡华润上华科技有限公司 | 监控半导体器件中磷硅玻璃层的磷浓度的方法 |
JP6828449B2 (ja) * | 2017-01-17 | 2021-02-10 | 株式会社デンソー | 半導体装置およびその製造方法 |
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JPH06232416A (ja) * | 1993-02-03 | 1994-08-19 | Rohm Co Ltd | 半導体記憶装置およびその製法 |
JPH0750396A (ja) * | 1993-08-06 | 1995-02-21 | Sony Corp | Nand型不揮発性半導体メモリ装置およびその製造方法 |
JPH07307339A (ja) * | 1994-04-12 | 1995-11-21 | Sgs Thomson Microelettronica Spa | 平坦化プロセス |
JPH08321502A (ja) * | 1995-03-22 | 1996-12-03 | Nippon Steel Corp | 半導体装置 |
JP2002184717A (ja) * | 2000-10-02 | 2002-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004228351A (ja) * | 2003-01-23 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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US5338954A (en) * | 1991-10-31 | 1994-08-16 | Rohm Co., Ltd. | Semiconductor memory device having an insulating film and a trap film joined in a channel region |
JPH05291414A (ja) * | 1992-04-13 | 1993-11-05 | Ricoh Co Ltd | 半導体装置とその製造方法 |
US5672907A (en) * | 1995-03-22 | 1997-09-30 | Nippon Steel Corporation | Semiconductor device having character in BPSG film |
JPH09213955A (ja) * | 1996-02-01 | 1997-08-15 | Hitachi Ltd | 半導体装置の製造方法 |
JPH1083972A (ja) * | 1996-09-06 | 1998-03-31 | Yamaha Corp | 低抵抗シリサイド層形成法 |
TW449872B (en) * | 1998-11-12 | 2001-08-11 | Hyundai Electronics Ind | Method for forming contacts of semiconductor devices |
US20020061639A1 (en) * | 2000-10-02 | 2002-05-23 | Kazuichiroh Itonaga | Semiconductor device and method for manufacturing the same |
KR100418091B1 (ko) * | 2001-06-29 | 2004-02-11 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US6977408B1 (en) * | 2003-06-30 | 2005-12-20 | Lattice Semiconductor Corp. | High-performance non-volatile memory device and fabrication process |
-
2004
- 2004-10-25 WO PCT/JP2004/015774 patent/WO2006046274A1/ja active Application Filing
- 2004-10-25 JP JP2006542151A patent/JP5047625B2/ja not_active Expired - Fee Related
- 2004-10-25 CN CNA2004800446661A patent/CN101088155A/zh active Pending
- 2004-10-25 DE DE112004003004T patent/DE112004003004T5/de not_active Ceased
-
2005
- 2005-10-25 US US11/258,823 patent/US20060214218A1/en not_active Abandoned
-
2007
- 2007-04-24 GB GB0707819A patent/GB2434486A/en not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH06232416A (ja) * | 1993-02-03 | 1994-08-19 | Rohm Co Ltd | 半導体記憶装置およびその製法 |
JPH0750396A (ja) * | 1993-08-06 | 1995-02-21 | Sony Corp | Nand型不揮発性半導体メモリ装置およびその製造方法 |
JPH07307339A (ja) * | 1994-04-12 | 1995-11-21 | Sgs Thomson Microelettronica Spa | 平坦化プロセス |
JPH08321502A (ja) * | 1995-03-22 | 1996-12-03 | Nippon Steel Corp | 半導体装置 |
JP2002184717A (ja) * | 2000-10-02 | 2002-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004228351A (ja) * | 2003-01-23 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102487057A (zh) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | 金属前介质层及其制造方法 |
CN102487057B (zh) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | 金属前介质层及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
GB2434486A8 (en) | 2007-07-26 |
JP5047625B2 (ja) | 2012-10-10 |
DE112004003004T5 (de) | 2007-10-25 |
JPWO2006046274A1 (ja) | 2008-05-22 |
CN101088155A (zh) | 2007-12-12 |
GB2434486A (en) | 2007-07-25 |
GB0707819D0 (en) | 2007-05-30 |
US20060214218A1 (en) | 2006-09-28 |
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