JP5047625B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP5047625B2 JP5047625B2 JP2006542151A JP2006542151A JP5047625B2 JP 5047625 B2 JP5047625 B2 JP 5047625B2 JP 2006542151 A JP2006542151 A JP 2006542151A JP 2006542151 A JP2006542151 A JP 2006542151A JP 5047625 B2 JP5047625 B2 JP 5047625B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- interlayer insulating
- ono
- insulating film
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 52
- 229910052698 phosphorus Inorganic materials 0.000 claims description 50
- 239000011574 phosphorus Substances 0.000 claims description 50
- 239000011229 interlayer Substances 0.000 claims description 46
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 24
- 239000010410 layer Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 230000015654 memory Effects 0.000 description 24
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 17
- 229910052796 boron Inorganic materials 0.000 description 17
- 238000000034 method Methods 0.000 description 13
- 230000007547 defect Effects 0.000 description 9
- 230000014759 maintenance of location Effects 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000002474 experimental method Methods 0.000 description 6
- 238000005247 gettering Methods 0.000 description 6
- 229910019001 CoSi Inorganic materials 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Formation Of Insulating Films (AREA)
Description
Claims (6)
- 半導体基板と、この上に形成されかつコンタクトホールが形成されたONO膜と、該ONO膜上に直接形成された層間絶縁膜とを有し、該層間絶縁膜はONO膜に接するPSGの第1の部分と、該第1の部分上に設けられたBPSGの第2の部分とを有し、前記第1の部分の膜厚は0.02μm以上であり、前記第1の部分は、前記ONO膜との界面部において、4.5wt%以上のリンを含む、半導体装置。
- 前記半導体装置は前記ONO膜上に形成されたゲート電極を有し、前記層間絶縁膜は前記ゲート電極上に直接形成されている請求項1に記載の半導体装置。
- 前記半導体装置は前記ONO膜上に形成されたゲート電極を有し、前記層間絶縁膜は前記ゲート電極の上部に形成されたシリサイド領域に接するように形成されている請求項1に記載の半導体装置。
- 前記層間絶縁膜の第1の部分は、前記ONO膜との界面部において、成膜後に4.5wt%以上かつ10.0wt%以下のリンを含む請求項1から3のいずれかに記載の半導体装置。
- 前記第1の部分のリン濃度は第2の部分のリン濃度以上である請求項1から3のいずれかに記載の半導体装置。
- 拡散領域が形成された半導体基板上にONO膜を形成するステップと、該ONO膜上にPSGの第1の部分と該第1の部分の上に設けられるBPSGの第2の部分とを有する層間絶縁膜を形成するステップと、前記層間絶縁膜及びONO膜にコンタクトホールを形成し、該コンタクトホールを介して前記拡散領域とコンタクトする金属配線層を前記層間絶縁膜上に形成するステップとを有し、前記第1の部分の膜厚は0.02μm以上であり、前記層間絶縁膜を形成するステップは、前記ONO膜との界面部において4.5wt%以上のリンを含むように前記層間絶縁膜の前記第1の部分を形成する、半導体装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2004/015774 WO2006046274A1 (ja) | 2004-10-25 | 2004-10-25 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2006046274A1 JPWO2006046274A1 (ja) | 2008-05-22 |
JP5047625B2 true JP5047625B2 (ja) | 2012-10-10 |
Family
ID=36227526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006542151A Expired - Fee Related JP5047625B2 (ja) | 2004-10-25 | 2004-10-25 | 半導体装置及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20060214218A1 (ja) |
JP (1) | JP5047625B2 (ja) |
CN (1) | CN101088155A (ja) |
DE (1) | DE112004003004T5 (ja) |
GB (1) | GB2434486A (ja) |
WO (1) | WO2006046274A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158289A (ja) * | 2005-11-11 | 2007-06-21 | Matsushita Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
DE202007001431U1 (de) * | 2007-01-31 | 2007-05-16 | Infineon Technologies Austria Ag | Halbleiteranordnung und Leistungshalbleiterbauelement |
JP2009049230A (ja) * | 2007-08-21 | 2009-03-05 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
US7691751B2 (en) * | 2007-10-26 | 2010-04-06 | Spansion Llc | Selective silicide formation using resist etchback |
US7951704B2 (en) * | 2008-05-06 | 2011-05-31 | Spansion Llc | Memory device peripheral interconnects and method of manufacturing |
US8669597B2 (en) * | 2008-05-06 | 2014-03-11 | Spansion Llc | Memory device interconnects and method of manufacturing |
JP2010010260A (ja) * | 2008-06-25 | 2010-01-14 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
JP2010272649A (ja) * | 2009-05-20 | 2010-12-02 | Panasonic Corp | 半導体装置及びその製造方法 |
CN102487057B (zh) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | 金属前介质层及其制造方法 |
CN103545227B (zh) * | 2012-07-10 | 2016-08-17 | 无锡华润上华科技有限公司 | 监控半导体器件中磷硅玻璃层的磷浓度的方法 |
JP6828449B2 (ja) * | 2017-01-17 | 2021-02-10 | 株式会社デンソー | 半導体装置およびその製造方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05291414A (ja) * | 1992-04-13 | 1993-11-05 | Ricoh Co Ltd | 半導体装置とその製造方法 |
JPH06232416A (ja) * | 1993-02-03 | 1994-08-19 | Rohm Co Ltd | 半導体記憶装置およびその製法 |
JPH0750396A (ja) * | 1993-08-06 | 1995-02-21 | Sony Corp | Nand型不揮発性半導体メモリ装置およびその製造方法 |
JPH07307339A (ja) * | 1994-04-12 | 1995-11-21 | Sgs Thomson Microelettronica Spa | 平坦化プロセス |
JPH08321502A (ja) * | 1995-03-22 | 1996-12-03 | Nippon Steel Corp | 半導体装置 |
JPH09213955A (ja) * | 1996-02-01 | 1997-08-15 | Hitachi Ltd | 半導体装置の製造方法 |
JPH1083972A (ja) * | 1996-09-06 | 1998-03-31 | Yamaha Corp | 低抵抗シリサイド層形成法 |
JP2002184717A (ja) * | 2000-10-02 | 2002-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004228351A (ja) * | 2003-01-23 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0280276B1 (en) * | 1987-02-27 | 1993-05-19 | Kabushiki Kaisha Toshiba | Ultraviolet erasable nonvolatile semiconductor memory device and manufacturing method therefor |
DE69028665T2 (de) * | 1989-07-18 | 1997-04-17 | Sony Corp., Tokio/Tokyo | Nichtflüchtige Halbleiterspeicheranordnung und Verfahren zur Herstellung |
US5338954A (en) * | 1991-10-31 | 1994-08-16 | Rohm Co., Ltd. | Semiconductor memory device having an insulating film and a trap film joined in a channel region |
US5672907A (en) * | 1995-03-22 | 1997-09-30 | Nippon Steel Corporation | Semiconductor device having character in BPSG film |
US6316349B1 (en) * | 1998-11-12 | 2001-11-13 | Hyundai Electronics Industries Co., Ltd. | Method for forming contacts of semiconductor devices |
US20020061639A1 (en) * | 2000-10-02 | 2002-05-23 | Kazuichiroh Itonaga | Semiconductor device and method for manufacturing the same |
KR100418091B1 (ko) * | 2001-06-29 | 2004-02-11 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US6977408B1 (en) * | 2003-06-30 | 2005-12-20 | Lattice Semiconductor Corp. | High-performance non-volatile memory device and fabrication process |
-
2004
- 2004-10-25 CN CNA2004800446661A patent/CN101088155A/zh active Pending
- 2004-10-25 JP JP2006542151A patent/JP5047625B2/ja not_active Expired - Fee Related
- 2004-10-25 DE DE112004003004T patent/DE112004003004T5/de not_active Ceased
- 2004-10-25 WO PCT/JP2004/015774 patent/WO2006046274A1/ja active Application Filing
-
2005
- 2005-10-25 US US11/258,823 patent/US20060214218A1/en not_active Abandoned
-
2007
- 2007-04-24 GB GB0707819A patent/GB2434486A/en not_active Withdrawn
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05291414A (ja) * | 1992-04-13 | 1993-11-05 | Ricoh Co Ltd | 半導体装置とその製造方法 |
JPH06232416A (ja) * | 1993-02-03 | 1994-08-19 | Rohm Co Ltd | 半導体記憶装置およびその製法 |
JPH0750396A (ja) * | 1993-08-06 | 1995-02-21 | Sony Corp | Nand型不揮発性半導体メモリ装置およびその製造方法 |
JPH07307339A (ja) * | 1994-04-12 | 1995-11-21 | Sgs Thomson Microelettronica Spa | 平坦化プロセス |
JPH08321502A (ja) * | 1995-03-22 | 1996-12-03 | Nippon Steel Corp | 半導体装置 |
JPH09213955A (ja) * | 1996-02-01 | 1997-08-15 | Hitachi Ltd | 半導体装置の製造方法 |
JPH1083972A (ja) * | 1996-09-06 | 1998-03-31 | Yamaha Corp | 低抵抗シリサイド層形成法 |
JP2002184717A (ja) * | 2000-10-02 | 2002-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004228351A (ja) * | 2003-01-23 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
GB2434486A (en) | 2007-07-25 |
CN101088155A (zh) | 2007-12-12 |
JPWO2006046274A1 (ja) | 2008-05-22 |
US20060214218A1 (en) | 2006-09-28 |
GB0707819D0 (en) | 2007-05-30 |
DE112004003004T5 (de) | 2007-10-25 |
WO2006046274A1 (ja) | 2006-05-04 |
GB2434486A8 (en) | 2007-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10957709B2 (en) | Systems including memory cells on opposing sides of a pillar | |
JP5288877B2 (ja) | 不揮発性半導体記憶装置 | |
US8564045B2 (en) | Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof | |
JP4989630B2 (ja) | Nandフラッシュメモリにおけるアレイソース線 | |
JP4482704B2 (ja) | Sonosフラッシュメモリにおける倍密度コアゲート | |
US20060214218A1 (en) | Semiconductor device and method of fabricating the same | |
US7465650B2 (en) | Methods of forming polysilicon-comprising plugs and methods of forming FLASH memory circuitry | |
JP2009164485A (ja) | 不揮発性半導体記憶装置 | |
KR101736246B1 (ko) | 비휘발성 메모리 소자 및 이의 제조방법 | |
US8952536B2 (en) | Semiconductor device and method of fabrication | |
JP3745297B2 (ja) | 不揮発性半導体記憶装置の製造方法 | |
JP2004056071A (ja) | 半導体素子の製造方法及びその素子 | |
JP5243237B2 (ja) | 半導体装置およびその製造方法 | |
KR20100138727A (ko) | 전하 축적층을 구비한 비휘발성 반도체 메모리 장치 및 그 제조 방법 | |
US7847340B2 (en) | Semiconductor device and method for manufacturing the same | |
JP4502802B2 (ja) | 不揮発性メモリー素子の製造方法 | |
KR100771553B1 (ko) | 전하트랩층을 갖는 매몰형 불휘발성 메모리소자 및 그제조방법 | |
KR20070055624A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2007067362A (ja) | 不揮発性半導体記憶装置の製造方法 | |
US7157335B1 (en) | Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100204 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100616 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100805 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20100922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110802 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110915 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120228 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120524 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120619 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120718 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150727 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150727 Year of fee payment: 3 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D02 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |