WO2006029957A1 - Ensemble circuit integre pourvu de trous d'interconnexion a deux sections et procede de fabrication - Google Patents

Ensemble circuit integre pourvu de trous d'interconnexion a deux sections et procede de fabrication Download PDF

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Publication number
WO2006029957A1
WO2006029957A1 PCT/EP2005/054184 EP2005054184W WO2006029957A1 WO 2006029957 A1 WO2006029957 A1 WO 2006029957A1 EP 2005054184 W EP2005054184 W EP 2005054184W WO 2006029957 A1 WO2006029957 A1 WO 2006029957A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive structure
integrated circuit
vertical
circuit arrangement
Prior art date
Application number
PCT/EP2005/054184
Other languages
German (de)
English (en)
Inventor
Klaus Goller
Jakob Kriz
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to US11/575,385 priority Critical patent/US8273658B2/en
Publication of WO2006029957A1 publication Critical patent/WO2006029957A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to an integrated circuit arrangement which contains a component layer in which a plurality of electronic components are arranged.
  • active electronic components are arranged in a semiconductor substrate.
  • the active components are arranged, for example, on an SOI substrate (Silicon On Insulator).
  • the integrated circuit also includes one of the component layers near the first conductive pattern.
  • This guide structure is, for example, part of a trackway layer in which many tracks are arranged. If the interconnects are produced by a damascene method, the baffles of a interconnect layer lie between the planar polishing surfaces of successive polishing steps. However, also produced by other manufacturing processes track layers are used.
  • the integrated circuit arrangement also includes a second conductive structure located farther away from the component layer than the first conductive pattern. Also, the second conductive structure is usually part of a track layer in which a plurality of interconnects is arranged, which has been produced simultaneously.
  • the integrated circuit arrangement also contains a vertical conductive structure, one end of which is arranged on the first conductive structure and whose other end is arranged on the second conductive structure.
  • the vertical conductive structures are referred to as contact, if the first conductive structure is arranged in a semiconductor substrate or consists of polycrystalline silicon. Passes the first lead structure whereas it is made of a metal, the vertical conductive structure is called a via.
  • the vertical conductive structure contains a first section, which is close to the first conductive structure, and a second section, which is near the second conductive structure, wherein the respective other section is referred to in the illustration of removal.
  • the first section of the vertical conductive structure is thus closer to the first conductive structure than the second section of the vertical conductive structure.
  • the invention is based on the consideration that due to the decreasing minimum structure width measures must be taken to enable a reliable filling of the vertical guide structure. In the invention, this is
  • the second section tapers with decreasing distance to the component layer and that the first section of the vertical guide structure does not taper or diminish with decreasing distance to the component layer than the second section of the vertical guide structure.
  • a small minimum structure width at the bottom of the vertical guide structure can be taken into account.
  • the vertical guide structure is widened so that filling, for example with a metal, is facilitated.
  • the guide structure can be filled with the aid of two metal deposits, wherein only the first metal deposition has a comparatively high deposition temperature.
  • the second deposition can be carried out at considerably lower deposition temperatures than the first deposition temperature.
  • the temperature required for filling the vertical conductive structure decreases. turbudget.
  • metal deposition at comparatively moderate temperatures offers the advantage that the grain size of the forming grains is comparatively small, so that structural edges are mapped in a conforming manner. This makes it possible, for example, to recognize alignment marks well.
  • the region there is an intermediate region, for example an edge, between the first section of the vertical guide structure and the second section of the vertical guide structure.
  • the region preferably lies at the boundary between the first section and the second section of the vertical conductive structure.
  • a dielectric layer which is referred to below as Hartmasken ⁇ layer.
  • the hard mask layer has another material composition as a dielectric layer that encloses the second portion of the vertical conductive structure.
  • the hard mask layer makes it possible to precisely define the position or length of the first section and the second section in the vertical direction.
  • the integrated circuit arrangement can fulfill narrow specifications, for example with regard to the transit time for the signal transmission in the conductive structures.
  • the hard mask layer makes it possible to produce the inventive vertical conductive structure with only one lithographic step.
  • the two sections are formed by using at least two different etching processes in a different manner, in particular with respect to the angle of inclination of the side walls.
  • the hard mask layer has a different material composition than a dielectric layer, which is arranged at a location of the vertical conductive structure which has the same distance to the region as to a side of the first conductive structure facing away from the component layer. This makes it possible to thinly extend the hard mask layer in comparison to the depth of the vertical conductive structure. After breaking the hard mask layer leaves Create a recess for the first portion of the vertical guide structure in a simple manner.
  • the upper, second section is seen in the vertical direction longer than the lower, first section, so that the lower section well with a "hot” deposition process and the upper section due to its long sloping sidewalls well with a " cold "deposition process can be filled.
  • the vertical guide structure has no further sections except for the first section and the second section. In spite of its division into two sections, the vertical guide structure is thus simple in construction and easy to manufacture.
  • the outline of all cross sections through the vertical guide structure in Ebe ⁇ NEN, which are parallel to the component layer, apart from the size of the outline is the same.
  • the outlines are along circles or squares.
  • the radius of the circles or the side length of the squares increases with increasing distance to the component layer, see, for example, FIG. 1, reference numeral 12.
  • the identical contour curves, apart from the size, are based on the use of only one lithograph ⁇ process for producing the vertical guide structure protest ⁇ out.
  • the first conductive structure has been produced using a different lithographic method than the vertical conductive structure. For this reason, the contours of both conductive structures also differ, and not only in terms of size. Also, the second conductive structure was made by a different lithographic process than the vertical guiding structure, so that here too the outlines do not differ only in terms of size.
  • the first guide structure contains at least 80 atomic percent copper. Copper offers a high current carrying capacity even with small minimum structural dimensions.
  • the vertical conductive structure and the second conductive structure contain at least 80 atomic percent aluminum. Aluminum has the advantage that it is easy to bond and therefore very well suited for the top metallization layer.
  • the first guide structure and the second guide structure are interconnects which serve for lateral current transport.
  • the vertical conductive structure is a via, which essentially serves for vertical current transport.
  • the invention also relates to a method for producing an integrated circuit arrangement, in particular the circuit arrangement according to the invention or one of its developments.
  • the above-mentioned technical effects also apply to the process.
  • FIG. 1 to 4 show production steps in the production of an integrated circuit arrangement.
  • FIGS. 1 to 4 show cross sections through the longitudinal axis of a vias to be produced in an integrated circuit arrangement 10.
  • a component layer 12 has already been produced, in which a multiplicity of active electronic semiconductor components are arranged, for example bipolar transistors, field effect transistors and / or diodes.
  • active electronic semiconductor components for example bipolar transistors, field effect transistors and / or diodes.
  • semiconductor material for example, single-crystal silicon is used.
  • the cross-sectional Level of the cross sections shown in Figures 1 to 4 is at an angle of 90 degrees to the component layer 12th
  • the interconnect layer 20 is the first metallization layer.
  • the interconnect layer 20 contains a plurality of interconnects, of which in FIG. 1 a interconnect 22 is shown.
  • the Leit ⁇ tracks of the interconnect layer 20 lie in a plane and are made of copper, which istientbet ⁇ tet in a sheath or liner layer, for example in a titanium nitride layer or a tantalum nitride layer.
  • a dielectric 24 is arranged, for example, silicon dioxide or a dielectric having a relative dielectric constant of less than 3.9.
  • the Leit ⁇ web layer 20 is prepared for example with a dual or with a single Damascene process.
  • a via layer 30 Adjacent to the interconnect layer 20, a via layer 30 is produced, the following layers being deposited in the following sequence: a barrier layer 32 having a layer thickness in the range of 50 nm to 100 nm, in the exemplary embodiment having a layer thickness of 50 nm,
  • the barrier layer 32 is made of an electrically non-conductive material, the one
  • Diffusion barrier for copper atoms is, for example, from Silizium ⁇ nitride.
  • the dielectric layer 34 consists, for example, of silicon dioxide or a metal oxide. material with a relative dielectric constant smaller than 3.9.
  • the layer thickness of the hard mask layer 36 is 100 nm.
  • the hard mask layer 36 consists of silicon nitride.
  • the hard mask layer 36 is made of silicon carbide or other non-conductive material.
  • the layer thickness of the dielectric layer 38 is, for example, 500 nm.
  • the dielectric layer 38 consists of silicon dioxide or a material having a relative dielectric constant of less than 3 , the ninth
  • the dielectric layer 34 is as thin as possible istschie ⁇ . However, the thickness of the dielectric layer 34 should be greater than the thickness of the hard mask layer 36, so that the dielectric layer 34 can be structured well with the aid of the hard mask layer 36.
  • a resist layer 40 which is patterned using a photolithographic process, is applied to this layer stack.
  • a recess 42 under which the via is to be generated.
  • the via to be generated becomes part of the via layer 30, in which there is a multiplicity of vias, all of which have the same structure.
  • an etch process 52 creates a recess 46 in the dielectric layer 38 having sloped sidewalls 48, 50.
  • the inclination of the side walls 48, 50 relative to, for example, the normal direction of the hardmask layer 36 is, for example, in the range between 10 degrees and 30 degrees.
  • the etching process 52 becomes performed so that the predetermined inclination angle W adjust.
  • the process parameters of the etching process are selected accordingly, in particular the plasma power, additional gases and the gas flows.
  • polymers are deposited on the side wall during the etching process, which minimally reduce the cross section. The equilibrium between sidewall deposition and etching propulsion into the depth ensures the angle of inclination. These polymers are removed during the paint removal residue-free in the contact hole.
  • the etching process 52 is carried out with a high selectivity to silicon nitride until the hard mask layer 36. Thereafter, for example, the hard mask layer 36 is time-etched with a second etching process, which is not shown in the figures, however.
  • the remainders of the resist layer 40 are then removed.
  • a third etching process 60 a recess 62 is produced for the lower section of the vias to be produced.
  • the third etching process 60 is strongly anisotropic, i. directed so that vertical 20 ⁇ walls 64 and 66 are generated in the recess 62 for the lower portion of the vias to be produced.
  • the hard mask layer 36 serves as a mask.
  • the dielectric layer 38 is thinned vertically.
  • the recess 46 is laterally expanded, so that side walls 48a and 50a arise, but which have the same angle of inclination W as the side walls 48 and 50, respectively.
  • portions 68 of the hardmask layer 36 are exposed.
  • the second etch process 60 is also performed with high selectivity to silicon nitride until the barrier layer 32 is reached. Subsequently, the barrier layer 32 is etched through in a time-controlled manner in a fourth etching process 70, for example
  • the dielectric layer 38 is further thinned.
  • the recess 46 is also widened further, so that side walls 48b and 50b are formed, which, however, have the same inclination angle W as the side walls 48 and 50, respectively.
  • a step 74 arises due to the etching process 70.
  • a funnel-shaped recess has been produced for the via to be produced.
  • a recess 72 for the upper via section has at its upper opening a diameter D1, which is considerably larger than a diameter D2 of the recess for the lower section 62b of the vias to be produced.
  • the diameter Dl is at least twice as large as the diameter D2.
  • a width Bl of the conductor track 22 is less than one micrometer in the embodiment.
  • a "hot" deposition process in which the lower section 62b is completely filled, is then first carried out after cleaning the via hole, on account of the funnel shape of the generated recesses.
  • a thin metal layer is deposited on the remaining surface of the circuit arrangement 10.
  • the diameter D2 is smaller than 0.5 ⁇ m.
  • a lower aluminum layer 82 is deposited, for example by means of a sputtering method.
  • the thickness of the lower aluminum layer 82 is, for example, 200 nm and is preferably in a range of less than 1 ⁇ m.
  • an aluminum-copper alloy is used, wherein the copper content is less than two atomic percent.
  • the deposition temperature ranges from 400 degrees Celsius to 440 degrees Celsius to ensure complete filling of the lower portion of the via 80.
  • the advantages of the via section with vertical sidewalls are used, ie the defined contact area, the void-free filling on a small contact area and the small aspect ratio, the is smaller than 1 in particular, so that the lower portion 62b is wider than higher.
  • the recess 72 for the upper section of the via 80 to be produced is filled completely or partially with a "cold" deposition process, wherein the alloy protrudes preferably beyond the via 80, preferably by at least 500 nanometers.
  • the same aluminum-copper alloy is used as before.
  • the deposition temperature is at least 50 degrees Celsius lower and is preferably in the range of 340 degrees Celsius to 360 degrees Celsius, especially 350 degrees Celsius.
  • the wafer supporting the integrated circuit device 10 is actively pre-cooled to the low temperature to reduce manufacturing time. Between the two
  • the thickness of the upper aluminum layer 84 is for example more than 2 micrometers, but is usually less than 5 micrometers.
  • the lower aluminum layer 82 and the upper aluminum layer 84 are then patterned by means of a further photolithographic step and an etching process, whereby a conductive track 92 is produced.
  • the interconnect 92 leads, for example, to a connection pad of the integrated circuit arrangement.
  • the connection pad is used, for example, for producing a bond connection or for producing a flip-chip connection.
  • An edge 94 is located at the location where the steeply inclined
  • FIG. 4 also shows a location Ol which lies in the center of the steeply inclined side wall 50b.
  • a location 02 lies in the middle of the vertical side wall 66.
  • the dielectric layer 38 adjoins the via 80.
  • the dielectric layer 34 adjoins the via 80.
  • the upper aluminum layer 84 is deposited with a smaller layer thickness than in the first exemplary embodiment, see dashed line 100.
  • dashed line 100 the recess 72 for the upper section of the via 80 is only partially filled.
  • dashed line 102 shows the upper limit of the vias 80. The position of the upper limit of the vias 80 coincides with the position of the component layer 12 facing side of the interconnect 92.
  • the sequence of "hot” and “cold” contact or vial filling can satisfy boundary conditions that exist with respect to the flank angle, with respect to the metal grain and with respect to the layer thickness.
  • the double profile of the contact hole or vial hole required for such a process control ie steep flanks for the hot deposition and comparatively flat flanks for the cold deposition, can be achieved without additional process steps with regard to a lithography or a plant change due to the use achieve an additional liner or an additional hard mask 36.
  • the additional hard mask layer 36 requires only one further deposition, which is carried out without effort and in the same plant but in a different chamber or even in the same chamber with modified process gases.
  • the dielectric layer 34 arranged below the hard-mask layer can be deposited with a precisely predetermined layer thickness, the layer thickness tolerance being, for example, less than ⁇ 3 percent.
  • the layer thickness of the dielectric layer 34 defines the vertical position or length of the lower portion of the vias 90 and thus indirectly the position or length of the upper portion of the vias 90 firmly.
  • narrow predetermined tolerances can be fulfilled for the process, in particular at different locations of an integrated circuit arrangement, at different locations of a wafer and also at circuit arrangements that have been produced on different wafers.
  • flank angle the lower via section must be produced with a "hot" deposition process, with values typical of aluminum being between 400 degrees Celsius and 450 degrees Celsius.
  • an angle W of the contact or via-hole flanks of less than or equal to 2 degrees results in a temperature of 440 degrees Celsius for the metal deposition in order to fill vacant space or void-free.
  • the goal is to have as steep as possible sidewalls of the contact hole in order to keep the area requirement low, i. high deposition temperatures are required.
  • Metal Grain As the temperature of the metal deposit increases, the granularity increases, which leads to an undesirable rough surface of the metal web. This in turn leads to several technical problems in the process. For example, the grain structures overlap with optical alignment marks, whose versatility is thereby limited. Lacquer residues on the aluminum layer can not be completely removed. In the subsequent etching these act
  • the aim is to keep the temperature of the metal deposition with regard to material graining low.
  • Layer thickness Another requirement is to have the lowest possible sheet resistance of the uppermost metal layer. Level to achieve, for example for Hochfrequenzanwen ⁇ applications as a coil level. Typical values for the thickness of the metal are 3 microns to 5 microns. As the layer thickness increases, the grain size of the aluminum increases sharply. For example, for a thickness of 3 micrometers, the deposition temperature must not exceed 330 degrees Celsius.
  • the upper metallization level can be produced by a process in which the vias are filled simultaneously with the deposition of conductive material, so that the via and the interconnect are made of the same material. After opening the via hole, the material deposition for the top metallization plane is used to fill these holes.
  • a small contact area D2 can be used, which is also associated with critical aspect ratios.
  • a small pitch of the lower metal level for example 280 nm, can be made.
  • the designed as a hard mask liner defines the contact surface safely. Since with the thickness of the aluminum metal, whose design rules are much more relaxed in the wiring area, the diameter of the upper opening D1 is uncritical and consequently does not restrict the minimum pitch of the upper metallization level.
  • an additional liner with the function of a hard mask is integrated. It is a combined contact or Vialoch specified that has defined adjustable flank angle. Furthermore, a "hot"
  • the procedures given are applicable to all metallizations.
  • the uppermost wiring level is connected to the underlying wiring level by means of the vias according to the invention in order to replace tungsten-filled vias.
  • the last copper plane is connected to an aluminum plane, which itself is a wiring plane.
  • the aluminum plane is electrically connected by means of the vias according to the invention to the underlying copper plane.
  • DRAM dynamic memories
  • NROM Non-Read On Memory
  • technologies for logic chips are NROM (Nitride Read On Memory) or technologies for logic chips.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne, entre autres, un ensemble circuit intégré (10), comportant un trou d'interconnexion (80). Ce trou d'interconnexion (80) présente une section supérieure (72) à parois latérales fortement inclinées. Une section inférieure (62b) du trou d'interconnexion (80) présente des parois latérales approximativement verticales. Une couche de revêtement (36) est utilisée comme masque dur lors de la formation du trou d'interconnexion (80) et détermine la position des sections (62b, 72) de ce trou d'interconnexion (80).
PCT/EP2005/054184 2004-09-15 2005-08-25 Ensemble circuit integre pourvu de trous d'interconnexion a deux sections et procede de fabrication WO2006029957A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/575,385 US8273658B2 (en) 2004-09-15 2005-08-25 Integrated circuit arrangement including vias having two sections, and method for producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004044686A DE102004044686B4 (de) 2004-09-15 2004-09-15 Integrierte Schaltungsanordnung mit Vias, die zwei Abschnitte haben, und Herstellungsverfahren
DE102004044686.5 2004-09-15

Publications (1)

Publication Number Publication Date
WO2006029957A1 true WO2006029957A1 (fr) 2006-03-23

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Family Applications (1)

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PCT/EP2005/054184 WO2006029957A1 (fr) 2004-09-15 2005-08-25 Ensemble circuit integre pourvu de trous d'interconnexion a deux sections et procede de fabrication

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US (1) US8273658B2 (fr)
DE (1) DE102004044686B4 (fr)
WO (1) WO2006029957A1 (fr)

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US7704869B2 (en) * 2007-09-11 2010-04-27 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
US7723851B2 (en) * 2007-09-11 2010-05-25 International Business Machines Corporation Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
WO2009033837A2 (fr) * 2007-09-11 2009-03-19 International Business Machines Corporation Procédé de fabrication de trous d'interconnexion ultra-profonds et circuits intégrés tridimensionnels utilisant des trous d'interconnexion ultra-profonds
US8232199B2 (en) * 2010-07-01 2012-07-31 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device comprises a photoresist pattern having a desired critical dimension
DE102010064289B4 (de) 2010-12-28 2019-06-19 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Größenreduzierung von Kontaktelementen und Kontaktdurchführungen in einem Halbleiterbauelement durch Einbau eines zusätzlichen Abschrägungsmaterials
CN108074861B (zh) * 2016-11-11 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其制造方法
US10276378B1 (en) * 2017-10-30 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming funnel-like opening for semiconductor device structure

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JPH0982664A (ja) * 1995-09-19 1997-03-28 Toshiba Corp 半導体装置の製造方法
US5933756A (en) * 1995-10-18 1999-08-03 Ricoh Company, Ltd. Fabrication process of a semiconductor device having a multilayered interconnection structure
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Publication number Publication date
DE102004044686A1 (de) 2006-03-16
US8273658B2 (en) 2012-09-25
DE102004044686B4 (de) 2006-08-31
US20080303169A1 (en) 2008-12-11

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