WO2005124862A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2005124862A1
WO2005124862A1 PCT/JP2005/005691 JP2005005691W WO2005124862A1 WO 2005124862 A1 WO2005124862 A1 WO 2005124862A1 JP 2005005691 W JP2005005691 W JP 2005005691W WO 2005124862 A1 WO2005124862 A1 WO 2005124862A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor element
insulating layer
support plate
main
control
Prior art date
Application number
PCT/JP2005/005691
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English (en)
French (fr)
Inventor
Takaaki Yokoyama
Original Assignee
Sanken Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co., Ltd. filed Critical Sanken Electric Co., Ltd.
Priority to US10/592,445 priority Critical patent/US7759697B2/en
Publication of WO2005124862A1 publication Critical patent/WO2005124862A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of favorably thermally and electrically separating a power semiconductor element and a control IC.
  • a semiconductor device in which a no-semiconductor element and its control IC are integrally packaged is known. Although not shown, this type of semiconductor device has a stacked structure in which a control IC is fixed on a power semiconductor element fixed on a support plate, and a power semiconductor element and a control IC arranged side by side on the support plate. There is an adjacent type structure that sticks.
  • a semiconductor device having a stacked structure is disclosed in Patent Document 1 below.
  • Patent Document 1 Patent No. 2,566,207, FIG. 4
  • the power semiconductor element Since the power semiconductor element generates a larger amount of heat than the control IC, heat generated by the power semiconductor element is transmitted to the control IC, and the control IC may be heated. For this reason, depending on the function of the control IC, it may be desirable to thermally separate the power semiconductor element and the control IC. In some cases, the power semiconductor element or the supporting plate force control IC to which the power semiconductor element is fixed is desired to be electrically insulated well.
  • An object of the present invention is to provide a semiconductor device that can thermally and electrically satisfactorily separate a power semiconductor element and a control IC.
  • the semiconductor device of the present invention comprises a support plate (1) having heat dissipation and conductivity, a main semiconductor element (2) fixed to one main surface of the support plate (1), and a sub semiconductor element ( 4). At least one of the main semiconductor element (2) and the slave semiconductor element (4) is fixed to one main surface of the support plate (1) via an insulating member (3), and the insulating member (3) is The insulating layer (3a) fixed to (1) and the heat insulating layer (3b) fixed between the insulating layer (3a) and the main semiconductor element (2) or the sub semiconductor element (4). Prepare.
  • the insulating member (3) makes it possible to thermally separate the main semiconductor element (2) and the sub-semiconductor element (4), and also to provide good electrical insulation.
  • a highly reliable semiconductor device capable of preventing electrical characteristics of a slave semiconductor element from deteriorating due to heat generated by a main semiconductor element and achieving good electrical insulation between the master semiconductor element and the slave semiconductor element. Can be provided.
  • FIG. 1 is a side view showing an embodiment of a semiconductor device of the present invention.
  • FIG. 2 is a cross-sectional view showing an embodiment of a method for manufacturing an insulating member.
  • FIG. 3 is a cross-sectional view showing an embodiment of another manufacturing method of the insulating member.
  • FIG. 4 is a side view of a semiconductor device according to another embodiment of the present invention.
  • the semiconductor device of the present invention comprises a support plate (1) having heat dissipation and conductivity, and an insulating member ( The control IC (2) as the main semiconductor element fixed via 3) is separated from the insulating member (3) by conductive adhesive or solder (5) on one main surface of the support plate (1).
  • a power switching semiconductor element for example, a MOSFET (4), which is fixed as a slave semiconductor element, is provided with a thin lead wire (6) for electrically connecting the control IC (2) and the MOSFET (4).
  • the support plate (1) is made of a metal having heat dissipation and conductivity, such as nickel-plated copper or aluminum, and the main electrode, that is, the drain electrode of the MOSFET (4) is electrically connected to the support plate (1). Is done.
  • the insulating member (3) includes a dielectric layer (3a) as an insulating layer fixed to the support plate (1), and a dielectric layer. It has a two-layer structure of a high heat transfer resistance heat insulating layer (3b) that is fixed to the dielectric layer (3a) and supports the control IC (2) between (3a) and the control IC (2). .
  • the dielectric layer (3a) is made of a dielectric film such as polyimide resin (Kapton film) having a relatively low bubble content or no bubbles or pinholes, and has an adhesive property of itself. Is bonded to the support plate (1).
  • the dielectric layer (3a) which contains little or no bubbles, has good insulating properties.
  • An adhesive tape may be provided below the dielectric layer (3a), and the dielectric layer (3a) may be bonded to the support plate (1) via the adhesive tape.
  • the control IC (2) is fixed to the heat insulating layer (3b) by the adhesive (13) arranged between the heat insulating layer (3b) and the control IC (2).
  • the heat insulating layer (3b) itself may be provided with adhesiveness, and the adhesive (13) may be omitted.
  • the heat insulating layer (3b) is formed of a dielectric film having relatively many bubbles or a foamed resin such as a polyimide foam.
  • the insulating layer (3b) may be formed using a tape containing air bubbles fixed to the dielectric layer (3a) .
  • the insulating layer (3b) may be formed of the same polyimide resin or a different material as the dielectric layer (3a). 3b) may be formed. If the dielectric layer (3a) and the heat insulating layer (3b) are formed by a tape member forming an adhesive surface on the upper surface and the lower surface, the support plate (3 1)
  • the control IC can be easily, firmly and quickly fixed. Alternatively, the dielectric layer (3a) and the heat insulating layer (3b) may be bonded together to form a chip-shaped insulating member (3).
  • the MOSFET (4) Since the heat transfer resistance of the heat insulating layer (3b) containing bubbles is higher than that of the dielectric layer (3a) substantially containing no bubbles, the MOSFET (4) is The transmission of heat generation to the control IC (2) can be prevented. Similarly to the heat insulating layer (3b), if the dielectric layer (3a) is formed of a resin material containing bubbles (3c), the heat transfer resistance of the coating (7) further increases, but at the same time, the insulating member (3 ) The overall electrical insulation is reduced, and the electrical isolation between the support plate (1) and the control IC (2) cannot be satisfactorily achieved. Therefore, it is important that the thermal resistance of the heat insulating layer (3b) is higher than the thermal resistance of the dielectric layer (3a).
  • Fig. 2 shows a pressure-sensitive adhesive resin tape (11) serving as a dielectric layer (3a) and a wavy resin (12) serving as a heat insulating layer (3b) pressed against the resin (12).
  • 1 shows a first method of manufacturing an insulating member (3) in which voids forming bubbles (3c) are formed at regular intervals between a resin and a resin tape (11).
  • Figure 3 shows the resin (11) that does not contain a foaming agent that forms the dielectric layer (3a) and the resin (12) that contains the foaming agent that forms the heat insulating layer (3b) is formed by caro-thermal bonding.
  • a second manufacturing method of the insulating member (3) will be described. The foaming agent in the fat (12) is heated Expands to form bubbles (3c).
  • An electrode (not shown) of the control IC (2) and a source electrode (not shown) of the MOSFET (4) are connected to a plurality of lead terminals (not shown) provided around the support plate (1).
  • the lead terminal connected to the support plate (1) serves as a path for the current flowing through the support plate (1), that is, the main current (drain current) of the MOSFET (4).
  • One end of the lead wire (6) is fixed to the electrode (not shown) on the control IC (2) by wire bonding, and the other end of the lead wire (6) is fixed to the gate electrode (not shown) on the MOSFET (4).
  • the MOSFET (4) repeats the on-off operation and controls the operation of the MOSFET (4) by the drive signal of the control IC (2). Can be done.
  • the MOSFET (4) is turned on, a drain current flows through the support plate (1) and the lead terminal, and the heat generated by the MOSFET (4) can be efficiently released from the support plate (1) via the solder (5). As a result, sufficient heat dissipation can be ensured and a large current can flow through the MOSFET (4).
  • the insulating member (3) blocks the heat of the MOSFET (4) and does not transmit it to the control IC (2).
  • the MOSFET (4) and the control IC (2) are completely electrically insulated by the dielectric layer (3a), an electrical short circuit between the MOSFET (4) and the control IC (2) occurs. Can be prevented.
  • the insulating member (3) has a function of fixing the support plate (1) and the control IC (2), a function of thermally separating the MOSF ET (4) and the control IC (2), and a function of the MOSFET (4). And has a function of electrically separating the control IC (2) from the control IC (2).
  • control IC (2) is sufficiently protected against heat generated from the MOSFET (4) by the insulating member (3), and the external force applied to the control IC (2) is flexible or cushioned. It can be alleviated by the insulating member (3) having the structure, and damage to the control IC (2) can be avoided.
  • FIG. 1 shows an example in which the present invention is applied to an adjacent structure in which a MOSFET (4) and a control IC (2) are juxtaposed and fixed on a support plate (1).
  • a semiconductor device is applied to a stacked structure in which a control IC (2) is fixed on a MOSFET (4) fixed on a support plate (1) via an insulating member (3).
  • the MOSFET (4) is fixed to one main surface of the support plate (1) with a conductive adhesive or solder (5), and the one main surface of the MOSFET (4) is interposed with an insulating member (3).
  • the electrodes of the control IC (2) and the electrodes of the MOSFET (4) are electrically connected by thin lead wires (6), and the support plate (1) is an external lead provided around the support plate (1) (7) (7a), and a current flows between the support plate (1) and the external lead (7a).
  • Other electrodes of the control IC (2) are electrically connected to a plurality of external leads (7b) arranged around the support plate (1) by lead wires (8).
  • the insulating member (3) includes a dielectric layer (3a) as an insulating layer fixed to one main surface of the MOSFET (4), and a dielectric layer (3a) and the control IC (2). And has a two-layer structure with a heat insulating layer (3b) having high heat transfer resistance and fixed to the dielectric layer (3a) and supporting the control IC (2).
  • the dielectric layer (3a) is made of a dielectric film such as polyimide resin (capton film) having a relatively low bubble content or having no bubbles or pinholes, and is supported by its own adhesiveness. Glued to board (1).
  • the dielectric layer (3a) which contains little or no bubbles, has good insulating properties.
  • the heat insulating layer (3b) is formed of a dielectric film having relatively many bubbles or a foamed resin such as a polyimide foam, and does not transmit heat to the control IC (2) by cutting off the heat of the MOSFET (4). .
  • the present invention is suitable for implementation in a semiconductor device including a power semiconductor element through which a relatively large current flows, and a control element that controls the power semiconductor element.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

　半導体装置内の半導体素子を周辺の熱環境から保護する。放熱性及び導電性を有する支持板(1)と、支持板(1)の一方の主面に絶縁部材(3)を介して固着された主半導体素子(2)とを半導体装置に設ける。絶縁部材(3)は、支持板(1)に固着された絶縁層(3a)と、絶縁層(3a)と主半導体素子(2)との間に固着された断熱層(3b)とを備え、主半導体素子(2)を周辺の熱環境から十分に保護する。

Description

明 細 書
半導体装置
技術分野
[0001] 本発明は、半導体装置、特にパワー半導体素子と制御 ICとを熱的、電気的に良好 に分離することができる半導体装置に関連する。
背景技術
[0002] ノ^ー半導体素子とその制御 ICとを一体にパッケージした半導体装置は公知であ る。図示しないが、この種の半導体装置は、支持板上に固着されたパワー半導体素 子の上に制御 ICを固着する積層型構造と、支持板上にパワー半導体素子と制御 IC とを並置して固着する隣接型構造とがある。例えば、積層型構造の半導体デバイス は、下記特許文献 1に示される。
[0003] 特許文献 1 :特許第 2,566,207号公報、第 4図
発明の開示
発明が解決しょうとする課題
[0004] パワー半導体素子は制御 ICに比較して発熱量が大きいため、パワー半導体素子 の発熱が制御 ICに伝わり、制御 ICが加熱されることがある。このため、制御 ICの機能 によっては、パワー半導体素子と制御 ICとを熱的に分離することが望ましい場合があ る。また、パワー半導体素子又はパワー半導体素子が固着された支持板力 制御 IC を良好に電気的に絶縁したい場合がある。
本発明は、パワー半導体素子と制御 ICとを熱的、電気的に良好に分離することが できる半導体装置を提供することを目的とする。
課題を解決するための手段
[0005] 本発明の半導体装置は、放熱性及び導電性を有する支持板 (1)と、支持板 (1)の一 方の主面に固着された主半導体素子 (2)及び従半導体素子 (4)とを備えている。主半 導体素子 (2)と従半導体素子 (4)の少なくとも一方は、支持板 (1)の一方の主面に絶縁 部材 (3)を介して固着され、絶縁部材 (3)は、支持板 (1)に固着された絶縁層 (3a)と、絶 縁層 (3a)と主半導体素子 (2)又は従半導体素子 (4)との間に固着された断熱層 (3b)とを 備える。絶縁部材 (3)により主半導体素子 (2)と従半導体素子 (4)とを熱的に分離でき ると共に、電気的に良好に絶縁することができる。
発明の効果
[0006] 主半導体素子の発熱によって従半導体素子の電気的特性が劣化することを防止し 、且つ主半導体素子と従半導体素子との電気的絶縁を良好に達成できる信頼性の 高 、半導体装置を提供することができる。
図面の簡単な説明
[0007] [図 1]本発明の半導体装置の実施の形態を示す側面図
[図 2]絶縁部材の製造法の実施の形態を示す断面図
[図 3]絶縁部材の他の製造法の実施の形態を示す断面図
[図 4]本発明の他の実施の形態による半導体装置の側面図
[図 5]図 4の平面図
符号の説明
[0008] (1)· ·支持板、 （2)· ·主半導体素子 (制御 IC)、 （3)· ·絶縁部材、 （3a)' ·誘電体層 、 （3b)' '断熱層、 （4)· ·従半導体素子 (MOSFET)、 （6)· ·リード細線、 発明を実施するための最良の形態
[0009] スイッチングレギユレータに使用されるパワー半導体装置に適用した本発明による 半導体装置の実施の形態を図 1一図 3について以下説明する。
[0010] 図 1に示す本発明の実施の形態では、本発明の半導体装置は、放熱性及び導電 性を有する支持板 (1)と、支持板 (1)の一方の主面に絶縁部材 (3)を介して固着された 主半導体素子としての制御 IC(2)と、支持板 (1)の一方の主面に導電性の接着剤又は 半田 (5)により絶縁部材 (3)から離間して固着された従半導体素子としてのパワースィ ツチング半導体素子、例えば MOSFET(4)と、制御 IC(2)と MOSFET(4)とを電気的 に接続するリード細線 (6)とを備えている。支持板 (1)は、ニッケルメツキされた銅又は アルミニウム等の放熱性及び導電性を有する金属により形成され、 MOSFET(4)の 主電極、即ちドレイン電極が支持板 (1)に電気的に接続される。
[0011] 絶縁部材 (3)は、支持板 (1)に固着された絶縁層としての誘電体層 (3a)と、誘電体層 (3a)と制御 IC(2)との間で誘電体層 (3a)に固着されて制御 IC(2)を支持する高伝熱抵 抗性の断熱層 (3b)との二層構造を有する。誘電体層 (3a)は、気泡の含有率が相対的 に少な!/、か又は気泡又はピンホールのな 、ポリイミド榭脂（カプトンフィルム）等の誘 電体膜から成り、それ自体の接着性で支持板 (1)に接着される。気泡を含まないか殆 ど含まない誘電体層 (3a)は、良好な絶縁特性を有する。誘電体層 (3a)の下側に接着 テープを設け、接着テープを介して支持板 (1)に誘電体層 (3a)を接着する構造にして も良い。何れにしても、制御 IC(2)は、断熱層 (3b)と制御 IC(2)との間に配置された接 着剤 (13)により断熱層 (3b)に固着される。断熱層 (3b)自体に接着性を持たせて、接着 剤 (13)を省略することもできる。
[0012] 断熱層 (3b)は、相対的に気泡の多い誘電体膜又はポリイミド発泡体等の発泡榭脂 により形成される。誘電体層 (3a)に固着された気泡を含むテープ剤を使用して断熱層 (3b)を形成してもよぐ誘電体層 (3a)と同一のポリイミド榭脂又は異なる材料で断熱層 (3b)を形成してもよい。上面と下面とに粘着面を形成するテープ部材により誘電体層 (3a)と断熱層 (3b)とを構成すれば、誘電体層 (3a)と断熱層 (3b)とを介して支持板 (1)に 制御 ICを容易に、強固に且つ迅速に固着することができる。別法として、誘電体層 (3a)と断熱層 (3b)とを張り合わせて、チップ状に絶縁部材 (3)を形成してもよ 、。
[0013] 気泡を含む断熱層 (3b)の伝熱抵抗は、気泡を実質的に含まない誘電体層 (3a)の伝 熱抵抗より大きいため、誘電体層 (3a)によって MOSFET(4)の発熱の制御 IC(2)への 伝達を防止できる。断熱層 (3b)と同様に、誘電体層 (3a)も気泡 (3c)を含む榭脂材料で 形成すれば、被覆体 (7)の伝熱抵抗は更に増加するが、同時に絶縁部材 (3)全体の 電気絶縁性が低下し、支持板 (1)と制御 IC(2)との電気的分離を良好に達成できな 、 。従って、断熱層 (3b)の熱抵抗は誘電体層 (3a)の熱抵抗よりも大きいことが重要であ る。
[0014] 図 2は、誘電体層 (3a)となる接着性の榭脂テープ (11)上に断熱層 (3b)となる波状の 榭脂 (12)を圧接して、榭脂 (12)と榭脂テープ (11)との間に気泡 (3c)となるボイドを一定 間隔で形成する絶縁部材 (3)の第 1の製法を示す。図 3は、誘電体層 (3a)となる発泡 剤を含有しない榭脂 (11)に対して断熱層 (3b)となる発泡剤を含有する榭脂 (12)とをカロ 熱接合して形成する絶縁部材 (3)の第 2の製法を示す。榭脂 (12)中の発泡剤は、加熱 により膨張して気泡 (3c)を形成する。
[0015] 制御 IC(2)の図示しない電極及び MOSFET(4)の図示しないソース電極は、支持 板 (1)の周辺に設けられた図示しない複数のリード端子に接続される。支持板 (1)に連 結して形成されるリード端子は、支持板 (1)に流れる電流、即ち MOSFET(4)の主電 流（ドレイン電流）の通路となる。ワイヤボンディングにより、制御 IC(2)上の図示しない 電極にリード細線 (6)の一端を固着し、 MOSFET(4)上の図示しないゲート電極にリ 一ド細線 (6)の他端を固着して、上方空間 (14)を通じてリード細線 (6)を制御 IC(2)と M OSFET(4)との間に橋絡させれば、動作の際に、リード細線 (6)を通じて制御 IC(2)の 駆動パルスを MOSFET(4)のゲート電極に付与すると、 MOSFET(4)は、オン'オフ 動作を反復して、制御 IC(2)の駆動信号により MOSFET(4)の動作を制御することが できる。 MOSFET(4)のオン時に支持板 (1)とリード端子とを通じてドレイン電流が流 れて、 MOSFET(4)力もの熱を半田 (5)を介して支持板 (1)から効率よく放出できるの で、十分な放熱性を確保して、 MOSFET(4)に大きな電流を流すことができる。 MO SFET(4)の放熱量が増加しても、絶縁部材 (3)は、 MOSFET(4)の熱を遮断して制御 IC(2)には伝達させない。また、 MOSFET(4)と制御 IC(2)とを誘電体層 (3a)によって 完全に電気的に絶縁するので、 MOSFET(4)と制御 IC(2)との間での電気的短絡事 故を防止できる。絶縁部材 (3)は、支持板 (1)と制御 IC(2)とを固着する作用と、 MOSF ET(4)と制御 IC(2)とを熱的に分離する作用と、 MOSFET(4)と制御 IC(2)とを電気的 に分離する作用とを有する。本実施の形態では、 MOSFET(4)からの発熱に対して 制御 IC(2)を絶縁部材 (3)により十分に保護すると共に、制御 IC(2)に加えられる外力 を可撓性又はクッション性のある絶縁部材 (3)により緩和して、制御 IC(2)の損傷を回 避することができる。
[0016] 図 1では、支持板 (1)上に MOSFET(4)と制御 IC(2)とを並置して固着する隣接型構 造に本発明を適用する例を示したが、図 4及び図 5に示すように、支持板 (1)上に固 着した MOSFET(4)上に絶縁部材 (3)を介して制御 IC(2)を固着する積層型構造に適 用して、半導体装置の高密度化を図り、平面占有面積を減少することもできる。この 場合、導電性の接着剤又は半田 (5)により MOSFET(4)を支持板 (1)の一方の主面に 固着し、 MOSFET(4)の一方の主面に絶縁部材 (3)を介して制御 IC(2)を固着する。 制御 IC(2)の電極と MOSFET(4)の電極とはリード細線 (6)により電気的に接続され、 支持板 (1)は、支持板 (1)の周辺に設けられる外部リード (7)の一つ (7a)に接続され、支 持板 (1)と外部リード (7a)との間で電流が流れる。制御 IC(2)の他の電極は、リード細線 (8)により支持板 (1)の周囲に配置された複数の外部リード (7b)に電気的に接続される
[0017] 絶縁部材 (3)は、 MOSFET(4)の一方の主面に固着された絶縁層としての誘電体 層 (3a)と、誘電体層 (3a)と制御 IC(2)との間で誘電体層 (3a)に固着されて制御 IC(2)を 支持する高伝熱抵抗性の断熱層 (3b)との二層構造を有する。誘電体層 (3a)は、気泡 の含有率が相対的に少な 、か又は気泡又はピンホールのな 、ポリイミド榭脂 (カプト ンフィルム)等の誘電体膜から成り、それ自体の接着性で支持板 (1)に接着される。気 泡を含まないか殆ど含まない誘電体層 (3a)は、良好な絶縁特性を有する。断熱層 (3b)は、相対的に気泡の多い誘電体膜又はポリイミド発泡体等の発泡榭脂により形 成され、 MOSFET(4)の熱を遮断して制御 IC(2)に伝達させな 、。
産業上の利用可能性
[0018] 本発明は、比較的な大きな電流が流れるパワー半導体素子と、パワー半導体素子 を制御する制御素子とを備えた半導体装置への実施に適する。

Claims

請求の範囲
[1] 放熱性及び導電性を有する支持板と、該支持板の一方の主面に固着された主半 導体素子及び従半導体素子とを備え、
前記主半導体素子と前記従半導体素子の少なくとも一方は、前記支持板の一方の 主面に絶縁部材を介して固着され、
前記絶縁部材は、前記支持板に固着された絶縁層と、該絶縁層と前記主半導体素 子又は前記従半導体素子との間に固着された断熱層とを備えることを特徴とする半 導体装置。
[2] 放熱性及び導電性を有する支持板と、該支持板の一方の主面に固着された従半 導体素子と、該従半導体素子の一方の主面に絶縁部材を介して固着された主半導 体素子とを備え、
前記絶縁部材は、前記従半導体素子の一方の主面に固着された絶縁層と、該絶 縁層と前記主半導体素子との間に固着された断熱層とを備えることを特徴とする半 導体装置。
[3] 前記絶縁層は、気泡の含有率が相対的に少ない誘電体膜から成り、前記断熱層 は、相対的に気泡の多い誘電体膜から成る請求項 1又は 2に記載の半導体装置。
[4] 前記主半導体素子と従半導体素子との間に形成された上方空間を通じてワイヤボ ンデイングされたリード細線により前記主半導体素子と従半導体素子とを接続し、前 記主半導体素子の駆動信号により前記従半導体素子の動作を制御する請求項 1乃 至 3の何れか 1項に記載の半導体装置。
[5] 前記主半導体素子は制御 ICであり、前記従半導体素子はパワ-半導体素子である 請求項 1乃至 4の何れか 1項に記載の半導体装置。
PCT/JP2005/005691 2004-06-18 2005-03-28 半導体装置 WO2005124862A1 (ja)

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WO2013124940A1 (ja) * 2012-02-23 2013-08-29 パナソニック株式会社 樹脂封止型半導体装置及びその製造方法
JP2015056646A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置及び半導体モジュール
DE112017008253T5 (de) * 2017-12-05 2020-08-13 Hamamatsu Photonics K.K. Reflektierender räumlicher lichtmodulator, optische beobachtungsvorrichtung und lichtbestrahlungsvorrichtung
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