WO2005034592A1 - 積層セラミックス基板及びその製造方法 - Google Patents
積層セラミックス基板及びその製造方法 Download PDFInfo
- Publication number
- WO2005034592A1 WO2005034592A1 PCT/JP2004/014551 JP2004014551W WO2005034592A1 WO 2005034592 A1 WO2005034592 A1 WO 2005034592A1 JP 2004014551 W JP2004014551 W JP 2004014551W WO 2005034592 A1 WO2005034592 A1 WO 2005034592A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ceramic substrate
- side electrode
- green sheet
- hole
- multilayer ceramic
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24777—Edge feature
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/541,494 US7440256B2 (en) | 2003-10-06 | 2004-09-27 | Laminated ceramic substrate and manufacturing method therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003347435A JP4131694B2 (ja) | 2003-10-06 | 2003-10-06 | 積層セラミックス基板及びその製造方法 |
JP2003-347435 | 2003-10-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005034592A1 true WO2005034592A1 (ja) | 2005-04-14 |
Family
ID=34419581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/014551 WO2005034592A1 (ja) | 2003-10-06 | 2004-09-27 | 積層セラミックス基板及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7440256B2 (ja) |
JP (1) | JP4131694B2 (ja) |
KR (1) | KR20070000967A (ja) |
CN (1) | CN100542376C (ja) |
WO (1) | WO2005034592A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9713258B2 (en) * | 2006-04-27 | 2017-07-18 | International Business Machines Corporation | Integrated circuit chip packaging |
KR101478810B1 (ko) | 2006-07-28 | 2015-01-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 축전 장치 |
US7838976B2 (en) * | 2006-07-28 | 2010-11-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a semiconductor chip enclosed by a body structure and a base |
US8232621B2 (en) * | 2006-07-28 | 2012-07-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
WO2009028289A1 (ja) | 2007-08-29 | 2009-03-05 | Murata Manufacturing Co., Ltd. | セラミック多層基板 |
DE102010018499A1 (de) * | 2010-04-22 | 2011-10-27 | Schweizer Electronic Ag | Leiterplatte mit Hohlraum |
KR102520038B1 (ko) | 2018-01-10 | 2023-04-12 | 삼성전자주식회사 | 가스 센서 패키지 및 이를 포함하는 센싱 장치 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0385793A (ja) * | 1989-08-30 | 1991-04-10 | Murata Mfg Co Ltd | 厚膜配線板の外部端子形成方法 |
JPH0983090A (ja) * | 1995-09-19 | 1997-03-28 | Murata Mfg Co Ltd | 電子部品 |
JP2003017851A (ja) * | 2001-06-29 | 2003-01-17 | Murata Mfg Co Ltd | 多層セラミック基板の製造方法 |
JP2003258398A (ja) * | 2002-02-27 | 2003-09-12 | Murata Mfg Co Ltd | 積層セラミック電子部品およびその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3612963A (en) * | 1970-03-11 | 1971-10-12 | Union Carbide Corp | Multilayer ceramic capacitor and process |
US4821007A (en) * | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
US4907128A (en) * | 1988-12-15 | 1990-03-06 | Grumman Aerospace Corporation | Chip to multilevel circuit board bonding |
US5140745A (en) * | 1990-07-23 | 1992-08-25 | Mckenzie Jr Joseph A | Method for forming traces on side edges of printed circuit boards and devices formed thereby |
JPH04221888A (ja) * | 1990-12-21 | 1992-08-12 | Matsushita Electric Ind Co Ltd | セラミック配線基板とその製造方法 |
US5258648A (en) * | 1991-06-27 | 1993-11-02 | Motorola, Inc. | Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery |
JP3223199B2 (ja) * | 1991-10-25 | 2001-10-29 | ティーディーケイ株式会社 | 多層セラミック部品の製造方法および多層セラミック部品 |
US5621193A (en) * | 1995-05-23 | 1997-04-15 | Northrop Grumman Corporation | Ceramic edge connect process |
JP3336913B2 (ja) | 1997-06-30 | 2002-10-21 | 株式会社村田製作所 | 電子部品のパッケージ構造 |
US6760227B2 (en) * | 2000-11-02 | 2004-07-06 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component and manufacturing method thereof |
JP2002232135A (ja) | 2001-01-30 | 2002-08-16 | Matsushita Electric Ind Co Ltd | 積層用両面回路基板とその製造方法及びそれを用いた多層プリント配線板 |
US6958899B2 (en) * | 2003-03-20 | 2005-10-25 | Tdk Corporation | Electronic device |
-
2003
- 2003-10-06 JP JP2003347435A patent/JP4131694B2/ja not_active Expired - Fee Related
-
2004
- 2004-09-27 KR KR1020057017438A patent/KR20070000967A/ko active IP Right Grant
- 2004-09-27 CN CNB2004800014600A patent/CN100542376C/zh not_active Expired - Fee Related
- 2004-09-27 US US10/541,494 patent/US7440256B2/en not_active Expired - Fee Related
- 2004-09-27 WO PCT/JP2004/014551 patent/WO2005034592A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0385793A (ja) * | 1989-08-30 | 1991-04-10 | Murata Mfg Co Ltd | 厚膜配線板の外部端子形成方法 |
JPH0983090A (ja) * | 1995-09-19 | 1997-03-28 | Murata Mfg Co Ltd | 電子部品 |
JP2003017851A (ja) * | 2001-06-29 | 2003-01-17 | Murata Mfg Co Ltd | 多層セラミック基板の製造方法 |
JP2003258398A (ja) * | 2002-02-27 | 2003-09-12 | Murata Mfg Co Ltd | 積層セラミック電子部品およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7440256B2 (en) | 2008-10-21 |
KR20070000967A (ko) | 2007-01-03 |
JP4131694B2 (ja) | 2008-08-13 |
CN100542376C (zh) | 2009-09-16 |
US20060115637A1 (en) | 2006-06-01 |
CN1717962A (zh) | 2006-01-04 |
JP2005116707A (ja) | 2005-04-28 |
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