Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
  • H01L21/743—Making of internal connections, substrate contacts
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5226—Via connections in a multilevel interconnection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance

Definitions

• the present invention relates generally to semiconductor memories and more specifically to controlling of wordline signals.
• Microprocessors are used in many applications including personal computers and other electronic systems.
• a goal of any microprocessor is to process information quickly.
• One problem has been the communication rate between a microprocessor and main memory.
• the instructions to be executed by the microprocessor and the data on which operations implemented by the instructions are to be performed are stored at addresses within main memory.
• the microprocessor transmits addresses to main memory.
• the main memory decodes the address and makes the contents at the requested address available for reading and/or writing.
• the time required for the microprocessor to transmit an address to main memory and receive the respective contents therefrom can significantly constrain system performance.
• a cache memory is a small, fast memory that keeps copies of recently used data or instructions. When these items are reused, they can be accessed from the cache memory instead of main memory. Instead of operating at slower main memory access speeds, the microprocessor can operate at faster cache memory access speeds most of the time.
• microprocessors have come to include more than one cache memory on the same semiconductor substrate as the microprocessor.
• the most commonly used cache memories use static random access memory (SRAM) circuitry, which provide high densities using wordlines and bitlines to access SRAM memory cells.
• SRAM static random access memory
• SRAM circuitry requires minimal cell and read/write circuit architectures.
• a memory cell is accessed by enabling a row wordline wire and enabling a selected column-gating transistor to read the value from the memory cell.
• the use of memory circuits in battery-operated and other low-voltage devices make it desirable to operate the memory circuits at lowest voltage possible.
• the wordline is set high with the power applied while the information stored in the memory cells is read by being transferred onto bitlines or information on the bitlines is written by being stored in the memory cells. For read operations, bitlines are then read by a sense-amplifier, or sense-amp.
• Sense-amps are common to all memories whether the memories are dynamic, static, Flash, or other types of memories. For write operations, information on the bitlines change the held charge in the memory cell. While the wordline is kept on, power is being consumed. The wordline remains on during and after the desired operation, whether it is a read or a write, to ensure the operation is complete; i.e., power is consumed even when no longer required. Reading reliable results from memory circuits operating at a low-power supply voltage is complicated by the large capacitance of the wordlines and the threshold drop produced by the gating transistor. Low-power supply voltages reduce memory speed, and at very low voltages, the reliability of the information drops.
• boost circuits provide reliable memory operation at low voltages.
• One of the problems with boost circuits is that at high voltages, the access circuitry is over-stressed. This limits the upper end of the power supply operating range of a memory device.
• Another problem is that boosting increases the power consumption of a memory circuit. At high supply voltages, the power dissipation can exceed tolerable levels and the memory circuitry is subject to failures due to overheating. Power saving has been a persistent need.
• the present invention provides a memory system, and method of operation therefor, having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals.
• a decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell.
• Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.
• FIG. 1 is a block diagram of an SRAM in accordance with the present invention
• FIG. 2 is a timing diagram showing operative signals in accordance with the present invention
• FIG. 3 is a schematic diagram of a memory circuit in accordance with the present invention
• FIG. 4 is a timing diagram of a read-only operation in accordance with the present invention
• FIG. 5 is a timing diagram of the read- write operation in accordance with the present invention.
• BEST MODE FOR CARRYING OUT THE INVENTION Referring now to FIG. 1, therein is shown a block diagram of an SRAM 100, with core regions typically including one or more M x N arrays 104 of individually addressable, substantially identical memory cells.
• Peripheral portions typically include input/output (I/O) circuitry and programming circuitry for selectively addressing the individual memory cells in accordance with the present invention.
• the cell access circuitry is represented in part by and includes one or more x-decoders 108 and y-decoders 110, cooperating with I/O circuitry 106 for connecting the source, gate, and drain of selected addressed memory cells to predetermined voltages or impedances to effect designated operations on the memory cell, e.g., programming, writing, reading, erasing, and deriving necessary voltages to effect such operations.
• FIG. 2 therein is shown is shown is a timing diagram 300 having a vertical voltage axis and a horizontal time axis.
• a clock signal 310 and two wordline signals 312 and 314 are shown in accordance with the present invention.
• the clock signal 310 is cyclic and a full cycle and part of a subsequent cycle are shown.
• the clock signal 310 also has two phases: Phase A and Phase B measured from about the middle of the rise and fall times such that the clock signal 310 is going high to a digital one in the beginning of Phase A, low to a digital zero in the beginning of Phase B, and high to a digital one in the beginning of the next subsequent phase.
• the wordline signal 312 shows the duration during which a wordline signal remains at a high voltage, or high, on a wordline for a read-only operation.
• the wordline signal 314 shows the duration during which a wordline signal remains latched high on a wordline for a read-write operation to respectively read data in and write data to a memory cell.
• a time delay 316 is shown because the wordline signals 312 and 314 are triggered by the beginning of the clock signal 310 but are delayed in reaching the wordlines because of decoding and other processes required before the wordline signals 312 and 314 can be imposed on the wordlines.
• the various signals overlap at various times and voltages but are shown offset in FIG. 2 in the interests of clarity. This is true for all the timing diagrams herein.
• the present invention can be applied to read-modify write schemes where write operations are performed after read operations. In certain embodiments of the present invention, read and write operations can occur in a single clock cycle.
• read operations from the M x N cell array 104 of FIG. 1 occur " during both read-only operations and write operations.
• the wordline signal goes high ideally at the start of Phase A as shown by the wordline signal 312.
• the read operation is triggered by a falling clock edge of the clock signal 310.
• the wordline signal 312 is shut down as soon as possible after the read operation to conserve power since power is being consumed whenever the wordline signal is being provided
• the wordline signal goes high ideally at the start of Phase A as shown by the wordline signal 314 and is extended throughout Phase B so that the write operation can occur within Phase B.
• FIG. 3 therein is shown a schematic diagram of a wordline latching memory circuit 400 in accordance with the present invention.
• a clock 401 is connected to clock inputs of a set of address flip-flops 402.
• the set of address flip-flops 402 include one or more address flip-flops 402(1... n) for l...n wordlines.
• the address flip-flops 402(1... n) are monotonic, or in continuous sequence, and each provide true and complementary outputs.
• the set of address flip-flops 402 is connected to a decoder 406, which causes the time delay 316 of FIG. 2.
• the decoder 406 includes decoding circuits 408(1... n) for decoding address information.
• Each of the decoding circuits 408(1...n) includes a pair of NAND gates 410(1...n) and 412(1...n), which have outputs respectively coupled to an input of AND gates 414(1...n), which have respective outputs connected to an input of inverters 416(1...n).
• the outputs of the inverters 416(1...n) are the outputs of the decoder 406.
• the decoder 406 can be of several types such as static decoders (shown on FIG. 3), dynamic decoders, or two-bit pre-decoders.
• the decoder 406 connects to latch circuitry 418.
• the latch circuitry 418 includes a set of OAI gates 420(1...n), which are respectively connected to the inverters 416(1...n) of the decoder 406.
• the number of OAI gates 420 can vary depending on the specific application, but generally it is equal to the number of wordlines.
• the OAI gates 420(1...n) are respectively connected to wordlines 422(l...n).
• the decoder 406 decodes the address information to select the wordlines 422(1...n), which will be activated when they have been selected.
• Each of the OAI gates 420(1...n) includes an OR, gate 424(1...n) and an AMD gate 426(1...n).
• n respectively connects to first inverting inputs of the OR gate 424(l...n), and each of the outputs of the AND gate 426(l...n) respectively connects to second inverting inputs of the OR gates 424(1...n).
• the outputs of the OR gates 424(l...n) are the respective output of the OAI gates 420(l...n) to the wordlines 422(1...n).
• the outputs of the OR gate 424(1. nieth) also respectively connect to first inputs of NAND gates 428(1...n).
• the NAND gates 428(1...n) have respective outputs connected to first inverting inputs of the AND gate 426(1...n).' Second inverting inputs of the AND gate 426(1...n) are connected to the clock 401.
• the clock 401 also connects to a write-enable flip-flop 430, which responds to a write-enable signal 531 and has an output that connects to second inputs of the NAND gates 428(1.. ⁇ ).
• the wordlines 422(1...n) are respectively connected to a set of memory cells 432 having memory cells 432(1...n).
• the memory cells 432(1...n) respectively include two pass transistors 434(1...n) and 436(1...n) having gates to which the wordlines 422(1...n) are respectively connected.
• the two pass transistors 434(1..,n) and 436(1...n) are respectively coupled to two inverters 438(l...n) and 440(l...n) and to two bitlines 442 and 444. It will be understood that there will be a plurality of bitlines in the cell array 104, but only two are shown.
• the two bitlines 442 and 444 are connected to sensing circuitry such as a sense-amp
• the sense-amp 450 is one of a plurality of sense-amps connected across the respective plurality of bitlines.
• the write-enable flip-flop 430 connects to a first inverting input of a read-enable AND gate 452 and the output of the read-enable AND gate 452 connects to the sense-amp 450 (and to other sense-amps for the other bitlines).
• a second inverting input of the read-enable AND gate 452 is connectable receive to an enable signal 454.
• FIG. 4 therein is shown a timing diagram 500 having a vertical voltage axis and a horizontal time axis. The timing diagram 500 is for a read-only operation.
• the clock signal 310 is shown with the wordline signal 312, which represents the duration in which a wordline signal remains high for the read-only operations.
• the wordline signal 312 represents the duration in which a wordline signal remains high for the read-only operations.
• two bitline signals 502 and 504 are shown.
• the bitline signals 502 and 504 represent signals on the bitlines such as the bitlines 442 and 444 of FIG. 3, respectively.
• a vertical line 506 represents the approximate trigger point of the sense-amp 450.
• the wordline signal 312 rises shortly after the clock signal 310 rises, due to the time delay 316. When the wordline signal 312 goes high, a differential builds.
• the bitline signal 502 stays high all the time because it is connected to a high voltage side of the memory cell 432(1) of FIG. 3.
• the bitline signal 504 slowly drops and is connected to the low voltage side of the memory cell 432; there is typically a 0 voltage at that point. Accordingly, there is a small voltage differential between the bitline signals 502 and 504 indicative of a logical state of the memory cell 432(1). In order for the overall circuit to operate properly the differential must be amplified so that the signal goes from zero to high. The sense-amp 450 amplifies the differential to provide a so-called full-swing voltage.
• the bitline signal 504 lowers in voltage due to a capacitance on the transistor 436(1) of FIG. 3.
• the transistor 436(1) of FIG. 3 has capacitance switch discharges causing the bitline signal 504 to lower in voltage.
• the bitline signal 504 begins to rise again after the wordline signal 312 goes low. As the wordline signal 312 goes low, the bitline signal 504 is not being pulled down. So the bitline signal 504 gets charged back up. The bitline signal 504 is charged back up because the bitline signal 504 is always connected to a Vdd voltage source (not shown).
• a vertical line represents an approximate sense-amp trigger point 506 of the sense-amp 450. This trigger point is important where the wordline latch circuit is a synchronous design, as it is in this specific embodiment. Because it is synchronous, events occur on the falling or rising edge of the clock cycle, subject to some delays; e.g., by the decoder delay.
• the wordline 422(1) goes low immediately after the write operation completes by using the falling edge of the clock signal 310 to release the latch of the wordline signal 314. If the wordline 422(1) goes low too soon, a write signal 603 to the bitlines 442 and 444 will not be able to write to the memory cell 432(1) because it will be shut off.
• FIG. 5 therein is shown a timing diagram 600 having a vertical voltage axis and a horizontal time axis.
• the timing diagram 600 is for a write operation.
• the clock signal 310 and bitline signals 602 and 604 are shown in accordance with the present invention.
• the address signals enter the address flip-flops 402(1... n) timed by the clock signals 310 from the clock 401.
• the clock 401 is asserted high, the set of address flip-flops 402 is triggered creating a set of true and complimentary signals that are fed to the decoder 406.
• n) selectively enable or disable the wordlines 422(1...n) by providing selected signals to the groups of six inputs of the decoding circuits 408(1...n) in the decoder 406.
• the following is an example of the operation of the wordline latching memory circuit 400 for a single wordline.
• the NAND circuit 408(1) outputs a low to the OAI gate 420(1).
• the inverting input of OR gate 424(1) is pulled low causing the output of OAI gate 420(1) to rise as shown by the wordline signal 312.
• the write-enable signal 431 is held low so the output of the write-enable flip-flop 430 is also forced low upon being triggered by the clock signal 310 from the clock 401. This forces the output of NAND gate 428(1) to be high, effectively disabling the AND gate 426(1) and causing the OAI gate 420(1) to provide a high on to the wordline 422(1).
• the high on the wordline 422(1) activates the memory cell 432(1) to place bitline signals 502 and 504, representative of previously stored high or lows signals, to be transferred onto the bitlines 442 and 444.
• the clock signal 310 falls, the outputs of the address flip-flops 402(1...
• the sense- amp 450 is triggered by the clock signal 310 and the enable signal 454 via the read-enable AND gate 452 to read the bitlines 442 and 444 for the bitline signals 502 and 504.
• the sense-amp 450 latches the data from the bitline signal 504 from the bitline 444. Shortly after the triggering of the sense-amp 450, the wordline signal 312 falls to its low.
• the effective power cut-off to all the wordlines around the beginning of the falling edge of the clock signal 310 conserves power and the read at around the end of the falling edge of the clock signal 310 assures the security of the read operation.
• the operation of the wordline latching memory circuit 400 for the write operation is similar to that of the read operation. The main difference is that the wordline is being held high longer, but not so long that it interferes with the next clock cycle.
• the decoder 406 determines the wordline 422(1) has been selected, the NAND circuit 408(1) outputs a low to the OAI gate 420(1).
• the inverting input of OR gate 424(1) is pulled low causing the output of OAI gate 420(1) to rise as shown by the wordline signal 314.
• the write-enable signal 431 is held high so the output of the write-enable flip-flop 430 is also forced high upon being triggered by the clock signal 310 from the clock 401.
• the high on the wordline 422(1) activates the memory cell 432(1) to place the bitline signals 502 and 504, representative of previously stored high or lows signals, onto the bitlines 442 and 444.
• the outputs of the address flip-flops 402(1... n) are forced but the wordline signal 314 remains high even when the decoder 406 provides a low to the OAI gate 420(1).
• the NAND GATE 428(1) provides a low to the first inverting input of the AND gate 426(1) while the clock 401 provides a second low to the second inverting input.
• the AND gate 426(1) provides a high to the OR gate 424(1) to latch the wordline 422(1) in high.
• the read operation can optionally be performed during Phase A.
• the write operation is performed while the wordline signal 314 is still high in Phase B as indicated by the write pulse placed on the bitline 442 by the bitline signal 602 from the I O circuitry 106 of FIG. 1.
• the combination' of the NAND gate 428(1) and the OAI gate 420(1) forms a latch which holds the wordline 422(1) high until the clock signal 310 starts rising again causing AND gate 426(1) to unlatch the output of the OAI gate 420(1) and de-assert the wordline 422(1).
• the effective power cut-off to all the wordlines around the beginning of the rising edge of the clock signal 310 assures the safety of the successful read operation in the next cycle.
• Embodiments of the present invention can have several applications.
• the wordline latch circuit can be used in cache memory.
• cache memories are built of one or more smaller memory blocks called banks.
• the wordline latch circuit can be used inside the banks of cache memory.
• Other embodiments can be used outside of cache memory as well.
• the microprocessor When used in a microprocessor for example, the microprocessor generates the memory addresses where the data resides.
• the microprocessor can have several layers of memory. There is a so-called Level 1 (LI) memory and a Level 2 (L2) memory, sometimes a Level 3 (L3) memory. There is also a main memory.
• the main memory is also called external memory because it is typically external to the microprocessor. LI memory is the easiest and fastest memory to access.

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