WO2005013357A1 - Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits - Google Patents
Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits Download PDFInfo
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- WO2005013357A1 WO2005013357A1 PCT/US2003/041684 US0341684W WO2005013357A1 WO 2005013357 A1 WO2005013357 A1 WO 2005013357A1 US 0341684 W US0341684 W US 0341684W WO 2005013357 A1 WO2005013357 A1 WO 2005013357A1
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- opening
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- depth
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- etching
- Prior art date
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- 238000004513 sizing Methods 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000003989 dielectric material Substances 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 239000012212 insulator Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- OPARTXXEFXPWJL-UHFFFAOYSA-N [acetyloxy-bis[(2-methylpropan-2-yl)oxy]silyl] acetate Chemical compound CC(=O)O[Si](OC(C)=O)(OC(C)(C)C)OC(C)(C)C OPARTXXEFXPWJL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 239000011819 refractory material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- LFQCEHFDDXELDD-UHFFFAOYSA-N tetramethyl orthosilicate Chemical compound CO[Si](OC)(OC)OC LFQCEHFDDXELDD-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical class CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000009021 linear effect Effects 0.000 description 1
- 230000009022 nonlinear effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the present invention relates generally to integrated circuits and more particularly to contacts formed down to active regions under a dielectric layer.
- Integrated circuits are used in most electronic devices such as computers, radios, TV's, cell phones, etc.
- the hearts of these integrated circuits are semiconductor devices, which can be transistors, diodes, capacitors, etc.
- the semiconductor devices are generally formed on semiconductor substrates and are covered by insulating, or dielectric, materials.
- transistors are formed by implanting spaced-apart source/drain regions into the semiconductor substrate and forming control gates over the semiconductor substrate above the space between the source/drain regions. A dielectric is then deposited over the transistors. Since electrical connections need to be made to the source/drain regions and to the control gates, metal contacts are formed through the dielectric layer to the tops of the control gates and to the surface of the semiconductor substrate.
- the contacts are referred to as multi-level contacts, and more specifically as two-level contacts.
- SOI technology deals with the formation of semiconductor devices on a layer of semiconductor material which is over an insulating layer in a semiconductor substrate.
- a common embodiment of the SOI structure is a single active layer of silicon which overlies a layer of silicon dioxide insulator in a substrate silicon.
- SOI technology requires multi-level contacts, which are three-level contacts.
- an etch process is used with contact holes patterned to have the same diameter. The etch through the dielectric layer reaches the shallowest layer or the top of the gate earlier than the active silicon and much before reaching the deeper substrate silicon. Since the duration of the etch process needs to be sufficient to reach the deepest levels, significant over-etch occurs at the shallowest levels.
- an underlayer or etch stop layer is provided over the gates, the source/drain regions, and the substrate silicon.
- the underlayer is either an etch stop dielectric layer or gate material (silicon/metal) and substrate silicon (active and/or SOI substrate).
- etch stop dielectric layer silicon/metal
- substrate silicon active and/or SOI substrate.
- immunity or selectivity of the underlayer to the etch is limited. As a result, a considerable portion of the underlayer is removed during long-duration over-etches.
- the required thickness of the underlayer is determined by the maximum over-etch and the etch rate of the underlayer, which is related to the selectivity. Multi-level contacts require much more over-etch than a single-level contact.
- the thickness of any underlayer is limited by geometric considerations. This is especially true for the CMOS technologies with very high gate densities.
- the thickness of the underlayer needs to be less than one-half of the space between the gate sidewall spacers around the gates where the contact will be formed. If the thickness of the underlayer is greater than one-half the space, the underlayer portions of the two gates will "merge" and form an increased thickness of underlayer which will prevent proper etching. Unfortunately also, if the etch requirement for a given underlayer thickness is above the maximum underlayer thickness allowed by the geometric considerations, then the multilevel contacts cannot be formed with a single etch process. This requires multiple etches and separate patterning for the different level contacts. For example, where two separate patterning steps are required, it will be necessary to mask for the shallow contacts, etch, mask for the deep contacts, and etch.
- the underlayers usually employed are materials such as silicon nitride and silicon oxynitride, which have dielectric constants higher than the pre-metal dielectric layers. This results in increased - parasitic capacitance in such areas as gate-to-contact, gate-fringing, and gate-to-first metal. In some SOI technologies, no underlayer is used. In these situations, significant over- -. etch occurs on the active silicon during the multi-level contact etch and in particular down to the substrate silicon. Since selectivity to silicon is limited, this results in etching into the active silicon.
- the present invention provides a method for forming an integrated circuit including etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate.
- the first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag.
- the first and second openings are filled with conductive material.
- FIG. 1 is calibration structure for aspect-ratio dependent etching (ARDE) with an etchable material
- FIG. 2 is a view of a two-level etched contact structure in accordance with the present invention
- FIG. 3 is a view of a three-level etched contact structure in accordance with the present invention
- FIG. 4 is a view of an alternate embodiment of a three-level etched contact structure in accordance with the present invention
- FIG. 5 is a view of a three-level etched contact structure as completed in accordance with the present invention
- FIG. 6 is a flowchart showing a method for foirming an integrated circuit in accordance with the present invention.
- ARDE a phenomenon called "Aspect-Ratio Dependent Etching"
- ARDE a phenomenon called "Aspect-Ratio Dependent Etching"
- RIB reactive ion etch
- RIE lag plasma dry etch
- etch lag features with smaller openings etch in a dielectric material slower than features having large openings. This is undesirable because each etch step is generally intended to etch to a single depth regardless of feature size.
- RIE lag When optimizing a plasma dry etch process for rninimized RIE lag, usually there is some trade-off, which has to be made, e.g., lower selectivity to etch stopping layers.
- horizontal as used in herein is defined as a plane parallel to the ** ** * conventional plane or surface of a wafer or substrate, regardless of its orientation.
- vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, “under”, “shallow”, and “deep”, are defined with respect to the horizontal plane.
- processing as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in fo ⁇ ning a described structure. Referring now to FIG.
- a calibration structure 100 for Aspect-Ratio Dependent Etching (ARDE).
- a calibration dielectric material 102 has a photoresist 104 deposited thereon.
- the photoresist 104 is processed to form a plurality of features over a range of sizes from a minimum photolithographic diameter to a multiple of this diameter; e.g., the minimum diameter could be 100 nm and the range could extend upwards to a maximum contact diameter of 1,000 nm.
- first, second, and third openings 106, 108, and 110 are shown having a plurality of dimensions such as respective first, second, and third dimensions 112, 114, and 116.
- the dimensions of the features are sized such that the first dimension 112 is smaller than the second dimension 114, which is smaller than the third dimension 116; i.e., the third dimension 116 is larger than the second dimension 114, which is larger than the first dimension 112.
- the dimensions of the features in the photoresist establish the starting dimensions of the features that will be etched into the calibration dielectric material 102. In situations where the phenomenon of etch lag occurs, the first, second, and third openings 106, 108, and 110 will form respective first, second, and third features 118, 120, and 122 in the calibration dielectric material 102.
- the first, second, and third features 118, 120 and 122 will have respective first, second, and third depths 124, 126, and 128.
- ARDE is generally a non-linear effect. Since the features increase in size from the first dimension 112 to the third dimension 116, the depths increase from the first depth 124 to the third depth 128; i.e., larger features etch faster and reach greater depth during the same time. While contact openings can be of various configurations, if the features were for cylindrical contact openings, the first, second, and third dimensions 112, 114, and 116 in the photoresist 104 would be diameters for the tops of the contact openings in the calibration dielectric material 102.
- FIG. 2 therein is shown a two-level etched contact structure 200 in accordance with the present invention.
- a first semiconductor substrate 202 or substrate silicon is implanted with source/drain regions 204 and 206 having a gate dielectric 208 above a space between the source/drain regions 204 and 206.
- a gate 210 is above the gate dielectric 208 and is surrounded by a gate spacer 212 to form the upper portion of a semiconductor device 213.
- An underlayer 214 is disposed over the first semiconductor substrate 202 to cover the gate spacer 212 and the gate 210.
- a pre-metal dielectric layer 216 is deposited over the underlayer 214 and a photoresist 218 is deposited over the pre-metal dielectric layer 216.
- the photoresist 218 has been processed to form first and second openings 220 and 222 having first and second diameters 224 and 226.
- a gate contact 228 and a region contact 230 are formed which reach the underlayer 214 at about the same time with no or minimal over-etch into the underlayer 214.
- the mh ⁇ dmum contact diameter is established; e.g., the first diameter 224 for the gate contact 228.
- this value is often determined by the minimum opening that can be reliably resolved in a photoresist by the photolithography process in use.
- the minimum contact diameter is used for the shallowest level contact.
- the etch lag of the etch process is determined using the calibration structure 100 shown in FIG. 1 forming feature openings over a range of sizes from the minimum contact diameter to a multiple of this diameter; e.g., the minimum diameter could be 100 nm and the range could extend upwards to a maximum contact diameter of 1 ,000 nm.
- L etch lag
- D m i n depth of the contact with the minimum diameter
- D depth of a contact with a different diameter.
- the etch lag above is not necessarily linear with diameter and depth.
- the calibration structure 100 is used to select feature opening sizes based on the desired etch depths where the feature etch lag is closest to the optimal etch lag.
- a diameter is selected to be a diameter that gives an etch lag closest to the optimal etch lag. With such a selection of the contact diameter, the etch process with reach the bottoms of both the shallow and deep contacts at about the same time. Referring now to FIG. 3, therein is shown a three-level etched contact structure 300 in accordance with the present invention.
- a second semiconductor substrate 302 or substrate silicon has an insulator 304 deposited thereon containing first semiconductor substrate 306 or active silicon.
- the first semiconductor substrate 306 has implanted source/drain regions 308 and 310 implanted therein.
- a gate dielectric 312 Formed over the gate dielectric 312 is a gate 314 having a gate spacer 316 therearound to form the upper portion of a semiconductor device 317.
- a trench 318 has been etched into the insulator
- a pre-metal dielectric layer 322 is deposited over the underlayer 320.
- a photoresist 324 is deposited over the pre-metal dielectric layer 322 and processed to form first, second, and third contact openings 326, 328, and 330.
- the first, second, and third contact openings 326, 328, and 330 have respective first, second, and third diameters 332,
- the three-level etched contact structure 300 has the optimal etch lag and contact diameter calculated separately for the very deep and the medium deep contact. The resultant contact sizing will allow the etch process for first, second, and third contact openings 338,
- FIG. 4 therein is shown an alternate embodiment of a three-level etched contact structure 400 in accordance with the present invention. Elements, which are the same as in FIG. 3, have the same element numbers.
- the three-level etched contact structure 400 has first, second, and third contact openings 402, 404, and 406 having respective first, second, and third diameters 408, 410, and 412.
- the first diameter 408 and the second diameter 410 have the same diameters.
- the second diameter 410 is smaller than the third diameter 412.
- the first and second diameters 408 and 410 are made the same diameter so as to simplify circuit layout and mask generation. At the same time, this may avoid increasing the die size for the integrated circuit. With the distance between the first and second levels being minimal as compared to the third level, the etch process will proceed until the second contact opening 404 has reached the underlayer 320. At this point, it is to be expected that the first and third contact openings 402 and 406 will slightly over-etch into the underlayer 320 as indicated by first and third over-etches 414 and 416. This slight over-etch would be considered acceptable to obtain the benefits of having the first and second diameters 408 and 410 of the same diameter. Referring now to FIG.
- FIG. 5 therein is shown a three-level etched contact structure 500 as completed in accordance with the present invention.
- the same elements, which are shown in FIG. 3, have the same element numbers.
- the openings are filled with conductive material to form the first, second, and third contacts 502, 504, and 506.
- the first, second, and third contacts 502, 504, and 506 are respectively in contact with the gate 314, the first semiconductor substrate 306, and the second semiconductor substrate 302.
- the first, second, and third contacts 502, 504, and 506 have respective first, second, and third contact diameters 508, 510, and 512.
- the first, second, and third contacts 502, 504, and 506 are of refractory materials such as tantalum (Ta), titanium (Ti), tungsten (W), alloys thereof, and compounds thereof. If the contacts are of highly conductive materials such as copper (Cu), gold (Au), silver (Ag), alloys thereof, and compounds thereof with one or more of the above elements, the previously mentioned refractory materials will surround the highly conductive materials.
- the pre-metal dielectric layer 322 is of a dielectric material such as silicon oxide (SiO x ), tettaethylorthosilicate (TEOS), borophosphosilicate (BPSG) ⁇ glass, etc.
- the underlayer 320 (where used) is of a material such as silicon nitride (Si x N x ) or silicon oxynitride (SiON).
- the method 600 includes: a step 602 of etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate; a step 604 of etching a second opening to a second depth in the dielectric material over the first semiconductor substrate, the first and second openings differently sized to respectively etch to the first and second depths in about the same time due to etch lag; and a step 606 of filling the first and second contact openings with conductive material.
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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- Electrodes Of Semiconductors (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10394263T DE10394263B4 (en) | 2003-07-02 | 2003-12-30 | Method for producing an integrated circuit |
GB0601531A GB2420015A (en) | 2003-07-02 | 2003-12-30 | Method Of Manufacturing Multi-Level Contacts By Sizing Of Contact Sizes In Intergrated Circuits |
JP2005507461A JP2007521630A (en) | 2003-07-02 | 2003-12-30 | Method for fabricating multilayer contacts by sizing contact size in integrated circuits |
KR1020067000079A KR101029384B1 (en) | 2003-07-02 | 2003-12-30 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
CNA2003801103715A CN1802738A (en) | 2003-07-02 | 2003-12-30 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
AU2003300121A AU2003300121A1 (en) | 2003-07-02 | 2003-12-30 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
USPCT/US03/20872 | 2003-07-02 | ||
PCT/US2003/020872 WO2004006261A2 (en) | 2002-07-02 | 2003-07-02 | Wordline latching in semiconductor memories |
USPCT/US03/21282 | 2003-07-09 | ||
PCT/US2003/021282 WO2004013908A1 (en) | 2002-08-02 | 2003-07-09 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
Publications (1)
Publication Number | Publication Date |
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WO2005013357A1 true WO2005013357A1 (en) | 2005-02-10 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/041684 WO2005013357A1 (en) | 2003-07-02 | 2003-12-30 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits |
PCT/US2003/041683 WO2005013282A1 (en) | 2003-07-02 | 2003-12-30 | Wordline latching in semiconductor memories |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US2003/041683 WO2005013282A1 (en) | 2003-07-02 | 2003-12-30 | Wordline latching in semiconductor memories |
Country Status (7)
Country | Link |
---|---|
JP (1) | JP2007521630A (en) |
KR (1) | KR101029384B1 (en) |
CN (1) | CN1802738A (en) |
AU (2) | AU2003300120A1 (en) |
DE (1) | DE10394263B4 (en) |
GB (1) | GB2420015A (en) |
WO (2) | WO2005013357A1 (en) |
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JP2011044589A (en) * | 2009-08-21 | 2011-03-03 | Oki Semiconductor Co Ltd | Semiconductor device and method of manufacturing the same |
JP6486137B2 (en) * | 2015-02-16 | 2019-03-20 | キヤノン株式会社 | Manufacturing method of semiconductor device |
JP7069605B2 (en) * | 2017-08-29 | 2022-05-18 | 富士電機株式会社 | Manufacturing method of semiconductor device |
US11250895B1 (en) * | 2020-11-04 | 2022-02-15 | Qualcomm Incorporated | Systems and methods for driving wordlines using set-reset latches |
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JPH05121369A (en) * | 1991-10-24 | 1993-05-18 | Oki Electric Ind Co Ltd | Method of etching contact hole of semiconductor device |
US5317193A (en) * | 1992-05-07 | 1994-05-31 | Mitsubishi Denki Kabushiki Kaisha | Contact via for semiconductor device |
US6211058B1 (en) * | 1997-12-16 | 2001-04-03 | Advanced Micro Devices, Inc. | Semiconductor device with multiple contact sizes |
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GB2239541B (en) * | 1989-12-29 | 1994-05-18 | Intel Corp | Dual port static memory with one cycle read-modify-write operation |
US5031141A (en) * | 1990-04-06 | 1991-07-09 | Intel Corporation | Apparatus for generating self-timing for on-chip cache |
JPH0574167A (en) * | 1991-09-17 | 1993-03-26 | Nec Corp | Semiconductor memory device |
JPH05267251A (en) * | 1992-03-18 | 1993-10-15 | Oki Electric Ind Co Ltd | Formation of contact hole in semiconductor device |
US5530677A (en) * | 1994-08-31 | 1996-06-25 | International Business Machines Corporation | Semiconductor memory system having a write control circuit responsive to a system clock and/or a test clock for enabling and disabling a read/write latch |
JPH08316320A (en) * | 1995-05-22 | 1996-11-29 | Nec Corp | Production of semiconductor device |
JPH10154752A (en) * | 1996-11-21 | 1998-06-09 | Ricoh Co Ltd | Manufacture of semiconductor device |
JP2001044441A (en) * | 1999-07-29 | 2001-02-16 | Sony Corp | Full depletion soi-type semiconductor device and integrated circuit |
DE10054109C2 (en) * | 2000-10-31 | 2003-07-10 | Advanced Micro Devices Inc | Method of forming a substrate contact in a field effect transistor formed over a buried insulating layer |
JP2003045963A (en) * | 2001-07-30 | 2003-02-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing same |
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2003
- 2003-12-30 KR KR1020067000079A patent/KR101029384B1/en active IP Right Grant
- 2003-12-30 WO PCT/US2003/041684 patent/WO2005013357A1/en active Application Filing
- 2003-12-30 DE DE10394263T patent/DE10394263B4/en not_active Expired - Fee Related
- 2003-12-30 JP JP2005507461A patent/JP2007521630A/en active Pending
- 2003-12-30 AU AU2003300120A patent/AU2003300120A1/en not_active Abandoned
- 2003-12-30 GB GB0601531A patent/GB2420015A/en not_active Withdrawn
- 2003-12-30 WO PCT/US2003/041683 patent/WO2005013282A1/en active Application Filing
- 2003-12-30 CN CNA2003801103715A patent/CN1802738A/en active Pending
- 2003-12-30 AU AU2003300121A patent/AU2003300121A1/en not_active Abandoned
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JPH05121369A (en) * | 1991-10-24 | 1993-05-18 | Oki Electric Ind Co Ltd | Method of etching contact hole of semiconductor device |
US5317193A (en) * | 1992-05-07 | 1994-05-31 | Mitsubishi Denki Kabushiki Kaisha | Contact via for semiconductor device |
US6211058B1 (en) * | 1997-12-16 | 2001-04-03 | Advanced Micro Devices, Inc. | Semiconductor device with multiple contact sizes |
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Also Published As
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KR20060119856A (en) | 2006-11-24 |
DE10394263T5 (en) | 2006-04-27 |
GB2420015A (en) | 2006-05-10 |
CN1802738A (en) | 2006-07-12 |
KR101029384B1 (en) | 2011-04-15 |
GB0601531D0 (en) | 2006-03-08 |
WO2005013282A1 (en) | 2005-02-10 |
AU2003300121A1 (en) | 2005-02-15 |
DE10394263B4 (en) | 2011-05-26 |
AU2003300120A1 (en) | 2005-02-15 |
JP2007521630A (en) | 2007-08-02 |
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