GB2239541A - Dual port static memory with one cycle read-modify-write operation - Google Patents

Abstract

Bistable memory cells 40 are coupled to read bit lines 51-54 through transistors 55-58 controlled by word lines 300, 310. Additional (write) lines 22-25 are coupled to the cells and isolated from the bit lines. During a read-modify-write operation precharge on the bit lines after the read operation is undisturbed when writing occurs into the cell from the write lines since word lines 300, 310 are now low. In the dual port memory a conflict determining circuit is used to provide a predetermined state to the cell when simultaneous access is sought for writing to the cells with conflicting data. <IMAGE>

Description

1 D -,,SA 1 DUAL PORT STATIC MEMORY WITH ONE CYCLE READ-MODIFY-WRITE

OPERATION.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

The invention relates to the field of semiconductor memories.

2. Prior Art.

Static memories are widely used in the semiconductor Industry. For example, these memories are often used for cache memories. Typically, these memories are fabricated from a plurality of bistable circuits (flipflops) each forming a cell for storing one bit of data. In the memory array bit lines are precharged for reading data from the cells; these bit lines are also used during writing by driving the lines to the desired state as determined by the Incoming data.

Dual port static memory cells are also known In the prior art. An example of one such cell is shown in U.S. Patent 4,823,314.

As can be seen, the present invention provides a dual port static memory where a read-modify-write operation can occur in one memory cycle. The memory also includes a circuit for resolving conflicting write data when one cell is accessed at both its ports.

SUMMARY OF THE INVENTION

An improvement in a bistable memory cell is described. Complementary nodes in the memory cell are connected to complementary bit fines In the memory array through first field-effect transistors. The gates of these transistors are coupled to a word line in the array. Separate write lines are employed which are coupled to the complementary nodes of the cell. The write fines are isolated from the bit lines when the first transistors are off. Data is read from the cell onto the bit lines when the first transistors conduct. During a read-modifywrtte operation, the bit lines may be precharged after data Is read from the cell since the bit lines are isolated from the cell by the first transistors. This allows data to be written Into the cells from the write lines without disturbing the precharge on the bit lines. The bit fines are then ready for a read operation during the very next memory cycle.

The nodes of the cell are selectively coupled to ground for wrIting through second transistors controlled by the write lines. These second transistors are in sedes with third transistors which are controlled by an extended word line (control) signal. This signal is terminated at the beginning of the next memory cycle. This arrangement allows the write lines to be decoupled from the cell under control of the extended word line signal thereby permitting reading to occur during the following memory cycle.

A circuit Is disclosed which resolves any conflict In data presented to a dual port cell.

2 1 BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram showing the general layout of a memory employing the present invention.

Figure 2 is an electrical schematic showing the currently preferred embodiment of a single dual port static memory cell with its coupling to dual pairs of bit fines, dual pairs of write lines, two word lines, and two extended word lines.

Figure 3 is an electrical schematic of an extended word fine control signal generator.

Figure 4 is a timing diagram showing several waveforms associated with 15 the operation of the invented memory.

Figure 5 is an electrical schematic showing the circuit used to resolve conflicts in data when one dual port cell is selected by both addresses.

DETAILED DESCRIPTION OF THE INVENTION:

A dual porl memory employing static memory cells Is described. In the following description. numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, wellknown circuits such as decoders are shown in block diagram form and other well-known details are not set forth in order not to unnecessarily obscure the present invention. OVERVIEW OF THE MEMORY

In the currently preferred embodiment, the memory is part of a cache memory. The memory is fabricated using well-known complementary metal oxide-semiconductor (CMOS) processing. In the drawings, the p-channel field-effect transistors are designated by the use of a small circle above the transistor's gate; the n-channel field-effect transistors are identified by the absence of the circle above the gate. The memory employs ordinary bistable (flip-flop) cells.

In the currently designed dual port array there are 128 groups of four cells; one group is shown as the group of cells 10 of Figure 1. Each group of 4 cells 10 Is coupled to two word lines, two extended word lines, 4 pairs of (complementary) first write fines, 4 pairs of (complementary) second write lines, 4 pairs of first (complementary) bit fines and 4 pairs of second (complementary) bit fines. One cell from a group of four cells is shown in Figure 2. This cell Is coupled to two word lines, two extended word fines, a first and second pair of write fines and a first and second pair of bit lines.

In Figure 1, the word lines are shown collectively as WL1 (lines 31) and WL2 (bnes 30). In Figure 2, a single one of the word lines WL1 is shown as word rine 310 and a single one of the word lines WL2 as line 300. In Figure 1.

4 the extended word lines are shown collectively as EWL1 (lines 33) and EWL2 (lines 32). In Figure 2, a single extended word lines is shown as line 320 and another as line 330. Two pairs of write lines, lines 22, 23, 24 and 25 are shown in Figures 1 and 2. The write signal, as discussed, is derived within the driving logic 17 from the input data supplied to the driving logic 17 on lines 19. Bit lines 51, 52. 53 and 54 are also shown in Figure 2.

The memory is coupled to receive two addresses shown as A1 (lines 35) and A2 (lines 36). Each address is decoded (decoder 13 for A1 and decoder 14 for A2). In an ordinary manner these decoders select word lines. Decoder 13 selects one of the 128-WL1 lines and decoder 14 selects one of 128-WL2 lines.

Extended word fine signals are generated by the extended word line control signal generators 11 and 12; one such generator is shown.in Figure 3.

The generators 11 provide the EWL1 signals on lines 33 and the generators 12 provides the EWL2 signals on lines 32. There is an extended word ling generator associated with each of the extended word lines and as will be seen in conjunction with Figure 3. each of these generators is coupled to an associated word line and in effect, extends the word line signal If such sigrud is present.

Data is read from the cells on the bit lines through the sense amplifiers and precharge circuit 18. Prior to the sensing of the data on the bit fines. these bit lines are precharged as is well-known in the art. The output data Is provided on lines 15. This output data is also coupled to the driving logic 17 for timing purposes. The logic 17. once data is outputted during a read-modify-writo operation then couples the Input data to the write fines through the ci=ft shown in Figure 5.

Reset/set signals on lines 28 and 29 are provided to the generators 11 and 12. These signals are shown and discussed in conjunction with Figures 3 and 4.

MEMORY CELL AND ITS COUPLING TO BIT LINES, WRITE LINES, WORD LINES AND EXTENDED WORD LINES In Figure 2, a single memory cell is shown within dotted line 40. (in the prior art static memory cells are often referred to as 6 transistors cells and include a bistable circuit such as shown within dotted ling 40 and a pair of transfer transistors which connect the cell to complementary bit lines. These bit lines are used for both reading and writing. For purposes of this application, the memory cell has been defined not to include these transistors since the complementary nodes of the flip-flop are coupled to separate bit lines and write lines.) The cell comprises transistors 41 and 42 cross-coupled with the transistors 43 and 44. The node 45, the junction between transistors 41 and 42. is coupled to the gates of transistors 43 and 44. Similarly, the common junction (node 46) between transistors 43 and 44 is coupled to the gates of transistors 41 and 42. Node 45 is coupled to the bit line 51 (BL1#) through 20 transistor 55 and to bit line 52(BL2#) through transistor 56. (The V symbol is used to designate the complementary binary state or line carrying that state.) The complementary node 46 Is coupled to the bit line 53 (BL2) through transistor 57 and bit line 54(130) through transistor 58. The gates of transistors 58 and 55 are coupled to line 310, thus the state of the call can be sensed on 25 BL1 BLI# when line 310 is positive or high. The gates of transistors 56 and 57 are coupled to line 300 and when this word line Is high. data may be sensed on BL2 and BL2#.

6 1 1 Nodes 45 and 46 are also coupled to the write lines 22, 23, 24 and 25. One terminal of transistors 60 and 61 is coupled to node 45. The gate of transistor 61 is coupled to line 24. Node 46 is coupled to one terminal of transistors 62 and 63. The gate of transistor 62 is coupled to fine 23 and the gate of transistor 63 is coupled to line 22. The other terminals of transistors 60 and 63 are coupled to ground through transistor 65. The gate of transistors 65 receives the signal on fine 330 (one of the EWL1 signals). Similarly, the other terminals of transistors 61 and 62 are coupled to ground through transistor 64; this transistor's gate is coupled to line 320 (and hence, receives one of the EVVIL2 signals).

It should be noted that transistors 63 and 65 are coupled in series as are transistors 60 and 65. In a like fashion, transistors 62 and 64 and transistors 61 and 64 are coupled In series. Thus, for example, for write (data) transferred from line 22 to the node 46 of the cell, both transistors 63 and 65 must conduct (both Write 1# signal and the associated EWL1 signal are high). This is important, since as will be seen, the EWL signal is terminated at the beginning of a cycle to prevent a bit line from being coupled to ground after a word line's potential rises for the next memory cycle.

Data is read from the cell through one port on BL1 and BL# (lines 54 and 51, respectively) when line 310 is selected. And, similarly, data is read from the cell onto the bit lines BL2 and BL2# when line 300 is selected. h is possible for the addresses A1 and A2 to be the same, and hence, the same cell or group of cells are selected. For reading, this presents no problem since the data In the cell Is read onto both pairs of bit lines.

Data is written into a cell from the write fines. For example, If Write 1 Is high and Write 1# is low, and assuming the EWL1 signal on line 330 is asserted, then node 45 is coupled to ground through transistors 60 and 65 7 setting the state of the cell. Similarly, data can be written Into the cell from lines Write 2 and Write 2#.

In effect, data is written into the cells through the Obackdooro; that Is, not through the bit lines and normally used to transfer transistors. Note this technique may be used on a single port memory cell where only one pair of bit lines and one pair of write lines are used. Also In some memory It may be feasible to use a single (non-complementary) bit line and write line.

As previously indicated, lines 300. 310. 320 and 330 are coupled to other cells located along the same row as cell 40 and similarly, the bit lines and write fines are coupled to other cells located along the column which Includes cell 40.

EXTENDED WORD LINE GENERATOR Each of the extended word lines includes an extended worcINne generator which is coupled to its associated word line. One such generator is shown in Figure 3. The generator basically comprises a bistable circuit (transistors 67. 68, 69 and 70). One node 74 provides an output (the extended word line signal), the other node 75 of this circuit is coupled through transistor 73 to the reset line 29. The gate of transistor 73 is coupled to (or is part ol) the associated word fine. The reset line 29 is also coupled to the gate of transistor 72; this transistor pulls to ground node 74 when the reset signal is high. The set Hne 28 Is coupled to the gate of transistor 71. When the set signal is high. node 75 Is coupled to ground.

At the beginning of every memory cycle, all the word line generators are reset. This occurs when the potential on line 29 rises and the potential on line 28 remains low. Note that at this time no potential is present on any of the word lines. The potential on line 29 causes transistor 72 to conduct, setting the bistable circuit so that node 74 is low, that is, no extended word line signal is 8 asserted. During the memory operation, such as a read-modify-write operation, the reset signal on line 29 remains low after the memory cycle Is initiated and the potential on the selected word lines rises. If the word line is asserted, then transistor 73 conducts, pulling node 75 to ground through the reset line. In this case, the extended word line signal is asserted as It would be in a read-modified-write operation. If the word fine is not selected. then node 74 remains at ground for the remainder of the cycle. (The set signal on line 28 may be used to assert the extended word fine signal. This, for example, may be done to initialize all the memory cells in the memory.) MEMORY OPERATION AND TIMING During an ordinary read cycle, addresses are applied to the address decoders selecting one or two word fines. The selected cell, or cells, are then coupled to the bit lines providing an output. The bit lines are first precharged as is commonly done to allow the sense amplifiers to more quickly sense the cell's state. Note that with the illustrated memory organization, one cell will be coupled to one set of bit lines and another cell to another set of bit lines If the addresses are different, or one cell will be connected to both sets of bit lines if the addresses are the same. In this latter event, the same data Is read onto both s of bit fines.

Une 78 of Figure 4 shows the waveforms 83 and 84 of the clocking signal each of which Initiates a memory cycle. Une 79 shows the word #no signal which follows the decoding of the addresses after the clock signal has occurred. For example, the leading edge of waveform 85 follows (in time) the leading edge of waveform 83 by time 86. The extended word line signals are shown online 80. Since the EWL signal requires the word line signal for Its generation, the EWL signal follows the WL signal. The leading edge of waveform 87 is shown trailing the leading edge of waveform 85 by time 88.

9 During a write operation, the input data from lines 19 is coupled onto the write lines 22, 23, 24 and 25. The extended word line generators associated with the selected word lines provide the EWL signal which is shown on line 80 of Figure 4. This signal continues on in time beygnd when the word line signal for that cycle drops in potential. This allows the data on the write lines to be coupled into the cell or cells setting the cells in the appropriate state. The timing of the EWL signal is discussed below for the read-modified-write operation.

Importantly, the present invention permits a read-modify-write operation for the selected cell or cells in one memory cycle as described below.

Both in a read operation and initial portion of the read-modify-write operation, once the word line rises in potential. the state of the cells can be sensed on the bit lines, these bit lines having previously been precharged.

Once the EWL signal is asserted, transistors 64 or 65 or in some cases both transistors conduct. However, this does not cause any writing into the cell at this time for the read-modify-write operation. The driving circuits which provide the write Une signals do not provide data until the sense amplifiers have latched the output data. For this reason. the output of the sense amplifiers Is also coupled to the driving circuit 17. Once the driving circuit senses that data is present on the output data lines 15, the write lines are activated. At this time, since for example, both transistors 60 and 65 conduct, data Is written Into the cell. The data out is represented in Figure 4 on line 61 by the waveform 89 and a write signal is shown on line 82 by waveform 90. The leading edge of the write signal follows the leading edge of the data out signal by time 91.

Once the data has been sensed. the word line potential drops. Isolating the bits lines from the cell, or cells. This permits the precharging of the bit lines in preparation for the next memory cycle. Importantly, once the next clocking c .. 5 signal occurs, the EWL generator is reset causing the EWL signal to drop. This is shown by line 92. It is important to note that the EWL signal drops In potential before the next word line signal occurs. Note the time 93 which occurs between the trailing edge of waveform 87 and the leading edge of waveform 94.

This prevents charge on the bit lines from being disturbed by the writing operation. Therefore, it is possible to have a read-modify-write operation in one memory operation and indeed. read- modify-write operations can occur one after the other in the invented memory.

Alternately, the write lines can be clamped once the clock rises on the next cycle.

RESOLUTION OF CONFLICTING DATA As mentioned, in the currently preferred embodiment, A1 and A2 may select the same cell and in a write operation conflicting data may bffl applied to the write lines. The circuit of Figure 5 senses when this occurs and then places the cell In a predetermined state when data conflict occurs.

The circuit for resolving the conflict includes a comparator 99 which provides an output signal on line 100 when the addresses on lines A1 and A2 are the same. The signal on line 100 is applied to Input terminals of the NAND gates 105 and 106. The other terminal of NAND gate 106 is coupled to receive the Writel IN signal. The other terminal of the NAND gate 105 Is coupled to receive the Wdte2#IN signal. The Write 1 IN signal is applied through the series inverters 101 and 102 to provide the Writel signal on line 25. The Wdtel#IN signal Is applied to one input terminal of NAND gate 103. The output of the Inverter 101 Is also an Input to the NAND gate 103. The third input to this gate is the output of gate 105. The output of gate 103 is coupled through the inverter 104 to provide the Writel# signal on line 22. The Write 2M signal Is applied to one input terminal of the NAND gate 107. The output of the gate 106 provides 11 f another input to gate 107. The Write21N signal is the third input to gate 107 after this signal is coupled through the inverter 109. The output of the gate 107, after passing through inverter 108, provides the Write2# signal on line 23. The Write21N signal is coupled through inverters 109 and 110 to provide the Writ92 signal on line 24.

Assume first that the addresses AI and A2 are different. The potential on line 100 is low and the conditions of gates 105 and 106 are not met. Since these are NAND gates, high inputs are provided to gates 103 and 107. This effectively removes gates 105 and 106 and their outputs from the remainder of the circuit. For example, no matter what the input on the Writel IN line, the ouW of gate 106 remains high.

Considering the circuit of Figure 5 without gates 105 and 106, it can be readily seen that the Writel signal appears on line 25 unaltered In ptate since h passes through two inverters. Similarly, the Write21N signal after passing through inverters 109 and 110 appears on line 24 unaltered in state. Ifthe WriteMN signal Is high, the input from inverter 101 YAII be low. since the Writel IN and Writel #IN signals are complementary. All the conditions of gate 103 are thus met, and the output of this NAND gate will be low. After passing through Inverter 104, the Write 1# signal is low. Similarly, the Write 2M signal appear on line 23 unaltered as long as the addresses do not match.

Next, consider the case when a match of address occurs and the Writel IN signals and the Write21N signals are high. (This is a case of nonconflicting data.) Both Inputs to gates 105 and 106 are high and hence, both outputs of these gates will be low. Therefore, the condition of gates 103 and 107 cannot be met. and the output of both these gates are high. The output from gate 103 after passing through inverter 104 provides a;ow Writel# signal. Theoutputof gate 107 will be high, and after passing through Inverter 108, a low signal Is 12 1 present on line 23. Thus, for this case of non-conflicting data: Writel and Wdte2 signals are high, and Writel# and Write2# signals are low.

The other case for non-conflicting data occurs when the Writel IN and Write21N signals are low. With the Writel IN signal low, the conditions of gate 106 are not met and a high input is applied to gate 106 from gate 107. The Write2#IN signal is high as is the output of the gate 109. Thusallthe conditions of gate 107 are met, and a low output will occur from this gate. This output, after passing through inverter 108, provides a high output on line 23.

Similarly, a high output occurs on line 22.

In the case of conflicting data, when a match occurs. the positive signal on either the Writel IN or Write21N line prevails and sets the flip-flop in a predetermined state (node 45 of the cell low). For example, if the Writel IN signal Is high, and the Write2IN signal low. the conditions of gate 106 are met and its output is low. This causes the output of gate 107 to be high and the output of gate 108 to be low. In essence, the high signal on the WriteMN fine is suppressed by gate 107 and hence. the conflicting data is suppressed. The same Is true if the Write21N signal is high and the Writel IN line is low. Then. the output of gate 105 is low and gate 103 suppresses the high Writel #IN signal.

Therefore the conflicting data is resolved so as to set the cell in a predetermined state.

Thus, a memory has been described which permits a read-modify-write cycle operation In a single memory cycle.

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Claims (12)

1. In a memory having a bistable memory cell with a pair of nodes, said memory including a pair of first lines, each of said nodes being coupled to one of said first lines through a transistor, where the state of said cell is sensed on said first fines when said transistors are caused to conduct, an Improvement comprising:

a pair of second lines coupled to said nodes for writing data Into said cell independently of said first lines.

2. The improvement defined by Claim 1 wherein said transistors can isolate said second lines from said first lines.

3. In a memory array having a plurality of static memory cells, pairs of complementary bit lines, and pairs of field-effect transistors, where each of said transistors have a first and second region and a gate, each of said bit lines being coupled to one of said cells by having said first region of one of said transistors, coupled to said one of said cells and said second region of said one of said transistors coupled to said bit line, and where the gates of said transistors are coupled to word lines in said memory, and further, where data Is read from said cells by first precharging said bit lines, an improvement comprising:

palm of second lines coupled to said cells at said first regions of said transistom, and wrfting means for coupling data to said second lines to write data Into said cells.

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4. The improvement defined by Claim 3 wherein said precharge on said bit lines is undisturbad by said writing means when data is written into said cells.

5. The improvement defined by Claim 4 wherein said second lines couples complementary data signals to said cells during said writing.

6. The improvement defined by Claim 5 wherein each of said second lines is coupled to said first region of said transistor through second and third field-effect transistors coupled in series, the gate of said second transistor being coupled to one of said second lines, the gate of said third transistor being coupled to receive an extended word fine signal.

7. An Improvement in a static memory where a first node of a memory cell is coupled to a bit line through a transistor to sense data in said cell when said transistor is caused to conduct, comprising:

a write line coupled to said first node, writing means coupled to said write fine for writing data into said cell, independently of said bit line.

8. The Improvement defined by Claim 7 wherein said coupling of said write line to said first node comprises:

a second and a third transistor coupled In series between sald node and a fixed potential, said gate of said second transistor being coupled to said write One and the gate of said third transistor being coupled to receive an extended word line signal.

9. In a memory having at least one bistable memory cell coupled to a bit line in said memory through a first transistor, the gate of said first transistor being coupled to a word line, an improvement comprising:

a write line for receiving data to be written into said cell, switching means for coupling said cell to said write line, and, timing means for controlling said switching means during a read-modify write memory operation occuring in a single memory cycle such that said write line is coupled to said cell after the state of said cell has been sensed and such that said write line is decoupled from said cell before said word line potential Is asserted for the next memory cycle following said single memory cycle.

10. The Improvement defined by Claim 9 wherein said timing means includes an extended word line generator coupled to said word line for 1 providing a first signal when said word line is selected, said first signal being 15 coupled to said switching means.

11. The improvement defined by Claim 10 wherein said generator Is reset so as to change the state of said first signal at the beginning of each memory cycle.

12. The Improvement defined by Claim 11 wherein said switch means comprises a second and third transistors, coupled In series between sald cell and a reference potential. the gate of said second transistor being coupled to said write fine and the gate of said third transistor being coupled to receive said 25 AM signal.

16 Published 1991 Sales Branch. Unit& Nat'he Patent O'lle, State House. 66171 High Holborn. LondonWC1R47P. Furthercoples may be obtained from Am Mile Point. C-mfelinfach. Cross Keys. N NPI 7HZ. Printed by Multiplex techniques lid, St Mary Cray. Rent.

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