AU2003300120A1 - Wordline latching in semiconductor memories - Google Patents

Wordline latching in semiconductor memories

Info

Publication number
AU2003300120A1
AU2003300120A1 AU2003300120A AU2003300120A AU2003300120A1 AU 2003300120 A1 AU2003300120 A1 AU 2003300120A1 AU 2003300120 A AU2003300120 A AU 2003300120A AU 2003300120 A AU2003300120 A AU 2003300120A AU 2003300120 A1 AU2003300120 A1 AU 2003300120A1
Authority
AU
Australia
Prior art keywords
wordline
latching
semiconductor memories
memories
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003300120A
Other languages
English (en)
Inventor
Alan Gieseke
William A. Mcgee
Ognjen Milic-Strkalj
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2003/020872 external-priority patent/WO2004006261A2/en
Priority claimed from PCT/US2003/021282 external-priority patent/WO2004013908A1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2003300120A1 publication Critical patent/AU2003300120A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Static Random-Access Memory (AREA)
AU2003300120A 2003-07-02 2003-12-30 Wordline latching in semiconductor memories Abandoned AU2003300120A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
PCT/US2003/020872 WO2004006261A2 (en) 2002-07-02 2003-07-02 Wordline latching in semiconductor memories
AU2003281431 2003-07-02
AU2003256458 2003-07-09
PCT/US2003/021282 WO2004013908A1 (en) 2002-08-02 2003-07-09 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
PCT/US2003/041683 WO2005013282A1 (en) 2003-07-02 2003-12-30 Wordline latching in semiconductor memories

Publications (1)

Publication Number Publication Date
AU2003300120A1 true AU2003300120A1 (en) 2005-02-15

Family

ID=34118088

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2003300120A Abandoned AU2003300120A1 (en) 2003-07-02 2003-12-30 Wordline latching in semiconductor memories
AU2003300121A Abandoned AU2003300121A1 (en) 2003-07-02 2003-12-30 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU2003300121A Abandoned AU2003300121A1 (en) 2003-07-02 2003-12-30 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits

Country Status (7)

Country Link
JP (1) JP2007521630A (ja)
KR (1) KR101029384B1 (ja)
CN (1) CN1802738A (ja)
AU (2) AU2003300120A1 (ja)
DE (1) DE10394263B4 (ja)
GB (1) GB2420015A (ja)
WO (2) WO2005013282A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011044589A (ja) * 2009-08-21 2011-03-03 Oki Semiconductor Co Ltd 半導体素子および半導体素子の製造方法
JP6486137B2 (ja) * 2015-02-16 2019-03-20 キヤノン株式会社 半導体装置の製造方法
JP7069605B2 (ja) * 2017-08-29 2022-05-18 富士電機株式会社 半導体装置の製造方法
US11250895B1 (en) 2020-11-04 2022-02-15 Qualcomm Incorporated Systems and methods for driving wordlines using set-reset latches

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2239541B (en) * 1989-12-29 1994-05-18 Intel Corp Dual port static memory with one cycle read-modify-write operation
US5031141A (en) * 1990-04-06 1991-07-09 Intel Corporation Apparatus for generating self-timing for on-chip cache
JPH0574167A (ja) * 1991-09-17 1993-03-26 Nec Corp 半導体記憶装置
JPH05121369A (ja) * 1991-10-24 1993-05-18 Oki Electric Ind Co Ltd 半導体装置のコンタクトホールエツチング方法
JPH05267251A (ja) * 1992-03-18 1993-10-15 Oki Electric Ind Co Ltd 半導体装置におけるコンタクトホールの形成方法
JP3086747B2 (ja) * 1992-05-07 2000-09-11 三菱電機株式会社 半導体装置およびその製造方法
US5530677A (en) * 1994-08-31 1996-06-25 International Business Machines Corporation Semiconductor memory system having a write control circuit responsive to a system clock and/or a test clock for enabling and disabling a read/write latch
JPH08316320A (ja) * 1995-05-22 1996-11-29 Nec Corp 半導体装置の製造方法
JPH10154752A (ja) * 1996-11-21 1998-06-09 Ricoh Co Ltd 半導体装置の製造方法
US5994780A (en) * 1997-12-16 1999-11-30 Advanced Micro Devices, Inc. Semiconductor device with multiple contact sizes
JP2001044441A (ja) * 1999-07-29 2001-02-16 Sony Corp 完全空乏ｓｏｉ型半導体装置及び集積回路
DE10054109C2 (de) * 2000-10-31 2003-07-10 Advanced Micro Devices Inc Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist
JP2003045963A (ja) * 2001-07-30 2003-02-14 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
GB2420015A (en) 2006-05-10
AU2003300121A1 (en) 2005-02-15
WO2005013282A1 (en) 2005-02-10
KR101029384B1 (ko) 2011-04-15
KR20060119856A (ko) 2006-11-24
GB0601531D0 (en) 2006-03-08
WO2005013357A1 (en) 2005-02-10
CN1802738A (zh) 2006-07-12
DE10394263T5 (de) 2006-04-27
DE10394263B4 (de) 2011-05-26
JP2007521630A (ja) 2007-08-02

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase