WO2005006694A1 - タイミング抽出装置及び方法並びにそのタイミング抽出装置を備えた復調装置 - Google Patents
タイミング抽出装置及び方法並びにそのタイミング抽出装置を備えた復調装置 Download PDFInfo
- Publication number
- WO2005006694A1 WO2005006694A1 PCT/JP2004/008246 JP2004008246W WO2005006694A1 WO 2005006694 A1 WO2005006694 A1 WO 2005006694A1 JP 2004008246 W JP2004008246 W JP 2004008246W WO 2005006694 A1 WO2005006694 A1 WO 2005006694A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- signal
- timing
- extraction device
- timing extraction
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
- H04L27/2276—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using frequency multiplication or harmonic tracking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
Definitions
- timing extracting device and method A timing extracting device and method, and a demodulating device provided with the timing extracting device
- the present invention provides a demodulation method for demodulating a digital modulation method such as a PSK (Pose Shift Keying) method or a QAM (Quadrature Amplitude Modulation) method used in digital satellite TV broadcasting or digital cable TV broadcasting.
- a digital modulation method such as a PSK (Pose Shift Keying) method or a QAM (Quadrature Amplitude Modulation) method used in digital satellite TV broadcasting or digital cable TV broadcasting.
- the present invention relates to a timing extracting device and a timing extracting method for extracting a timing required for a timing.
- Patent Document 1 Japanese Patent No. 2555140 (Patent Document 1). Some are described.
- a frequency component that is a half of the symbol rate fs existing in a digital modulation signal in accordance with a change in symbol data is nonlinearly processed, and a frequency component of fs is extracted.
- timing extraction can be performed stably without being affected by the carrier frequency offset caused by the frequency error of the local oscillator used on the receiver side.
- the frequency component of fs is finally extracted, it is necessary to operate at a sampling frequency exceeding 2 fs to satisfy the sampling theorem in digital noise signal processing.
- the sampling frequency is set to 4fs or more.
- the fs / There is a timing extraction method that extracts the frequency components of 2 and performs a solid-state process, a frequency shift process, and a double-size process on the extracted frequency components.
- another conventional timing component extraction method for example, as described in Japanese Patent Application Laid-Open No.
- Patent Document 1 requires digital signal processing at a sampling frequency of 4 fs in order to stably extract timing. For this reason, when the symbol rate is a high frequency, it is difficult to realize hardware or power consumption increases. In addition, even if the symbol rate is low, there is a disadvantage that the amount of processing per unit time increases when the processing is realized by the DSP.
- Patent Document 2 in order to perform vectorization processing, an influence of a carrier frequency offset caused by a frequency error of a local oscillator used on a receiver side is received. If there is an offset, accurate timing extraction becomes difficult. Furthermore, in the extraction method described in Patent Document 3, since the sampling frequency is 2 fs, the extracted signal causes interference due to the sampling theorem, and stable timing extraction cannot be performed. Disclosure of the invention
- the present invention has been made to solve the above-mentioned problem, and an object of the present invention is to perform hardware processing while performing digital signal processing at a low sampling frequency of 2 fs even when the symbol rate fs is high. It is an object of the present invention to provide a stable timing extraction method free of interference and without being affected by a carrier frequency offset.
- the symbol rate of the digitally modulated signal is fs, and the symbol rate is comprised of an I signal and a Q signal.
- the timing extraction device of the present invention is a timing extraction device for extracting a determination timing component of a symbol from a digital modulation signal having a symbol rate of fs, and from a I signal and a Q signal obtained from the digital modulation signal.
- Frequency conversion means for frequency-converting the positive and negative frequency components having a half value of fs contained in the complex baseband signal into a frequency position fm (0 ⁇ I fm I ⁇ fs / 2); and Nonlinear processing means for at least squaring each of the I signal and the Q signal after frequency conversion by the means, and extracting a frequency component twice the frequency position fm as a timing signal from an output signal of the nonlinear processing means Frequency extracting means for performing the operation.
- the frequency conversion unit converts a frequency component that is an aliasing distortion component with respect to a frequency component twice as high as the frequency position fm included in an output signal of the nonlinear processing unit. It is characterized by including filtering means for removing in advance from the complex baseband signal.
- the frequency conversion unit includes a first frequency shift unit that shifts the frequency of the complex baseband signal in a frequency increasing direction. Second frequency shift means for shifting the frequency of the complex baseband signal in a frequency decreasing direction.
- the frequency conversion means includes frequency shift means for shifting the frequency of the complex baseband signal by a frequency of fsZ2 in a frequency increasing direction and a frequency decreasing direction.
- the frequency conversion unit includes a bandpass filtering unit that extracts positive and negative frequency components of the 1Z2 value of fs included in the complex baseband signal. .
- the frequency conversion unit may determine whether the frequency is converted to the frequency position fm by a positive or negative frequency component of a half value of fs every two samplings.
- the timing extracting apparatus according to the present invention is characterized in that the non-linear processing means is configured to perform a frequency conversion by the frequency converting means.
- Two multiplication means for squaring the I signal and the Q signal, an adder for adding the I signal and the Q signal squared by the multiplication means, and a bit shift for halving the output of the adder
- a selecting means for selecting one of the output of the adder and the output of the bit shift means.
- the first and second frequency shift means include a filtering means for previously removing an interference component existing at the frequency position fm.
- the frequency conversion means performs complex addition on outputs of the first and second frequency shift means.
- the timing extraction method of the present invention is a timing extraction method for extracting a determination timing component of a symbol from a digital modulation signal having a symbol rate of fs, comprising a I signal and a Q signal obtained from the digital modulation signal.
- the positive and negative frequency components of the 1Z2 value of fs included in the complex baseband signal are frequency-converted to a frequency position fm (0 ⁇ Ifm
- Each of the Q signals is at least squared, the squared I signal and the Q signal are added, and thereafter, a frequency component twice the frequency position fm is extracted as a timing signal from the added signal. It is characterized.
- a demodulation apparatus includes an antenna for receiving a digital modulation signal, and a quasi-synchronous detection for quadrature detecting the digital modulation signal received by the antenna to obtain a complex baseband signal including an I signal and a Q signal.
- the digital base complex signal obtained by the AD converter is demodulated data sampled at a sampling frequency of 2 fs.
- the frequency position obtained by frequency-converting the positive and negative frequency components of fs / 2 of the complex baseband signal is calculated from the half value of the fm force symbol rate fs.
- the sampling theorem implies that the positive and negative frequency components of fs / 2 at this frequency position fm do not interfere with aliasing components and reduce power consumption. Is possible.
- the frequency component of fs is also extracted by nonlinear processing called square processing, so it is affected by the carrier frequency offset.
- the complex multiplication performed by the frequency conversion means in the frequency calculation means can be performed by the bit shift means and the selection means of the non-linear processing means. Can be reduced. Furthermore, in the present invention, since the timing extraction device only needs to output the timing signal once every L times, the amount of calculation per unit time of the timing error detector and loop filter used in the subsequent stage is greatly reduced. Is done. Brief Description of Drawings
- FIG. 1 is a block diagram showing a configuration of a demodulation device employing a timing extraction method according to a first embodiment of the present invention.
- FIG. 2 is a block diagram illustrating a specific configuration example of the timing extracting unit used in the first embodiment.
- FIG. 3 is a frequency characteristic diagram for explaining the operation principle of the frequency conversion unit used in the first embodiment
- FIG. 3A is a diagram showing a spectrum of a complex baseband signal after rate conversion
- Fig. (B) shows the frequency conversion of the soil fs / 2 frequency component to the soil fs / 4 frequency position
- Fig. (C) shows that the soil fs / 4 frequency component is converted into a DC component and a soil fs / 2 frequency component. It is a figure showing a situation where it was converted.
- FIG. 4 is a block diagram illustrating a specific configuration example of the frequency conversion unit used in the first embodiment.
- FIG. 5 is a frequency characteristic diagram for explaining the operation of the frequency converter used in the first embodiment.
- FIG. 5A shows one fs / 2 frequency component of the complex baseband signal as one fs / 4.
- Figure (b) shows the frequency conversion of the + fs / 2 frequency component to the 1 fs / 4 frequency position.
- Figure (c) shows the frequency characteristics of the first complex filter.
- FIG. 3D is a diagram illustrating the frequency characteristic of the second complex filter.
- FIG. 6 is a block diagram showing a specific configuration example of the earth fs / 4 shift unit used in the first embodiment. It is a lock figure.
- FIG. 7 is a block diagram showing a specific configuration example of a complex filter used in the first embodiment.
- Fig. 8 is a waveform diagram showing the relationship between the timing signal and the sampling point.
- Fig. 8 (a) shows the case where the sampling timing is late
- Fig. 8 (b) shows the case where the sampling timing is early. is there.
- FIG. 9 is a block diagram illustrating a specific configuration example of a frequency conversion unit used in the second embodiment.
- FIG. 10 is a frequency characteristic diagram for explaining the operation of the frequency conversion unit used in the second embodiment.
- FIG. 10 (a) shows one fs / 2 frequency component of the complex baseband signal at the zero frequency position.
- the figure (b) shows the frequency characteristics of the + fs / 2 frequency component at the 0 frequency position, the figure (c) shows the frequency characteristics of the LPF, and the figure (d) shows the frequency characteristics of the LPF.
- FIG. 9 is a diagram illustrating another frequency characteristic.
- FIG. 11 is a block diagram showing a specific configuration example of the frequency conversion unit used in the third embodiment.
- FIG. 12 is a block diagram illustrating a specific configuration example of a timing extracting unit used in the fourth embodiment.
- FIG. 13 is a block diagram illustrating a specific configuration example of the frequency conversion unit used in the fourth embodiment.
- FIG. 14 is a block diagram illustrating a specific configuration example of a timing extracting unit used in the fifth embodiment.
- FIG. 15 is a block diagram illustrating a specific configuration example of the frequency conversion unit used in the fifth embodiment.
- FIG. 16 is a waveform diagram showing a relationship between a timing output signal of a timing extracting unit used in the fifth embodiment and a sample point.
- FIG. 17 is an input / output characteristic diagram showing a specific error function example of the timing error detector.
- FIG. 18 is a diagram illustrating an entire configuration of a demodulation device using a voltage controlled oscillator used in the sixth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram illustrating a configuration of a demodulation device that demodulates a digital modulation signal such as a QPSK (Quadrature PS) signal or a QAM signal employing the timing extraction method according to the first embodiment of the present invention.
- a digitally modulated signal is received by an antenna 101.
- Downconverter 102 frequency-converts a signal received by antenna 101 to a desired intermediate frequency band, and outputs the converted signal.
- a quasi-synchronous detector (quasi-synchronous detection means) 103 performs orthogonal detection at a fixed oscillation frequency of the local oscillator 104, and outputs both in-phase and quadrature components.
- Low-pass filters (LPF) 105 and 106 remove harmonic components from the complex baseband signal composed of the in-phase component and the quadrature component from the quasi-synchronous detector 103 and output the result.
- AD converters (AD conversion means) 107 and 108 sample the complex baseband signals from the LPFs 105 and 106 using a clock signal exceeding twice the symbol rate fs, and convert the complex baseband signals from analog values to digital values. Convert to
- the rate converter 109 performs rate conversion of the digital-valued complex baseband signals from the AD converters 107 and 108 based on a timing control signal 110a output from a timing control unit 110 described later, and at a sampling rate of 2 fs. Output.
- Digital filters (RX-FIL) 111 and 112 receive the signals subjected to the rate conversion by the rate converter 109, shape the spectrum so as to prevent inter-symbol interference in digital data transmission, and output the signals.
- the waveform equalizer 113 equalizes the waveform of a ghost due to reflection or the like generated in the transmission path and outputs the result.
- Synchronous detector 114 corrects the carrier frequency offset and outputs demodulated data.
- the timing control unit 110 inputs a complex baseband signal composed of an in-phase signal (I) and a quadrature signal (Q) sampled at 2 fs after rate conversion by the rate converter 109, and outputs a timing control signal 110a Is output to the rate converter 109, and forms a feedback loop including the rate converter 109.
- the timing control unit 110 includes a timing extraction unit 20, a timing error detection unit 21, and a loop filter 22.
- the timing extractor (timing extractor) 20 extracts a symbol determination timing component from the complex baseband signal output by the rate converter 109 and outputs the extracted component to the timing error detector 21.
- FIG. 2 shows a specific configuration example of the timing extraction unit 20.
- the timing extraction unit 20 includes a frequency conversion unit 30, two multipliers (multiplication means) 31, 32, an adder (addition means) 33, and a band-pass filter (BPF).
- FIG. 3A shows the spectrum of the complex baseband signal after the rate conversion.
- the dashed line indicates the spectrum of the digital modulation signal
- the solid line indicates the frequency component of the earth 2 that exists as the data of the digital modulation signal changes at the symbol rate fs.
- the frequency conversion section 30 receives the complex baseband signal from the rate conversion section 109, and converts the frequency component of the earth fs / 2 to the frequency component of the other frequency domain so as not to interfere with the frequency components in other frequency domains as shown in FIG. The frequency is converted to the indicated fsZ4.
- the I signal and the Q signal constituting the complex baseband signal are squared (non-linear processing) by a non-linear processing unit (non-linear processing means) 40 composed of two multipliers 31, 32 and an adder 33, respectively. Is done. That is, the I signal and the Q signal are squared by the multipliers 31 and 32, respectively, and nonlinear processing of adding the squared results by the adder 33 is performed.
- the frequency component of the soil fsZ4 is converted into the DC component and the frequency component of the soil fsZ2 by nonlinear processing as shown in FIG. 3 (c).
- the BPF34 has a pass center frequency having the frequency characteristic of soil fsZ2 as shown by the broken line in Fig.
- the frequency conversion unit 30 includes a + fsZ4 shift unit 301, an fsZ4 shift unit 302, first and second complex filters (filtering means) 303 and 304, and a complex adder 305.
- the operation of the frequency conversion unit 30 will be described with reference to FIG.
- the complex baseband signal is input to + fsZ4 shift section 301 and one fsZ4 shift section 302.
- the + fsZ4 shift section 301 shifts the complex baseband signal by + fs / 4 frequency, and converts one fs / 2 frequency component of the complex baseband signal shown in FIG. 3 (a) as shown in FIG. 5 (a). Then, the frequency is converted to a frequency position of 1 fs / 4 and supplied to the first complex filter 303.
- the internal configuration of the + fs / 4 shift unit 301 is shown, for example, in FIG. In the figure, + fs / 4 shift section 301 includes a complex multiplier 3011 and a sine / cosine signal generator 3012.
- Complex multiplier 3011 performs complex multiplication of the complex baseband signal and the output signal of sine-cosine generator 3012.
- Complex multiplier 3011 performs complex multiplication of the complex baseband signal and the output signal of sine-cosine generator 3012.
- one fsZ4 shift section 302 shifts the complex baseband signal by one fs / 4 frequency, and shifts the + fsZ2 frequency component of the complex baseband signal to the + fs / 4 frequency as shown in FIG. 5 (b).
- the frequency is converted to the position and supplied to the second complex filter 304.
- the internal configuration of the 1 fs / 4 shift section 302 is also the same as that shown in FIG.
- (1, Q) (1, 0), ⁇ , — l / f2, (0, —1), (1 1 2, _1 / ⁇ 2), (_ 1, 0), [1 l / f2 , 1 2), (0, 1), l / f2, 1Z 2) I signal and taking, by supplying sequentially repeating the complex multiplier 301 E Q signals, a frequency
- the first complex filter 303 passes at least one fs / 4 frequency, and sets the + fsZ4 frequency so as not to interfere with the frequency component of + fsZ4 output from the second complex filter 304 in frequency. It has a frequency characteristic of blocking and ⁇ 3 fs, 4 frequencies, which are aliasing distortion components of the frequency of soil fs / 2 after the non-linear processing in the subsequent stage.
- the complex baseband signal filtered according to this characteristic is This is supplied to the complex adder 305.
- This filtering operation involves the operation of passing the frequency of ⁇ fs 2 in the complex baseband frequency component input to the frequency conversion unit 30, blocking the 0 frequency, and blocking the frequencies of + fsZ2 and the earth fs. Become.
- the internal configuration of the first complex filter 303 is shown, for example, in FIG.
- the first complex filter 303 has a configuration including three complex delay units 41, 42, 43, four complex computing units 44, 45, 46, 47, and a complex adder 48.
- the complex delay devices 41 to 43 delay the complex baseband signal according to the sampling clock frequency 2fs.
- the complex adder 305 outputs the sum of the complex arithmetic units 44 to 47.
- the complex filter 304 passes at least the frequency of + fsZ4 and does not interfere with the frequency component of 1 fs / 4 output from the first complex filter 303 in frequency!
- the second complex filter 304 has an internal configuration shown in FIG.
- the complex adder 305 in FIG. 4 performs complex addition on the complex baseband signal obtained by the above-described processing. As a result, the complex addition output is combined with the frequency-converted complex baseband signal to the frequency position of fs / 4 so that the frequency component of the digital modulation wave does not interfere with the frequency component of fsZ2. Become. Next, returning to FIG.
- the multipliers 31 and 32 of the nonlinear processing unit 40 are configured to output the complex baseband signal, which is the power of the I signal and the Q signal output from the complex adder 305 of the frequency conversion unit 30 of FIG.
- Each of the I and Q signals is squared and output.
- the adder 33 adds the squared signal and supplies it to the BPF.
- the sum-of-squares processing in the non-linear processing unit 40 is a non-linear processing method that has been conventionally used, and includes phase uncertainty between 0 degrees and 180 degrees of a frequency component due to a symbol change and offset of a carrier frequency. Cancel the effect.
- the frequency offset caused by the + fs / 4 shift section 301 and the ⁇ fs / 4 shift section 302 of the frequency conversion section 30 in FIG. 4 due to the sampling frequency and the time lag are cancelled. 2
- the BPF 34 extracts the frequency component of the soil fsZ2 from the addition result signal from the adder 33 of the nonlinear processing unit 40, and uses the extracted frequency component as a timing signal to detect the timing error shown in FIG. Output to the container 21.
- FIG. 8 is a waveform chart showing the relationship between the timing waveform and the sample points.
- curve A shows the case of the correct sampling timing
- curve B in the figure (a) shows the case where the sampling timing is late
- curve C in the figure (b) shows the sampling timing Indicates the earlier case.
- FIG. 17 shows the error function of the timing error detector 21.
- the timing error detector 21 has, for example, a counter that counts four samples as pseudo-synchronization avoidance means, analyzes four samples of the sampling clock frequency 2fs as one cycle, When the input phase is between ⁇ / 2 to ⁇ and 1 ⁇ / 2 to 1 ⁇ , the characteristics are as shown by the broken line or the dashed line.
- a signal quality detection means such as a BER measurement device or a CZN detector
- the loop filter 22 smoothes the timing error signal from the timing error detector 21 and outputs it to the rate conversion section 109 as a timing control signal 110a.
- the timing can be stably extracted at the sampling clock frequency of 2fs without being affected by the carrier frequency offset.
- the + fsZ2 frequency component of the complex baseband signal input to the frequency conversion unit 30 is frequency-converted to the + fsZ4 frequency position, and the 1 fs / 2 frequency component is shifted to the _fs / 4 frequency position.
- the present invention is not limited to this.
- the frequency component of + fs / 2 is shifted to one fs / 4 frequency so that interference does not occur in the frequency component. It is needless to say that the same effect can be obtained even if the frequency is converted to the same frequency and the frequency component of one fs / 2 is converted to the frequency arrangement reverse to the + fsZ4 frequency position.
- FIG. 9 shows a configuration of the frequency conversion section 30 of the present embodiment.
- the same parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
- different parts will be mainly described.
- the complex baseband signal is shifted by + fsZ2 in the frequency increasing direction in the + fsZ2 shift section (first frequency shifting means) 306, and conversely, the frequency is shifted by 1 fs / 2 in the frequency decreasing direction.
- the second fs / 2 shift unit (second frequency shift means) 307 is input.
- the + fsZ2 shift unit 306 shifts the complex baseband signal by + fsZ2 frequency, and one fs / 2 frequency component of the complex baseband signal shown in FIG. 3A is shown in FIG. 10A.
- the frequency is converted to the position of the zero frequency and supplied to the LPF 308.
- the fsZ2 shift unit 307 shifts the complex baseband signal by one fsZ2 frequency and frequency-converts the + / 2 frequency component of the complex baseband signal to the 0 frequency position as shown in Fig. 10 (b). And supply it to PF309.
- LPF 308 and LPF 309 are filters having a frequency characteristic of passing zero frequency and blocking each frequency component of fs / 2 and soil fs, as shown in FIG. 10 (c).
- the obtained complex baseband signals are supplied to one fsZ4 shift section (second frequency shift means) 310 and + fs / 4 shift section (first frequency shift means) 311 respectively. Since the LPF 308 and the LPF 309 have the same frequency characteristics, they have the same configuration. Further, the I signal and the Q signal input to each of the LPFs 308 and 309 can perform independent and identical filtering processing because the frequency characteristics of the LPF are positive and negative symmetric with respect to the zero frequency.
- the filtering operation of the LPF 308 is an operation in which the frequency component of the complex baseband signal input to the frequency conversion unit 30 passes the frequency of 1 fsZ2 and blocks the 0 frequency, + fs / 2, and the fs frequency. It is.
- the filtering operation of the other LPF 309 in the frequency component of the complex baseband signal input to the frequency conversion unit 30, the frequency of + fsZ2 is passed, and the frequency of 0 frequency, 1 fs / 2 and ⁇ fs is blocked. Operation. Further, in FIG.
- one fs / 4 shift unit 310 shifts the zero frequency component to the frequency position of one fsZ4, shifts the null frequency component of fs to the frequency position of 3fsZ4, and obtains the null frequency component of fs / 2. Is shifted to the frequency position of.
- + fs, 4 shift section 311 shifts the 0 frequency component to the frequency position of fsZ4, shifts the 1 fs null frequency component to the 13fs / 4 frequency position, and shifts the 1 fsZ2 null frequency component. Shift to one fs, 4 frequency position.
- the complex adder 305 performs a complex addition on the outputs of the one fs / 4 shift unit 310 and the + fsZ4 shift unit 311.
- the complex added output is frequency-converted to the frequency position of soil fsZ4 to prevent interference with the frequency component of digital modulation wave fsZ2 and frequency components of other frequency domains. It becomes a complex baseband signal having ⁇ 3/4, which is the aliasing distortion component of 4, and a null frequency component.
- the two LPFs 308 and LPF 309 have the same configuration, and the I side and the Q side of each LPF 308 and 309 are independent and identical to each other.
- the circuit is simplified because of the filtering processing configuration. Other specific effects are the same as in the first embodiment.
- the frequency component of the earth fs of the complex baseband signal input to the frequency conversion unit 30 is not changed so that the frequency component of the earth fs / 4 does not cause interference.
- the same effect can be obtained even if the frequency is converted to the reverse frequency arrangement.
- FIG. 11 shows a configuration of the frequency conversion unit 30 of the present embodiment. Note that, in FIG. 11, the same portions as those in FIGS. 4 and 9 are denoted by the same reference numerals, and description thereof will be omitted.
- a complex baseband signal is input to a BPF (bandpass filtering means) 312.
- the BPF 312 has a pass center frequency having a frequency characteristic of fsZ2, receives a complex baseband signal, extracts a frequency component of fs / 2, and outputs a + fsZ2 shift unit 306 and a _fsZ2 shift unit 307.
- Output to The +2 shift unit 306 frequency-shifts the complex baseband signal by + fs / 2, frequency-converts one fsZ2 frequency component to a zero frequency position, and shifts the + fsZ2 frequency to a fs frequency position. Convert and output to LPF313.
- the 12 shift unit 307 shifts the frequency by ⁇ fs / 2, converts the frequency component of + fsZ2 to the position of 0 frequency, and converts the frequency component of 1fsZ2 to the position of 1 fs frequency. , And output to LPF309.
- LPF 313 and LPF 314 are filters having a frequency characteristic of passing the zero frequency and blocking the frequency of the earth fs as shown in FIG. 10 (d) .
- the complex baseband signal filtered according to this characteristic is Output to one fs / 4 shift section 310 and + fs / 4 shift section 311 respectively.
- the —fs / 4 shift unit 310 shifts the zero frequency component to one fs / 4 frequency position, and shifts the fs null frequency component to 3fs / 4 frequency position.
- + fsZ4 shift section 311 shifts the zero frequency component to the frequency position of fsZ4 and shifts the null frequency component of one fs to the frequency position of _3fs / 4.
- the complex adder 305 performs a complex addition on both outputs of the ⁇ fs / 4 shift unit 310 and the fsZ4 shift unit 311. As a result, this complex addition output is frequency-converted to the frequency position of earth fsZ4 so that the frequency component of the digitally modulated wave fsZ2 does not interfere with the frequency components of other frequency regions, and the frequency is converted by nonlinear processing in the subsequent stage.
- the frequency component of soil fsZ2 is extracted by BPF312. Therefore, unnecessary frequency signal components can be removed in advance, and timing can be more stably extracted. Other specific effects are similar to those of the first embodiment.
- the frequency component of fs / 2 of the complex baseband signal input to the frequency conversion unit 30 is set to the frequency opposite to that of the earth fsZ4 so that the frequency component does not interfere with the frequency component. It goes without saying that the same effect can be obtained even if the frequency is converted to the arrangement.
- FIG. 12 shows a configuration of the timing extracting section 20 of the present embodiment.
- the timing extraction unit 20 uses a frequency conversion unit 35 instead of the force frequency conversion unit 30 which is the same as the input / output signal in the first to third embodiments described above.
- the difference is that a bit shifter (bit shift means) 36 and a selector (selection means) 37 are inserted after the adder 33 in the nonlinear processing section 40 '.
- bit shifter bit shift means
- selector selection means
- FIG. 13 shows a configuration of the frequency conversion unit 35.
- the frequency converter 35 is slightly different from the configuration of the frequency converter 30 shown in FIG. 13, the same parts as those in FIG. 11 are denoted by the same reference numerals, and different parts will be described here.
- (1, Q) (1, 0), (1, 1 1), (0, 1 1), (1 1, 1 1), (1 1, 0), (1 1 , 1), (0, 1), (1, 1)
- the I signal and Q signal are successively multiplied by complex multiplication.
- control signal generator 317 uses ⁇ ( ⁇ ) Is the value to be subjected to complex multiplication at the time of ⁇ sampling of the first numerical calculator 315, and ⁇ ( ⁇ ) is the value to be subjected to complex multiplication at the time of ⁇ sampling of the second numerical calculator 316.
- the complex multiplication of the numerical value and the complex baseband signal can be realized by a selector, a sign inversion, an adder or the like without using the complex multiplication.
- the squared value becomes 2 when squared. That is, the signal doubled by the frequency conversion unit 35 is squared after the squaring process, thereby obtaining the original signal.
- the signal is squared and then multiplied by 12 by the bit shifter 36, and the output of the bit shifter 36 and the output of the adder 33 are controlled by the control signal generator 317. Based on the timing of By selecting the output signal of the bit shifter 36 at the timing of the V " ⁇ 2 signal, and selecting the output of the adder 33 at the timing of the other signals, the timing extraction unit 20 shown in FIG.
- a configuration is adopted in which a signal multiplied by 1Z2 after the square operation and an output signal having a normal value are selected based on the control signal. Accordingly, the operation performed by the complex multiplier can be realized only by the adder 33, the bit shifter 36, and the selector 37, so that the circuit scale can be reduced.
- FIG. 14 shows a configuration of the timing extraction unit 20 of the present embodiment.
- the timing extractor 20 has the same input signal as that of FIG. 2 of the first embodiment described above, but uses a frequency converter 38 instead of the frequency converter 30.
- the difference is that a BPF 39 whose pass center frequency is the frequency characteristic of the earth fsZ4 is used instead of the BPF 34 of FIG.
- the same portions as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.
- FIG. 14 shows a configuration of the timing extraction unit 20 of the present embodiment.
- the timing extractor 20 has the same input signal as that of FIG. 2 of the first embodiment described above, but uses a frequency converter 38 instead of the frequency converter 30.
- a BPF 39 whose pass center frequency is the frequency characteristic of the earth fsZ4 is used instead of the BPF 34 of FIG.
- FIG. 14 the same portions as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be
- This frequency conversion unit 38 uses one fs / 8 shift unit 318 instead of one fsZ4 shift unit 310 shown in FIG. 11 and uses + fs instead of + fs / 4 shift unit 311.
- Use fs / 81 shift unit 319 Is different. 15, the same parts as those in FIG. 11 are denoted by the same reference numerals, and different parts will be described here.
- one fs / 8 shift section 318 shifts the frequency component generated due to the change of the symbol at the 0 frequency position to the frequency position of _fsZ8.
- + fs / 8 shift section 319 shifts the frequency component generated with the change of the symbol at the 0 frequency position to the frequency position of fsZ8.
- the complex adder 305 performs a complex addition on both outputs of the one fsZ8 shift unit 318 and the + fs / 8 shift unit 319, and performs the non-linear processing of the earth fsZ4 without causing the frequency component of the earth fsZ8 to interfere. It outputs a complex baseband signal with a null frequency component of ⁇ 7fsZ8, which is the aliasing distortion component of.
- two multipliers 31, 32 combine the I signal and the Q signal of the complex baseband signal composed of the I signal and the Q signal supplied from the complex adder 305 of the frequency conversion section 38 together. Each of them is squared, and the adder 33 performs the nonlinear processing by adding the signals after the squares.
- FIG. 16 shows a waveform representing the relationship between the timing signal and the sample interval.
- the force expressed by four samples for one cycle of the sine wave in FIG. 8 As shown in FIG. 16, eight sampling points are obtained for one cycle of the sine wave.
- a 1-sample data thinning-out signal obtained by thinning out the signal indicated by a black circle in the figure is output as a timing signal, so that the timing error detector 22 and the loop filter 22 at the subsequent stage use the thinned-out timing signal. It is possible to reduce the amount of computation per unit of time if the operation is performed. As described above, according to the present embodiment, it is possible to thin out the output data of the BPF 39, and to reduce the amount of computation per unit time of the timing error detector 22 and the loop filter 23 at the subsequent stage. Can be. Other specific effects are similar to those of the first embodiment.
- the frequency component of fs / 2 of the complex baseband signal which is the input of the frequency conversion unit 38, is inverted to the frequency fs / 8 of the complex baseband signal so that no frequency component interference occurs. It goes without saying that the same effect can be obtained even if the frequency is converted to the above frequency arrangement. Further, in the present embodiment, an example is shown in which the frequency of soil fs / 2 of the complex baseband signal input to the timing extraction unit 20 is frequency-converted to soil fsZ8, and the frequency component of soil fsZ4 is extracted after nonlinear extraction processing. The present invention is not limited to this.
- the frequency is converted to soil fsZ2M (M is an integer of 3 or more), and after nonlinear processing, the frequency of soil fsZM is extracted. Needless to say, the same effect can be obtained, and furthermore, it is not essential to use the integer value M in this way.
- the frequency of the earth fs / 2 included in the complex baseband signal is The frequency may be converted into fm (0 ⁇ I fm I fs / 2) so that the frequency component of the soil fs / 2 does not interfere with other frequency components.
- frequency conversion to ⁇ fs / (2 2 XL), nonlinear processing, and extraction of soil fs / (2 XL) (L is an integer of 3 or more) are performed.
- FIG. 18 shows another configuration example of the demodulation device including the timing extraction device of the present invention.
- the demodulator shown in FIG. 3 differs from the demodulator shown in FIG. 1 in that a DA converter 115 and a voltage-controlled clock oscillator 116 are used instead of the rate converter 109 shown in FIG.
- a feedback loop including a control unit 110, a DA converter 115, and a voltage-controlled clock oscillator 116, the configuration is such that timing control is performed.
- the demodulator shown in FIG. 18 will be briefly described with respect to the differences from FIG. 1.
- the AD converters 107 and 108 sample at a clock twice the symbol rate fs supplied from the voltage-controlled clock oscillator 116, and output the complex baseband. Convert signals from analog to digital values
- the AD converters 107 and 108 sample at a clock twice the symbol rate fs supplied from the voltage-controlled clock oscillator 116, and output the complex baseband. Convert signals from analog to digital values
- the timing control unit 110 receives the complex baseband signal, extracts the timing in the timing extraction unit 20, detects the error in the sample timing generated in the AD converters 107 and 108 in the timing error detector 21, and In step 22, the timing error is smoothed and output as a timing control signal.
- the DA converter 115 converts the timing control signal from the loop filter 22 from a digital signal to an analog signal.
- the voltage control clock oscillator 116 has a configuration in which the clock oscillation frequency can be controlled by the voltage value.
- the timing control signal from the DA converter 115 is input as a voltage value, and the frequency at which the timing control signal is stabilized is The clock is supplied to AD converters 107 and 108.
- the timing extracting apparatus and method of the present invention when extracting a symbol determination timing component from a digital modulation signal, the sampling frequency is set to a sampling frequency twice as high as the symbol rate fs.
- the timing component since it is possible to extract the timing component stably without being affected by the carrier frequency offset that causes interference with the aliasing distortion component, it can be used in digital satellite TV broadcasting and digital cable TV broadcasting. This is useful for applications such as demodulation of digital modulation.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/520,616 US7457375B2 (en) | 2003-07-11 | 2004-06-07 | Timing extractor, timing extraction method, and demodulator having the timing extractor |
JP2005511488A JP3873078B2 (ja) | 2003-07-11 | 2004-06-07 | タイミング抽出装置及び方法並びにそのタイミング抽出装置を備えた復調装置 |
EP04736273A EP1643705A4 (en) | 2003-07-11 | 2004-06-07 | STOPWATCH EXTRACTION DEVICE AND METHOD, AND DEMODULATION DEVICE USING THE TIMING EXTRACTION DEVICE |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003273698 | 2003-07-11 | ||
JP2003-273698 | 2003-07-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005006694A1 true WO2005006694A1 (ja) | 2005-01-20 |
Family
ID=34056033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/008246 WO2005006694A1 (ja) | 2003-07-11 | 2004-06-07 | タイミング抽出装置及び方法並びにそのタイミング抽出装置を備えた復調装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7457375B2 (ja) |
EP (1) | EP1643705A4 (ja) |
JP (1) | JP3873078B2 (ja) |
KR (1) | KR100676568B1 (ja) |
CN (1) | CN100546294C (ja) |
TW (1) | TWI252624B (ja) |
WO (1) | WO2005006694A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8009723B2 (en) * | 2006-06-02 | 2011-08-30 | Terrace Communications Corporation | Measurement of baseband timing in a spread spectrum communications system |
SG141257A1 (en) * | 2006-09-12 | 2008-04-28 | Oki Techno Ct Singapore Pte | Apparatus and method for demodulating a modulated signal |
JP2011035557A (ja) * | 2009-07-30 | 2011-02-17 | Panasonic Corp | シンボルレート検出器及び受信装置 |
US8965290B2 (en) * | 2012-03-29 | 2015-02-24 | General Electric Company | Amplitude enhanced frequency modulation |
WO2019044195A1 (ja) | 2017-08-31 | 2019-03-07 | 株式会社村田製作所 | 心拍測定装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05207082A (ja) * | 1992-01-27 | 1993-08-13 | Fujitsu Ltd | タイミング抽出方法 |
JPH06104558A (ja) * | 1992-09-18 | 1994-04-15 | Toyota Motor Corp | 配線基板に対する電子部品パッケージの取付構造 |
JPH06120935A (ja) * | 1991-02-18 | 1994-04-28 | Canon Inc | タイミング抽出装置 |
JPH07226781A (ja) * | 1994-02-15 | 1995-08-22 | Nippon Hoso Kyokai <Nhk> | 位相誤差検出回路およびクロック再生回路 |
JP2555140B2 (ja) * | 1988-04-05 | 1996-11-20 | 株式会社日立製作所 | サンプリング位相制御装置 |
JPH11127133A (ja) * | 1997-10-22 | 1999-05-11 | Matsushita Electric Ind Co Ltd | Cdma同期回路及びcdma同期信号検出方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6145658A (ja) | 1984-08-10 | 1986-03-05 | Nec Corp | タイミング位相制御方式 |
US5495203A (en) * | 1994-12-02 | 1996-02-27 | Applied Signal Technology, Inc. | Efficient QAM equalizer/demodulator with non-integer sampling |
US6295325B1 (en) * | 1997-11-14 | 2001-09-25 | Agere Systems Guardian Corp. | Fixed clock based arbitrary symbol rate timing recovery loop |
-
2004
- 2004-06-07 CN CNB2004800003381A patent/CN100546294C/zh not_active Expired - Fee Related
- 2004-06-07 EP EP04736273A patent/EP1643705A4/en not_active Withdrawn
- 2004-06-07 US US10/520,616 patent/US7457375B2/en not_active Expired - Fee Related
- 2004-06-07 KR KR1020047020095A patent/KR100676568B1/ko not_active IP Right Cessation
- 2004-06-07 JP JP2005511488A patent/JP3873078B2/ja not_active Expired - Fee Related
- 2004-06-07 WO PCT/JP2004/008246 patent/WO2005006694A1/ja active IP Right Grant
- 2004-06-29 TW TW093119045A patent/TWI252624B/zh not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2555140B2 (ja) * | 1988-04-05 | 1996-11-20 | 株式会社日立製作所 | サンプリング位相制御装置 |
JPH06120935A (ja) * | 1991-02-18 | 1994-04-28 | Canon Inc | タイミング抽出装置 |
JPH05207082A (ja) * | 1992-01-27 | 1993-08-13 | Fujitsu Ltd | タイミング抽出方法 |
JPH06104558A (ja) * | 1992-09-18 | 1994-04-15 | Toyota Motor Corp | 配線基板に対する電子部品パッケージの取付構造 |
JPH07226781A (ja) * | 1994-02-15 | 1995-08-22 | Nippon Hoso Kyokai <Nhk> | 位相誤差検出回路およびクロック再生回路 |
JPH11127133A (ja) * | 1997-10-22 | 1999-05-11 | Matsushita Electric Ind Co Ltd | Cdma同期回路及びcdma同期信号検出方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1643705A4 * |
Also Published As
Publication number | Publication date |
---|---|
TWI252624B (en) | 2006-04-01 |
EP1643705A1 (en) | 2006-04-05 |
EP1643705A4 (en) | 2010-05-19 |
CN100546294C (zh) | 2009-09-30 |
US7457375B2 (en) | 2008-11-25 |
KR20050042753A (ko) | 2005-05-10 |
TW200514347A (en) | 2005-04-16 |
KR100676568B1 (ko) | 2007-01-30 |
CN1698333A (zh) | 2005-11-16 |
JP3873078B2 (ja) | 2007-01-24 |
US20050253742A1 (en) | 2005-11-17 |
JPWO2005006694A1 (ja) | 2006-08-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108183877B (zh) | 一种基于fpga的多音调频信号解调方法 | |
CN101005480A (zh) | 解调电路和解调方法 | |
KR20010063060A (ko) | 잔류측파대 수신기 | |
KR100406224B1 (ko) | 주파수변조신호복조회로및이를채용한통신단말장비 | |
EP0924892A2 (en) | Circuit for reproducing bit timing and method of reproducing bit timing | |
US7970071B2 (en) | Method and device for synchronizing the carrier frequency of an offset quadrature phase-modulated signal | |
WO2005006694A1 (ja) | タイミング抽出装置及び方法並びにそのタイミング抽出装置を備えた復調装置 | |
KR20060031074A (ko) | Atsc 수신기에서의 결합된 심볼 타이밍 및 캐리어위상 복원 회로 | |
CN115632923A (zh) | 一种基于oqpsk的无人机与卫星超宽带通信方法及相关设备 | |
JP4277090B2 (ja) | キャリア周波数検出方法 | |
JP2931454B2 (ja) | ディジタル位相変調信号復調回路 | |
JP2540931B2 (ja) | Psk信号復調方法 | |
JPH0870332A (ja) | クロック再生装置 | |
JP4430073B2 (ja) | タイミング再生回路および受信装置 | |
JP2765601B2 (ja) | 復調回路 | |
JP4307746B2 (ja) | 搬送波再生回路および復調装置 | |
JP3088892B2 (ja) | データ受信装置 | |
Jankovic et al. | Extraction of in-phase and quadrature components by IF-sampling | |
JP3614540B2 (ja) | Psk変調信号評価装置 | |
JP2929366B2 (ja) | デジタルam復調器とその方法 | |
KR100451749B1 (ko) | 디지털 티브이 수신기의 클럭 복조 장치 | |
KR100459142B1 (ko) | 디지털 티브이의 심볼 클럭 복구 장치 | |
JP2943803B1 (ja) | 受信装置 | |
JP4803079B2 (ja) | 復調装置 | |
EP2797225B1 (en) | Method of and apparatus for demodulating an amplitude modulated signal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 2005511488 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020047020095 Country of ref document: KR Ref document number: 20048003381 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10520616 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004736273 Country of ref document: EP |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 1020047020095 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2004736273 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 1020047020095 Country of ref document: KR |