Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/01—Manufacture or treatment
  • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Definitions

• This invention relates to integrated circuits and more particularly to integrated circuits with a recess in the substrate.
• the recesses in the substrate occur primarily as a consequence of the substrate being exposed during the etching away of some portion of a layer of material that was over the substrate.
• An etchant is applied to the substrate for some amount of time during and/or after the layer that is being etched has been removed.
• One example is that there is a situation in which there is exposed substrate at the onset of an etch of another material in a different location.
• Another example is that a thin layer over the substrate is etched through during an etch of a material elsewhere so that the substrate becomes exposed part way through the etch of the material elsewhere.
• a layer over the substrate is being etched and after the substrate becomes exposed, the etch continues as an over-etch to ensure that the layer that is desired to be removed is completely removed.
• the etchant that is chosen desirably does not significantly etch semiconductor substrates, but as a practical matter such etchants are very difficult to work with. Consequently the layers that are desired to be removed are removed by an etchant that does have some etching effect on the semiconductor substrate, typically silicon. Such a process is shown in FIGs. 1-9.
• FIG. 1 Shown in FIG. 1 is a semiconductor device 10 useful in making an integrated circuit comprising a substrate 12, a polysilicon gate 14, an anti-reflective coating (ARC) 16 of nitride, and a thin oxide 18 which is between gate 14 and substrate 12 as well as extending in areas adjacent to gate 14.
• ARC 16 anti-reflective coating
• an etchant such as a halogen based material such as fluorine and chlorine, is used. These etchants also etch silicon although at not as fast a rate as nitride is etched.
• the result of removing ARC 16 is a recess surface 22 shown in FIG. 2.
• Shown in FIG. 3 is device 10 after formation of a sidewall spacer 24.
• Sidewall spacer 24 is formed of oxide and occurs as a result, as is commonly known, of applying a relatively conformal layer and subsequently etching it with an anisotropic etch. This causes a further recess in substrate 12 aligned with sidewall spacer 24.
• Shown in FIG. 4 is formation of source/drain region 26 and source/drain 28 using sidewall spacer 24 as a mask. This implant is commonly called the extension implant and has a relatively lower doping concentration than a subsequent heavy source/drain implant.
• Shown in FIG. 5 is device 10 after deposition of an oxide liner 30 and a nitride layer 32. Nitride layer 32 is then etched back as is liner 30 resulting in sidewall spacer 34 and liner portion 38.
• source/drain regions 26 and 28 diffuse, expanding the area of source/drain regions 26 and 28.
• FIG. 7 is device 10 after a heavy implant to form heavily-doped regions 40 and 42 using sidewall spacer 34 as a mask.
• FIG. 8 is continued expansion of source/drain regions 26 and 28 as well as diffusion of regions 40 and 42 due to standard processing.
• FIG. 9 Shown in FIG. 9 is device 10 after formation of suicide regions 48 and 50 which extend under regions 40 and 42. This also shows a completed diffusion of regions 49 and 51 , which are the remaining portions of regions 26 and 28. These regions may not extend all the way to gate oxide 20. With the regions 49 and 51 not fully extending to be in contact with gate oxide 20, there is some additional space between gate 44 and the channel formed between regions 49 and 51 so that current passing between regions 49 and 51 is less than it would be if they had diffused in closer proximity to gate 20. This is a disadvantage and is a direct result of the additional distance the diffusion must travel due to the recess of substrate 12 adjacent to gate 44.
• Suicide region 46 is also formed on top of gate 14 and consumes a significant amount of gate 14 to leave a gate that is a combination of a region 44 of polysilicon and a region 46 of suicide.
• FIGs. 1 -9 show sequential cross-sections of a semiconductor device according to the prior art
• FIGs. 10-18 are sequential cross-sections of a semiconductor device made according to one embodiment of the invention.
• FIGs. 19-25 are sequential cross-sections of a semiconductor device made according to another embodiment of the invention.
• a problem with recess in the substrate is overcome by waiting until later in the process to remove the nitride anti- reflective coating (ARC) so that the recess that occurs has much less impact with regard to the source and drain moving in to close proximity to the gate dielectric and overlapping with the gate.
• ARC nitride anti- reflective coating
• One way this is achieved is by waiting until the sidewall spacer stack that is utilized for masking the heavy source/drain implant is in place before removing the nitride ARC.
• the nitride ARC is removed after formation of the sidewall spacer that is used for the source/drain extension implant and in such case the nitride ARC is removed with a wet etch.
• FIG. 10 Shown in FIG. 10 is a device 60 after formation of a sidewall spacer 70 as an alternative to the structure shown in FIG. 2.
• the structure of FIG. 10 follows the device structure shown in FIG. 1.
• Device 60 comprises a substrate 62, a gate 64, which may be made of polysilicon and is a type of patterned conductive layer, a gate oxide 66, an ARC 16, which may be nitride, and a sidewall spacer 70.
• Preferable material for substrate 62 is silicon and for sidewall spacer 70 is oxide.
• ARC 16 could be of some other effective anti-reflective material than nitride as well.
• Gate 64 could be materials other than polysilicon also.
• Sidewall spacer 70 results from an oxide layer that is relatively conformal being anisotropically etched.
• FIG. 11 Shown in FIG. 11 is device 60 after a source/drain extension implant forming source/drain region 72 and source/drain region 74 adjacent to sidewall spacer 70 which surrounds gate 64.
• Shown in Shown in FIG. 12 is device 60 after formation of liner 76, a layer 78, and a layer 80.
• Layer 76, 78 and 80 are all typically dielectric materials.
• Layer 76 is preferably oxide
• layer 78 is preferably nitride
• layer 80 is preferably oxide, but instead of a typical dielectric may be amorphous silicon.
• FIG. 13 is sidewall spacer 82 formed from layer 80 using an anisotropic etch. This exposes layer 78 of nitride in areas adjacent to sidewall spacer 82 including an area over gate 64 and ARC 68 as well as a portion of layer 76 which functions as a liner. Shown in FIG.
• nitride etch has been performed so that uncovered portions of layer 78 are removed to leave nitride portions 84 around gate 64. This also has the effect of removing the portion of layer 76 above ARC 68 to leave a portion 86 of layer 76. During this processing regions 72 and 74 diffuse toward each other and toward being under gate 64. With the relatively small amount of recess of substrate 62, the diffusion process is effective in overcoming that small amount of recess. The removal of nitride continues until ARC 68 has been removed which also causes a reduction in the height of sidewall spacer 84 to leave sidewall spacer 88.
• Sidewall spacer 88 is slightly lower than polysilicon 64 due to over-etching which is necessary to be certain that all of ARC 68 has been removed.
• a relatively large recess in substrate 62 aligned with sidewall spacer 82 occurs primarily during the etch of ARC 68.
• This etch is preferably a dry etch because of its superior detectivity characteristics over that of a wet etch. The dry etch will result in a greater recess in substrate 62 than if a wet etch had been used. In this case, however, the relative difference is not material because the recess is significantly removed from the area where it would have a negative impact on the ability of source/drain regions 72 and 74 to become overlapped with gate 64. Shown in FIG.
• FIG. 16 is device 60 after a heavy source/drain implant resulting in heavily doped source/drain regions 90 and 92 aligned to sidewall spacer 82 which acts as an implant mask. If sidewall spacer 82 is chosen to be amorphous silicon, it should be removed after this implant. Shown in FIG. 17 is device structure 60 after a silicide step forms silicide regions 94 and 96 that is also aligned to sidewall spacer 82. If sidewall spacer 82 was chosen to be amorphous silicon, it should be removed before this step of forming silicide. In the depicted example, sidewall spacer 82 is oxide. Shown in FIG.
• FIG. 19 Shown in FIG. 19 is a device structure 110 is shown as a beginning point for another embodiment comprised of a non- volatile memory (NVM) transistor 111 and a regular transistor 113 both of which are formed in a substrate 112.
• NVM non- volatile memory
• Transistor 111 as shown in FIG. 19, comprises a gate oxide 130, a floating gate 114, an interlayer dielectric 120, and a control gate 1 18.
• Regular transistor 113 comprises a gate oxide 132 and a gate 116.
• Over control gate 118 is an ARC layer 126 and over gate 116 is an ARC layer 128. These are two transistors are formed simultaneously and are shown as transistors that would occur as a result of formation of sidewall spacers 122 and 124 and analogous to FIG. 10. Thus there is a recess in the surface of substrate 112 shown as 134 and 136 in FIG. 19. This recess is caused by the over-etch in the formation of sidewall spacer 122. Shown in FIG. 20 is device structure 110 after ARC layers 126 and 128 have been removed using a wet etch. By using a wet etch the recess shown in 134 and 136 in FIG. 120 is significantly less than it would be if a dry etch were used.
• a typical wet etch chemistry is phosphoric acid.
• a typical dry etch for nitride is CF4+HBO.
• the wet etch is effective in this situation because sidewall spacer 122 protects interlayer dielectric 120.
• a wet etch without sidewall spacer 122 protecting interlayer dielectric 120 would degrade dielectric layer 120 and cause a problem between the storage element 114 and the control gate 118. It is important that there not be leakage between storage element 114, which in this depicted case is a floating gate, and control gate 118. With the protection of sidewall spacer 122, the wet etch will not harm interlayer dielectric 120. This also shows the resulting transistor 113 with ARC 128 removed.
• FIG. 21 Shown in FIG. 21 is device structure 110 after an extension implant using sidewall spacer 122 as a mask and sidewall spacer 124 as a mask. The resulting source/drain extension regions 138, 140, 142, and 144 are formed.
• FIG. 22 Shown in FIG. 22 is device structure 110 after deposition of a liner 146 and a nitride layer 148. Nitride layer 148 is then anisotropically etched to form sidewall spacer 150 and sidewall spacer 152. Liner 146 is substantially, if not completely, removed in those areas where it is exposed as a consequence of the removal of nitride layer 148 in the forming of sidewall spacers 150 and 152. Shown in FIG.
• FIG. 24 is device structure 110 after a heavy implant to form heavily doped source/drain regions 154, 156, 158, and 160 using sidewall spacers 150 and 152 as a mask.
• FIG. 25 Shown in FIG. 25 is device structure 110 after silicide formation to form silicide regions 170, 172, 174, and 176.
• the source/drain regions 142 and 144 have, to a large extent, been consumed by silicide regions 170, 172, 174, and 176.
• gate regions 114 and 116 have been somewhat consumed by silicide regions 164 and 168 respectively. This leaves a polysilicon portion 167 for transistor 111 and a polysilicon portion 166 for transistor 113.
• Source/drain portions 178, 180, 182, and 184 expand and diffuse sufficiently to overlap gate regions 167 and 166 although there is a recess to overcome caused by removal of the ARC.
• Such ARC removal is by wet etch so that the amount of the recess is significantly less then that of a dry etch.
• the dry etch is preferred, in the case of a non-volatile memory the significance of having sufficient overlap is greater than for a regular transistor. Thus it is more important that the overlap between the floating gate, the area that has charge storage in it, to have good overlap in the source/drain area.
• the ARC removed after formation of sidewall spacer 122 the location of the recess does not have as severe of an impact as for the case depicted in FIGs. 1 -9 in which the ARC removal occurs prior to formation of such sidewall spacer.
• the sidewall spacer 24 is formed after removal of the ARC layer.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
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• Insulated Gate Type Field-Effect Transistor (AREA)
• Non-Volatile Memory (AREA)

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• 2002
  • 2002-03-19 US US10/101,298 patent/US6753242B2/en not_active Expired - Lifetime
• 2003
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