WO2003034487A1 - Dispositif a semi-conducteur et substrat imprime destine a un dispositif a semi-conducteur - Google Patents

Dispositif a semi-conducteur et substrat imprime destine a un dispositif a semi-conducteur Download PDF

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Publication number
WO2003034487A1
WO2003034487A1 PCT/JP2002/010409 JP0210409W WO03034487A1 WO 2003034487 A1 WO2003034487 A1 WO 2003034487A1 JP 0210409 W JP0210409 W JP 0210409W WO 03034487 A1 WO03034487 A1 WO 03034487A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor element
printed circuit
circuit board
wiring pattern
semiconductor device
Prior art date
Application number
PCT/JP2002/010409
Other languages
English (en)
Japanese (ja)
Inventor
Toru Kai
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Publication of WO2003034487A1 publication Critical patent/WO2003034487A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to, for example, a semiconductor device in which a semiconductor element is mounted on a printed circuit board and a printed circuit board in which the semiconductor element is mounted.
  • a substrate type area array package represented by BGA (Ba11GridArray) or the like has been known.
  • the configuration of the substrate type area array package includes, for example, the specific examples disclosed in (1) Japanese Patent Application Laid-Open No. 2000-58581 and (2) Japanese Patent Application Laid-Open No. Hei 11-3456476. Techniques are known.
  • a dummy wiring pattern is formed on a side on which a semiconductor chip is mounted in order to reduce a difference in thickness of a solder resist on a printed circuit board.
  • FIG. 6 shows the back side of the printed circuit board 1, and the mounting terminals 2 are located near the periphery. Are formed, and a back wiring pattern 3 is formed, and a space region 4 free of these mounting terminals 2 and the back wiring pattern 3 is left in the center.
  • a wiring pattern 6 is formed on the front side of the printed circuit board 1, that is, on the surface on which the semiconductor element 5 is mounted, near the periphery. Then, there is a difference in thickness between the region where the wiring pattern 6 is provided and the region where the wiring pattern 6 is not provided, that is, the region inside the wiring pattern 6. Therefore, it has a configuration in which the dummy wiring pattern 7 is provided in the inner region.
  • the semiconductor element 5 is fixed by an adhesive sheet, and in the above-mentioned prior art example, the semiconductor element 5 is fixed by a paste, and the semiconductor element 5 is placed substantially horizontally with respect to the printed circuit board 1. After mounting and wire-bonding process, it is packaged with mold resin.
  • the packaged semiconductor device depends on the number of terminals of the semiconductor element 5, the design of the semiconductor element 5 mounted on the center of the package on the back surface of the printed circuit board 1 as shown in FIG. Above, a space region 4 where the mounting terminal 2 and the back wiring pattern 3 are not arranged is left.
  • the solder resists 8 and 9 are used to protect the back wiring pattern 3 and the wiring pattern 6 on the front side. It is desired that the solder resists 8 and 9 have a uniform thickness over the entire area of the printed circuit board 1.
  • the inside of the mounting terminal 2 having no wiring pattern on the back side is preferably used. That is, in the spatial region 4, a step a occurs in the thickness of the solder resist 9.
  • the printed circuit board 1 and the semiconductor element 5 are further reduced in thickness due to the demand for smaller size, thinner, and higher functionality.
  • the semiconductor element 5 and the printed circuit board 1 are formed by the pressure P at the time of resin molding.
  • a bending phenomenon occurs. Due to this bending phenomenon, as shown in FIG. 9, a crack 10 may enter the semiconductor element 5, and the semiconductor element 5 may be substantially damaged.
  • At least the semiconductor device according to the first invention of the present invention includes a printed board on which a wiring pattern is provided on both front and back surfaces and a solder resist is applied, and a semiconductor mounted on the printed board.
  • a semiconductor device packaged with an element and a mold resin, wherein a dummy not electrically connected to the wiring pattern is provided on a back surface side of the printed circuit board corresponding to a portion where the semiconductor element is mounted.
  • the printed circuit board according to the second invention of the present invention has at least a wiring pattern provided on both front and back surfaces and a solder resist
  • the printed circuit board according to the second invention of the present invention has A printed circuit board on which a semiconductor element is mounted on a wiring pattern, wherein a dummy pattern that is not electrically connected to the wiring pattern is provided on a back surface side of the printed circuit board corresponding to a portion where the semiconductor element is mounted.
  • the board type area array can be used as a package type printed circuit board and transfer mold
  • a package is formed by encapsulation with a resin such as a type, it does not bend even when a pressing force is applied, so that cracks and breakage of the semiconductor element do not occur, and a high-quality and highly reliable semiconductor device is stabilized. It has the excellent effect that it can be manufactured by using BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a rear view showing a printed circuit board according to the first embodiment of the present invention.
  • FIG. 2 is a rear view showing a printed circuit board according to the second embodiment of the present invention.
  • FIG. 3 is a back view showing a printed circuit board according to the third embodiment of the present invention.
  • FIG. 4 is a cross-sectional view schematically showing a region where a semiconductor element is mounted, using the printed circuit board according to the first embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view for explaining a situation in which a semiconductor element is mounted on the printed circuit board and a pressing force is applied at the time of transfer mold type resin sealing.
  • FIG. 6 is a rear view showing a printed circuit board according to a conventional example.
  • FIG. 7 is a schematic cross-sectional view for explaining that a step is formed on the back surface side of the area where the semiconductor element is mounted on the printed circuit board in the conventional example.
  • FIG. 8 is a schematic cross-sectional view for explaining a situation in which a semiconductor element is mounted on a printed circuit board of the same conventional example and bending is caused by a pressing force applied at the time of transfer molding type resin sealing.
  • FIG. 9 is a schematic cross-sectional view for explaining that a semiconductor element is mounted on a printed circuit board of the conventional example, and that the semiconductor element is bent by the pressure at the time of resin sealing and cracks are generated in the semiconductor element.
  • FIG. 1 shows the back side of the printed circuit board 11 for the board type area array package, in which the mounting terminals 12 and the back surface wiring pattern 13 are formed near the periphery, A space area 14 without a wiring pattern is left in the center, but the space area 14 is not electrically connected to the mounting terminals 12 and the back wiring pattern 13.
  • a backside dummy pattern 20 having a lattice shape is formed, and the backside dummy pattern 20 is formed at substantially the same height (thickness) as the backside wiring pattern 13.
  • FIG. 2 shows the back side of the printed circuit board 1 la according to the second embodiment.
  • this printed circuit board 11a as well, similarly to the printed circuit board according to the first embodiment, mounting terminals 12a and back wiring patterns 13a are formed near the periphery, and in the center part.
  • a space area 14 a with no wiring pattern is left, and the space area 14 a is a regular hexagon without being electrically connected to the mounting terminals 12 a and the back wiring pattern 13 a.
  • the back side dummy pattern 20a formed of a plurality of blocks is formed, and the back side dummy pattern 20a is formed at substantially the same height (thickness) as the back side wiring pattern 13a.
  • FIG. 3 shows a back surface side of a printed circuit board 11b according to the third embodiment.
  • mounting terminals 12b and a back wiring pattern 13b are formed near the periphery, and wiring is formed in the center.
  • a space region 14b without a pattern is left, and the space region 14b has a plurality of concentric circles that are not electrically connected to the mounting terminal 12b and the backside wiring pattern 13b.
  • the back dummy pattern 20 b is formed at substantially the same height (thickness) as the back wiring pattern 13 ′ b. .
  • the wiring pattern and the dummy wiring pattern are formed on the front surface side, as in the above-described conventional example.
  • the printed circuit board 11 according to the first embodiment will be described, and the printed circuit boards 11a and lib according to the second and third embodiments will not be described because the description is redundant.
  • FIG. 4 is a cross-sectional view of a print substrate 11 schematically showing a situation in which the semiconductor element 15 is mounted.
  • a wiring pattern 16 is formed near the peripheral edge on the front side, and a dummy wiring pattern 17 is formed inside the wiring pattern 16.
  • Solder resists 18 and 19 are applied to protect the pattern 13 and the wiring pattern 16 on the front side.
  • These solder resists 18 and 19 are dummy wiring patterns 1 on the front side. Due to the presence of 7, on the back surface side, due to the presence of the back surface dummy pattern 20, the printed circuit board 11 is formed to have a substantially uniform thickness over the entire area.
  • the wiring pattern 16 on the front side and the dummy wiring pattern 17 on the printed circuit board 11 and the wiring pattern 13 on the rear side and the back side Since the dummy patterns 20 are formed at the same time by an etching process, they are all formed of the same material and have the same thickness, and even if the solder resists 18 and 19 are applied. The overall thickness is almost the same.
  • the semiconductor element 15 is fixed to the printed circuit board 11 on which the solder resists 18 and 19 have been applied in this manner, for example, by a paste or the like, and after a wire bonding process, resin molding of a transfer mold type is performed.
  • a pressure P at the time of resin sealing is applied to the semiconductor element 15, and particularly, the back surface of the surface on which the semiconductor element 15 is mounted. Since the back side dummy pattern 20 and the solder resist 19 exist on the side and are flat, the semiconductor element 15 and the printed circuit board 11 do not bend even when the pressure P is applied, and the semiconductor element 15 This eliminates cracks and breaks in the device, making it possible to manufacture semiconductor devices with stable quality.
  • the back surface dummy pattern 20 (20 a, 20 b) is uniform in the space region 14 (14 a, 14 b) on the back surface on which the semiconductor element 15 is mounted, and It is sufficient that they are formed with an even balance.
  • the shapes are not limited to the illustrated shapes, and any other shapes other than these can be formed continuously or intermittently.
  • the shape of the backside dummy pattern 20 (20a, 20b) has a wide range of the spatial region 14 (14a, 14b) other than the above.
  • the packaged semiconductor device by forming a dummy pattern on the back surface side of the portion where the semiconductor element is mounted, the front surface and the back surface on which the semiconductor element is mounted after solder-resist application is substantially completed.
  • the printed circuit board and the semiconductor element do not bend when packaged by performing resin sealing such as a transfer molding type of the board type area array package method, so the semiconductor element is cracked. This eliminates the occurrence of breakage and damage, and provides a semiconductor device with stable quality.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur encapsulé dépourvu de craquelures. A cet effet, on empêche la flexion du substrat imprimé (1) et d'un élément semi-conducteur (5), y compris lors de l'application d'une pression pendant le moulage de résine. Le dispositif à semi-conducteur encapsulé avec une résine de moulage comprend au moins un substrat imprimé dont les deux côtés sont pourvus de motifs d'interconnexion et d'une réserve de soudure, un élément semi-conducteur étant monté sur ce substrat imprimé. Un motif factice qui n'est pas connecté électriquement aux motifs d'interconnexion est disposé dans la partie de l'arrière du substrat imprimé correspondant à la partie où l'élément semi-conducteur est monté. Avec cette configuration, même si une pression est appliquée sur l'élément semi-conducteur pendant l'encapsulation par moulage de résine de type à moule à transfert, l'élément semi-conducteur et le substrat imprimé ne subissent aucune flexion. On empêche ainsi l'apparition de défauts, tels que craquelures et cassures, sur l'élément semi-conducteur, ce qui permet de stabiliser la qualité de ce dispositif à semi-conducteur et d'en améliorer la fiabilité.
PCT/JP2002/010409 2001-10-10 2002-10-07 Dispositif a semi-conducteur et substrat imprime destine a un dispositif a semi-conducteur WO2003034487A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001312902A JP2003124387A (ja) 2001-10-10 2001-10-10 半導体装置及び該半導体装置に使用されるプリント基板
JP2001-312902 2001-10-10

Publications (1)

Publication Number Publication Date
WO2003034487A1 true WO2003034487A1 (fr) 2003-04-24

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Family Applications (1)

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PCT/JP2002/010409 WO2003034487A1 (fr) 2001-10-10 2002-10-07 Dispositif a semi-conducteur et substrat imprime destine a un dispositif a semi-conducteur

Country Status (2)

Country Link
JP (1) JP2003124387A (fr)
WO (1) WO2003034487A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8198546B2 (en) 2005-05-23 2012-06-12 Ibiden Co., Ltd. Printed wiring board
CN104253106A (zh) * 2013-06-26 2014-12-31 英特尔公司 具有局部过孔的金属-绝缘体-金属管芯上电容器

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7355283B2 (en) * 2005-04-14 2008-04-08 Sandisk Corporation Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging
ATE460829T1 (de) * 2005-06-24 2010-03-15 Taiwan Semiconductor Mfg Substrate zur verhinderung von wellungen und herstellungsverfahren dafür
JP5186741B2 (ja) * 2006-08-18 2013-04-24 富士通セミコンダクター株式会社 回路基板及び半導体装置
JP6596652B2 (ja) * 2015-05-11 2019-10-30 パナソニックＩｐマネジメント株式会社 コモンモードノイズフィルタ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04133344A (ja) * 1990-09-25 1992-05-07 Minolta Camera Co Ltd フレキシブル基板
JPH0690068A (ja) * 1992-09-08 1994-03-29 Ibiden Co Ltd プリント配線板
JP2000058581A (ja) * 1998-08-17 2000-02-25 Oki Electric Ind Co Ltd 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04133344A (ja) * 1990-09-25 1992-05-07 Minolta Camera Co Ltd フレキシブル基板
JPH0690068A (ja) * 1992-09-08 1994-03-29 Ibiden Co Ltd プリント配線板
JP2000058581A (ja) * 1998-08-17 2000-02-25 Oki Electric Ind Co Ltd 半導体装置及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8198546B2 (en) 2005-05-23 2012-06-12 Ibiden Co., Ltd. Printed wiring board
CN104253106A (zh) * 2013-06-26 2014-12-31 英特尔公司 具有局部过孔的金属-绝缘体-金属管芯上电容器
CN104253106B (zh) * 2013-06-26 2017-04-12 英特尔公司 具有局部过孔的金属－绝缘体－金属管芯上电容器
US10090239B2 (en) 2013-06-26 2018-10-02 Intel Corporation Metal-insulator-metal on-die capacitor with partial vias

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