WO2003001714A1 - Circuit de commande de gain automatique et procede correspondant, ainsi que dispositif de demodulation faisant intervenir leur utilisation - Google Patents
Circuit de commande de gain automatique et procede correspondant, ainsi que dispositif de demodulation faisant intervenir leur utilisation Download PDFInfo
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- WO2003001714A1 WO2003001714A1 PCT/JP2002/006364 JP0206364W WO03001714A1 WO 2003001714 A1 WO2003001714 A1 WO 2003001714A1 JP 0206364 W JP0206364 W JP 0206364W WO 03001714 A1 WO03001714 A1 WO 03001714A1
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- signal
- gain control
- gain
- burst
- amplification
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
- H03G3/3078—Circuits generating control signals for digitally modulated signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
Definitions
- the present invention relates to an automatic gain control circuit applied to a receiver of a wireless communication system, a method thereof, and a demodulator using the same, and particularly to, for example, orthogonal frequency division multiplexing ( ⁇ FDM).
- ⁇ FDM orthogonal frequency division multiplexing
- AGC automatic gain control
- a burst signal called a preamble signal is inserted at the head of a modulated signal and transmitted.
- the AGC circuit mounted on the synchronous demodulator synchronizes timing within the period of the burst signal, and controls the amplification gain based on the reception level of the burst signal.
- FIG. 1 is a block diagram showing a configuration example of a demodulation device equipped with a conventional AGC circuit applicable to a wireless communication system using burst synchronization.
- FIG. 1 The apparatus shown in FIG. 1 is disclosed in Japanese Patent Application Laid-Open No. H11-205278.
- the demodulation device 10 includes an automatic gain control amplification unit (AG CAMP) 101, an A / D converter (ADC) 102, an OFDM demodulation unit (DEMOD) 103, a delay unit It comprises a (DLY) 104, a burst detection unit (BDT) 105, a packet detection unit (PDT) 106, and an amplification gain control unit (AGCTL) 107.
- AG CAMP automatic gain control amplification unit
- ADC A / D converter
- DEMOD OFDM demodulation unit
- DEMOD OFDM demodulation unit
- DLY burst detection unit
- BDT packet detection unit
- ACTL amplification gain control unit
- OFDM reception signal RS received by an antenna is input to automatic gain control amplification section 101.
- received signal RS is subjected to automatic gain control, and is output to AZD converter 102 as an optimal signal level.
- the case where the automatic gain control is performed and the case where the control gain is fixed are controlled by the control signal S107 from the amplification gain controller 107.
- the input received signal is The log signal is converted into a digital signal, and the digital reception signal S 102 is output to the OFDM demodulation unit 103, the delay unit 104, and the burst detection unit 105.
- the digital reception signal S102 is subjected to discrete Fourier transform based on the output of the cost detection unit 105, and the OFDM signal is demodulated.
- S 103 is output to the packet detector 106 and the processing circuit at the next stage.
- the digital reception signal S102 is delayed by the burst period and output to the burst detection unit 105 as the signal S104.
- burst detection section 105 digital received signal S102 and its delayed signal S104 are correlated, and a burst signal having a period determined by the communication system is detected.
- the detection result is output to the OFDM demodulation unit 103 and the amplification gain control unit 107 as a signal S105.
- the packet detection unit 106 detects the unique word at the head of the bucket from the demodulated signal S103 from the OFDM demodulation unit 103, and determines whether or not the bucket has been correctly demodulated. Then, the end time of the packet is detected, and the detection result is output to the amplification gain controller 10 # as a signal S106.
- the automatic gain control amplification unit 1 based on the output signal S105 from the burst detection unit 105 and the output signal S106 from the bucket detection unit 106, the automatic gain control amplification unit 1 It is determined whether or not the automatic gain control of 01 is fixed, and the result of the determination is output to the automatic gain control amplifier 101 as a control signal S 107.
- the demodulator of FIG. 1 fixes or varies the control gain in the automatic gain control amplifier 101 depending on whether or not burst synchronization has been established in the burst synchronization system. It is suitable for a burst synchronous communication system in which synchronization timing and data / packet timing are transmitted in a time-division manner.
- the OFDM modulation method performs inverse Fourier transform on 2 n power signal symbols that have been subjected to primary modulation (QP SK, 16 SAM, etc.). In this way, we can obtain a variable power equation that configures 2 n subcarriers orthogonal to each other on the frequency axis.
- the OFDM modulated signal by the OFDM modulation method is a composite signal of a plurality of modulated waves, the ratio of the peak amplitude to the average amplitude is large and the amplitude fluctuation is large.
- the optimum gain is gradually drawn over several packets, an error occurs in the first packet, and the communication efficiency is degraded due to data retransmission and the like. There is a benefit.
- the received signal level greatly varies depending on the transmission output of individual devices and the distance between the devices.
- the gain control circuit not the optimum gain for each packet, but the average gain of all the buckets is drawn, and the system may break down. Disclosure of the invention
- the present invention has been made in view of the above circumstances, and has as its object to realize a high-speed and accurate level capture, which can prevent an error from occurring, and can prevent a system from breaking down. It is to provide a gain control circuit and a method thereof, and a demodulation device using the same.
- a first aspect of the present invention provides a data signal An automatic gain control circuit for controlling the amplification gain of a received signal having a burst portion including at least a preamble signal at the beginning, wherein the automatic gain amplifies an input received signal level with a gain according to the gain control signal.
- a control amplification unit a reception signal power observation unit that detects the power of the reception signal; a delay unit that delays the output of the automatic gain control amplification unit for a fixed time; an output signal of the automatic gain control amplification unit and the delay unit
- a burst detection unit that performs burst detection based on the correlation operation of the output signals of the above and outputs a burst synchronization detection signal, and upon receiving a trigger signal indicating the start of burst detection, has a first gain set in advance.
- the gain control signal is output to the automatic gain control amplification unit so as to amplify the signal.
- a second gain is calculated based on the received signal power value, and the gain control signal is output to the automatic gain control amplifier so as to amplify the signal with the second gain.
- the received signal power value is obtained by receiving the output signal of the automatic gain control amplifier, and when the burst synchronization detection signal is received by the burst detection unit, the third gain is calculated based on the obtained received signal power value.
- an amplification gain control section for outputting the gain control signal to the automatic gain control amplification section so as to amplify the gain with the third gain.
- a burst portion including at least a preamble signal is added to the head of a data signal, and the preamble signal is divided into two stages of a first half and a second half.
- An automatic gain control circuit for controlling the amplification gain of the received signal, wherein the automatic gain control amplification section amplifies the input received signal level with a gain corresponding to the gain control signal; and Based on a received signal power observation unit to be detected, a delay unit for delaying the output of the automatic gain control amplification unit for a fixed time, and a correlation operation between the output signal of the automatic gain control amplification unit and the output signal of the delay unit. A burst detection is performed.
- a strike detection unit upon receiving a trigger signal indicating a burst detection start Outputting the gain control signal to the automatic gain control amplification section so as to amplify the signal with the first gain set in advance, and receiving the first burst synchronization detection signal by the burst detection section;
- a second gain is calculated based on the received signal power value detected by the power observation unit, and the gain control signal is output to the automatic gain control amplification unit so as to amplify with the second gain.
- An amplification gain control unit that calculates a third gain based on the signal power value and outputs the gain control signal to the automatic gain control amplification unit so as to amplify the signal with the third gain.
- the amplification gain control section sets the gain of the automatic gain control amplification section after setting the third gain until the start of the next burst detection. Is fixed to the third gain.
- the burst signal includes a reference signal following a preamble signal, and receives the correlation operation result of the burst detection unit to convert the reference signal.
- An amplification control unit for detecting and outputting the second burst synchronization detection signal or the third burst synchronization detection signal to the amplification gain control unit, wherein the amplification gain control unit
- the mode shifts to the standby mode for the trigger signal, and the gain of the automatic gain control amplification unit is adjusted to the third gain until the next trigger signal is input.
- the received signal power monitoring unit is reset each time burst detection is started, and detects the received signal power after reset.
- the received signal power measuring unit detects a peak value of the received signal.
- a burst of a received signal is provided.
- a reference signal is inserted in a data signal section following the section, and the amplification gain control section finely adjusts the value of the third gain during a reference signal section.
- the amplification gain control section obtains a received signal power value in a reference signal section, and calculates the received signal power value in a previous reference signal section. To fine-tune the value of the third gain.
- a third aspect of the present invention is an automatic gain control circuit for controlling the amplification gain of a received signal in which a burst portion including at least a preamble signal is added to the head of a data signal.
- An automatic gain control amplifier for amplifying an input received signal level with a gain corresponding to the gain control signal; and an analog-to-digital converter for converting an output signal of the automatic gain control amplifier from an analog signal to a digital signal.
- a reception signal power observation unit for detecting the power of the reception signal, a delay unit for delaying the output of the automatic gain control amplification unit for a fixed time, a digital output signal of the analog / digital converter and the delay unit
- a burst detection unit that detects a burst based on the correlation operation of the output signals of the first and second stages and outputs a burst synchronization detection signal;
- the gain control signal is output to the automatic gain control amplification unit so as to be amplified with a first gain set in advance, and when the reception signal power is detected by the reception signal power observation unit, Calculating a second gain based on at least the detected received signal power value; outputting the gain control signal to the automatic gain control amplification unit so as to amplify the signal with the second gain;
- a burst portion including at least a preamble signal is added to the head of a data signal, and the preamble signal is added to the beginning of the data signal.
- An automatic gain control circuit that controls the amplification gain of a received signal that is divided into two stages, a half section and a second half section, and that amplifies the input received signal level with a gain according to the gain control signal.
- a delay section for delaying the output for a fixed time; and a burst detection based on a correlation operation between the digital output signal of the analog / digital converter and the output signal of the delay section.
- the first A burst detector that outputs a burst synchronization detection signal and outputs a second burst synchronization detection signal for detecting the second half section.
- the gain control signal is output to the automatic gain control amplifier so that the signal is amplified with a first gain set in advance, and the first signal is output from the burst detector.
- a second gain is calculated based on the received signal power value detected by the received signal power observation unit, and the gain control signal is amplified so as to be amplified with the second gain.
- the signal is output to the automatic gain control amplifying section, and the digital output signal of the analog / digital converter amplified by the second gain is received and integrated to obtain a received signal power value.
- a third gain is calculated based on the obtained received signal power value, and the gain control signal is amplified so as to amplify with the third gain. To have the amplification gain controller for outputting the dynamic gain control amplifier.
- the amplification gain control unit adds the second gain to the received signal power value obtained by the received signal power observation unit and adds the second gain to the analog signal Z. Calculate based on reference signal power value without distorting digital converter
- the amplification gain control unit optimizes the received signal power after gain control in addition to the received signal power value for which the third gain has been obtained. It is calculated based on the converted reference signal power value.
- the amplification gain control unit may add a second gain to the received signal power value obtained by the received signal power observation unit, The second gain is calculated based on the first reference signal power value that does not distort the digital converter, and in addition to the received signal power value for which the third gain has been obtained, the second signal obtained by optimizing the received signal power after gain control. Calculate based on the reference signal power value.
- the amplification gain control unit sets the gain of the automatic gain control amplification unit after setting the third gain until the start of the next burst detection. Is fixed to the third gain.
- the burst signal includes a reference signal following a preamble signal, and receives the correlation operation result of the burst detection signal to generate the reference signal.
- the received signal power monitoring unit is reset every time burst detection is started, and detects the received signal power after reset.
- the received signal power observation unit detects a peak value of the received signal.
- a reference signal is inserted in a data signal section following a burst section of a received signal, and the amplification gain control section includes a reference signal section. During this, the third gain value is finely adjusted.
- the amplification gain control unit Calculates the received signal power value in the reference signal section, and finely adjusts the third gain value based on the received signal power value in the previous reference signal section.
- a fifth aspect of the present invention is an automatic gain control method for controlling the amplification gain of a received signal in which a burst portion including at least a preamble signal is added to the head of a data signal.
- the amplification gain is set so as to amplify the signal with the first gain set in advance, and when the burst detection is started, the received signal is amplified with the first gain.
- the power of the received signal is detected, a second gain is calculated based on the detected power value of the received signal, and the amplification gain is set so as to amplify with the second gain.
- the power value of the received signal amplified with the gain of the above is obtained, and burst detection is performed based on the correlation operation of the received signal amplified with the second gain and the delay signal of the received signal, and burst is detected.
- the third gain based on the amplified received signal power value at the second gain obtained above was calculated, setting the amplification gain so as to amplify with the third gain.
- a burst portion including at least a preamble signal is added to the head of a data signal, and the preamble signal is divided into two stages of a first half and a second half.
- An automatic gain control method for controlling an amplification gain of a divided received signal wherein when starting burst detection, the amplification gain is set so as to amplify with a first gain set in advance, and When the detection is started, the received signal is amplified with the first gain, and in parallel with this, the power of the received signal is detected, and the received signal amplified with the first gain and the received signal are amplified.
- a burst is detected in the first half of the preamble signal based on the correlation operation of the delayed signal, and when a burst in the first half is detected, a second gain is calculated based on the detected received signal power value.
- the amplification gain is set so as to be amplified with the second gain, the power value of the reception signal amplified with the second gain is obtained, and the reception signal amplified with the second gain and the The above based on the correlation operation of the delay signal of the received signal
- a burst is detected in the latter half of the preamble signal, and when a burst in the latter half is detected, a third gain is calculated based on the received signal power value amplified by the second gain obtained above, and the third gain is calculated.
- the amplification gain is fixed to the third gain until the start of the next burst detection.
- the burst signal includes a reference signal following a preamble signal, and receives the correlation operation result at the time of detecting the burst to generate the reference signal.
- the mode shifts to a standby mode of a burst detection start command, and the amplification gain is fixed at the third gain until the next burst detection start command is received.
- a reference signal is inserted in a data signal section following a burst section of a received signal, and the reference signal section is included in the reference signal section. Fine adjustment of the third gain value is performed.
- the received signal power value in the reference signal section is determined, and the third signal power value is calculated based on the received signal power value in the previous reference signal section. Fine-tune the gain value.
- an amplification gain of a reception signal in which a burst portion including at least a preamble signal is added to a head portion of a data signal is controlled, and the reception signal after amplification is controlled.
- An automatic gain control amplification section for amplifying an input received signal level with a gain according to a gain control signal; a received signal power observation section for detecting the power of the received signal; A delay unit for delaying the output of the gain control amplification unit for a fixed time; a burst for detecting a burst based on a correlation operation between the output signal of the automatic gain control amplification unit and the output signal of the delay unit and outputting a burst synchronization detection signal Upon receiving a trigger signal indicating the start of burst detection and the detection unit, the automatic gain control signal is used to amplify the gain control signal with the first gain set in advance. Output to the control amplifier, and when the received signal power is detected by the received signal power observation unit,
- Calculating a second gain based on the detected received signal power value outputting the gain control signal to the automatic gain control amplifying unit so as to amplify the signal with the second gain, and
- a received signal power value is obtained by receiving the amplified output signal of the automatic gain control amplifying unit, and when a burst synchronization detection signal is received by the burst detecting unit, a third gain is obtained based on the obtained received signal power value.
- an amplification gain control unit that outputs the gain control signal to the automatic gain control amplification unit so as to amplify the gain with the third gain.
- a burst portion including at least a preamble signal is added to the head of a data signal, and the preamble signal is divided into two stages of a first half and a second half.
- a demodulator for controlling the amplification gain of the received signal, and demodulating the amplified received signal, wherein the automatic gain control amplification unit amplifies the input received signal level with a gain according to the gain control signal;
- a reception signal power observation unit for detecting the power of the reception signal; a delay unit for delaying the output of the automatic gain control amplification unit for a certain time; and an output signal of the automatic gain control amplification unit and an output signal of the delay unit.
- a second gain is calculated based on the reception signal power value detected by the reception signal power observation unit, and the second gain is amplified with the second gain.
- the gain control signal is output to the automatic gain control amplification unit so as to receive the output signal of the automatic gain control amplification unit amplified by the second gain to obtain a received signal power value.
- a third gain is calculated based on the obtained received signal power value, and amplification is performed with the third gain.
- an amplification gain control section for outputting the gain control signal to the automatic gain control amplification section.
- a ninth aspect of the present invention is to control the amplification gain of a reception signal in which at least a burst part including a preamble signal is added to the head of a data signal, and to control the amplification of the reception signal.
- An automatic gain control amplifier for amplifying an input received signal level with a gain according to a gain control signal, and converting an output signal of the automatic gain control amplifier from an analog signal to a digital signal.
- An analog Z-to-digital converter a reception signal power observation unit for detecting the power of the reception signal, a delay unit for delaying the output of the automatic gain control amplification unit for a predetermined time, a digital output signal of the analog-to-digital converter, A burst detection unit that performs burst detection based on the correlation operation of the output signal of the delay unit and outputs a burst synchronization detection signal;
- the gain control signal is output to the automatic gain control amplification section so as to amplify the signal with the first gain set in advance, and the received signal power is detected by the received signal power observation section.
- a second gain is calculated based on at least the detected received signal power value, and the gain control signal is output to the automatic gain control amplification unit so as to amplify with the second gain
- the digital output signal of the analog / digital converter amplified by the second gain is received and integrated to obtain a received signal power value, and when a burst synchronization detection signal is received by the burst detection unit, the obtained received signal is obtained.
- An amplification gain control unit that calculates a third gain based on the power value, and outputs the gain control signal to the automatic gain control amplification unit so as to amplify with the third gain; Including an automatic gain control circuit having.
- a burst portion including at least a preamble signal is added to the beginning of a data signal, and the preamble signal is divided into two stages, a first half interval and a second half interval.
- a demodulator for controlling the amplification gain of the received signal, and demodulating the amplified received signal, wherein the automatic gain control amplifier amplifies the input received signal level with a gain according to the gain control signal;
- Above automatic gain control An analog Z digital converter for converting the output signal of the width section from an analog signal to a digital signal; a reception signal power observation section for detecting the power of the reception signal; and a delay for delaying the output of the automatic gain control amplification section for a predetermined time.
- the first half of the preamble signal is detected based on the correlation calculation between the digital output signal of the analog / digital converter and the output signal of the delay section.
- a burst detector that outputs a signal and outputs a second burst synchronization detection signal that detects the latter half section, and receives a trigger signal indicating the start of burst detection and amplifies it with a preset first gain
- the gain control signal is output to the automatic gain control amplification section, and the burst detection section outputs the first burst synchronization detection signal.
- the second gain is calculated based on the received signal power value detected by the received signal power observation unit, and the gain control signal is transmitted to the automatic gain control amplification unit so that the signal is amplified with the second gain.
- Receiving and integrating the digital output signal of the analog Z digital converter amplified by the second gain to obtain a received signal power value, and receiving the second burst synchronization detection signal by the burst detection section, An amplification gain control unit that calculates a third gain based on the obtained received signal power value and outputs the gain control signal to the automatic gain control amplification unit so as to amplify the gain with the third gain. Includes automatic gain control circuit.
- the reception signal is modulated based on an orthogonal frequency division multiplexing modulation scheme.
- a gain control signal is output from the amplification gain control unit to the automatic gain control amplification unit, and the amplification gain of the automatic gain control amplification unit is set in advance.
- the first gain for example, the maximum value
- the preamble signal at the head of the received signal is input to the automatic gain control amplifier.
- the automatic gain control amplifier for example, the first half of the preamble signal of the received signal is amplified with the first gain (maximum gain), and output, for example, in the A / D converter in the evening.
- the preamble signal of the received signal is input to the received signal power monitoring unit.
- the received signal power observing section the power of the received signal is observed, for example, a peak voltage is measured, and the received signal power value having a value corresponding to the input received signal level is supplied to the amplification gain control section.
- the preamble signal portion of the received signal is converted from an analog signal to a digital signal and supplied to an amplification gain control section, a delay section, and a burst detection section.
- the digital reception signal is delayed by a burst period for burst detection and output to the burst detection section.
- a burst signal having a period determined by the communication system is detected.
- a first synchronization detection indicating that the first half X section of the preamble signal has been detected A signal is generated and output to the amplification gain control unit.
- burst detection can be performed without reducing the detection rate because the autocorrelation circuit is used in the burst detection unit.
- the amplification gain control unit receives the first burst synchronization detection signal from the burst detection unit, and receives the received signal power value detected by the received signal observation unit and the AZD command.
- the gain is calculated based on an appropriate value that does not distort the signal, and the gain control signal is set to the calculated value.
- This gain control signal is supplied to the automatic gain control amplifier.
- the automatic gain control amplifier receives the gain control signal and sets the gain to a second gain, which is a calculated value.
- the gain of the automatic gain control amplification unit includes analog signal processing in the process of calculating the peak value of the received signal power, and includes a slight variation, so that the rough gain Control.
- the remaining first half and second half of the preamble signal of the received signal are amplified with a gain according to the received signal level, and output to the A / D converter.
- the preamble signal portion of the received signal is converted from an analog signal to a digital signal and supplied to an amplification gain control unit, a delay unit, and a burst detection unit.
- the digital reception signal is delayed by a burst period for burst detection and output to the burst detection section.
- the burst detector performs correlation (autocorrelation and cross-correlation) between the digital received signal by the A / D converter and the delayed signal by the delay unit.
- the amplification gain control unit receives a signal passed through the A / D converter without distortion at a gain based on the received signal power, and for example, integrates the digital signal value of the received signal to obtain an accurate signal. The power value is measured.
- the amplification gain control unit receives the second burst synchronization detection signal from the burst detection unit, and receives the digital integration value and A / D of the received signal passed through the A / D converter without distortion.
- the gain is calculated based on the optimal value that does not distort the D converter, and the gain control signal is set to the calculated value.
- This gain control signal is supplied to the automatic gain control amplifier.
- the automatic gain control amplifier receives the gain control signal and sets the gain to the third gain, which is the optimum calculated value.
- the remaining second half of the preamble signal of the received signal, the reference signal and the data signal are amplified with the gain according to the received signal level, and output to the A / D converter. Is done.
- a reference signal and a data portion of a received signal are converted from an analog signal to a digital signal and supplied to an amplification gain control unit, a delay unit, and a burst detection unit.
- the digital reception signal is delayed by a burst period for burst detection and output to the burst detection unit.
- the cross-correlation power which is the cross-correlation result
- the timing control unit After a predetermined time from the first timing, a third synchronization detection signal is output to the amplification gain control unit.
- the amplification gain control unit that has received the third synchronization detection signal returns to the initial mode, that is, the standby mode for the trigger signal.
- FIG. 1 is a block diagram showing a configuration example of a demodulation device equipped with a conventional AGC circuit applicable to a wireless communication system using burst synchronization.
- FIG. 2 is a block diagram showing an embodiment of a burst synchronous demodulator to which the automatic gain control circuit according to the present invention is applied.
- FIG. 3 is a diagram showing a burst signal section including a representative preamble signal of the IEEE 802.11a system.
- FIG. 4 is a diagram showing a burst signal section including a representative preamble signal of the BRAN system.
- FIG. 5 is a diagram showing a burst signal section including a typical preamble signal of the WIRELESS 394 system.
- FIG. 6 is a diagram showing a signal form in which a reference signal REF is inserted into a data signal section that is longer than a certain period in the Wireless 394 394 system.
- FIG. 7 is a circuit diagram showing a specific configuration of the automatic gain control amplifier of FIG.
- FIG. 8 is a diagram showing an example of the gain control characteristic of the gain control amplifier of FIG. 7.
- FIG. 9 shows the output of the received signal power observing section with respect to the input level of the received signal. It is a figure showing a force characteristic.
- FIG. 10 is a circuit diagram showing a specific configuration example of the reception signal processing unit in FIG.
- FIG. 11 is a circuit diagram showing a specific configuration example of the burst detection unit and the timing control unit in FIG.
- FIG. 12 is a circuit diagram showing a configuration example of the autocorrelation circuit of FIG.
- FIG. 13 is a circuit diagram showing a configuration example of the cross-correlation circuit of FIG.
- FIGS. 14A to 14G are diagrams showing timing charts from the autocorrelation processing of the burst detection unit to the output of the synchronization detection signals Xpulse and ypulse.
- FIGS. 15A to 15F are diagrams showing timing charts from the cross-correlation processing of the burst detection unit to the output of the synchronization detection signal cuise and the FFT timing signal TFFT.
- FIG. 16 is a flowchart for explaining the first stage of the gain control operation in the amplification gain control unit according to the present invention.
- FIG. 17 is a flowchart illustrating a second stage of the gain control operation in the amplification gain control unit according to the present invention.
- FIG. 18 is a flowchart for explaining a third stage of the gain control operation in the amplification gain control unit according to the present invention.
- FIG. 19 is a circuit diagram showing a specific configuration example of the amplification gain control unit in FIG.
- FIGS. 20A to 20H are diagrams showing evening timing charts for explaining the operation of the amplification gain control unit in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 2 is a block diagram showing an embodiment of a burst synchronous demodulator to which the automatic gain control circuit according to the present invention is applied.
- the burst synchronous demodulator 20 has an automatic gain control amplification unit (AGCAMP) 201, a received signal power observation unit (POW) 202, and an A / D converter (ADC) 203 , Digital / analog (D / A) converter (DAC) 204, A / D converter (ADC) 205, received signal processing unit (RXP RC) 206, OFDM demodulation unit (DEMOD) 207, delay unit (DLY) 208 , A burst detection section (BDT) 209, a timing control section (TMG) 210, and an amplification gain control section (AGCTL) 211 as main components.
- a CAAMP automatic gain control amplification unit
- POW received signal power observation unit
- ADC ADC
- DAC Digital / analog converter
- ADC ADC
- RXP RC received signal processing unit
- DEMOD OFDM demodulation unit
- DLY delay unit
- a burst detection section BDT
- TMG timing control section
- an automatic gain control system of a burst synchronous demodulator of a 5-GHz band wireless LAN system will be described as an example of a burst synchronous communication system.
- the 5 GHz band wireless LAN system employs an OFDM modulation scheme to achieve excellent communication performance over a wide band.
- the OFDM modulation method has high strength against ghost and multipath, but weak strength against nonlinearity (non-linearity) of the circuit.
- a burst signal of 10 to 20 X seconds called a preamble signal is inserted at the beginning of the modulated signal, and the timing is synchronized within this interval.
- / D converter 203 It is necessary to capture the level of the voltage amplitude within a signal allowable range that does not cause distortion.
- a frequency characteristic of a transmission path called a reference signal is observed, and a reference signal for correcting a data signal (actual communication data) following the preamble signal is provided. Since the level of the digital signal output from the A / D converter 203 is not allowed to fluctuate between the reference signal and the overnight signal, it is necessary to keep the gain of the automatic gain control amplifier 201 constant. is there.
- three levels of level acquisition are performed in order to realize high-speed and high-performance level acquisition performed in the above preamble section.
- FIG. 3 is a diagram showing a burst signal section including a typical preamble signal of an IEEE 802.11a system
- FIG. 4 is a burst signal including a typical preamble signal of a BRAN system
- FIG. 5 is a diagram showing a signal portion
- FIG. 5 is a diagram showing a burst signal portion including a typical preamble signal of the Wire 1 ess 1394 system.
- a 16, B 16, etc. indicate the pattern identification and the burst period
- IA 16 indicates the phase inverted pattern of A 16 Is represented.
- C 64 represents a reference signal, and 3 shows this part of the evening.
- pattern B16 is repeated 10 times, whereas in BRAN, the first five periods are different (A16, IA16, A16, IA 16, IA 16).
- the pattern is A16, IA16, A16, IA16, A16, IA16, A16, IA16, IA16, IA16.
- a reference signal REF is inserted in a data signal section longer than a certain period.
- the transmission characteristics are measured again for each of the reference signals, thereby preventing the deterioration of the reception performance.
- each element of the demodulation device that demodulates a received signal by inserting a burst signal portion including a signal of 10 to 20 // seconds called a preamble signal at the head of the modulated signal is as follows: It has various configurations and functions.
- the automatic gain control amplification section 201 converts the reception signal RS received by an antenna (not shown) based on the level of the gain control signal Vagc from the amplification gain control section 211 supplied through the DAC 204. Automatic gain control is performed, and the signal RX at the desired level is output to the AZD converter 203 as.
- the automatic gain control amplifier 201 controls the case where the automatic gain control is performed by the gain control signal Vagc from the amplification gain controller 211 and the case where the control gain is fixed.
- FIG. 7 is a circuit diagram showing a specific configuration of the automatic gain control amplifier 201. It is.
- the automatic gain control amplifier 201 includes a gain control amplifier (GCA) 201 1, a local oscillator 201 2, a multiplier 201 3, an amplifier 2014, and a It has a 10 MHz band pass filter (BPF) 20 15.
- GCA gain control amplifier
- BPF band pass filter
- the local oscillator 2012 and the multiplier 2013 constitute a frequency conversion circuit.
- Local oscillator 20 12 outputs, for example, signal e [j 2 ⁇ f cw t) of carrier frequency i cw to multiplier 2013.
- [] indicates a power of e.
- the received signal (IF input signal) RS is amplified by the gain control amplifier 201 1 with the gain determined by the gain control signal Vagc, and the local oscillator 20 12 After the frequency conversion by the frequency conversion circuit composed of the device 2013, the band is limited by the BPF 2015 to obtain the output signal (IF output) RX.
- FIG. 8 is a diagram showing gain control characteristics of the gain control amplifier 201 1 of FIG.
- the horizontal axis represents the gain control signal Vagc, and the vertical axis represents the gain.
- the gain control amplifier 201 1 has a gain of 0 to 80 dB when the gain control signal Vagc is in the range of 0 V to 1 V (linear). Has changed. ,
- control gain range is 80 dB.
- the received signal power observation unit 202 includes a peak detection circuit (Peak Det) 2021 as a peak value detection circuit as shown in FIG. 7, measures the peak voltage of the received signal RS, and inputs the measured signal. The signal is converted to an electric field strength signal RSSI, which is a voltage signal having a value corresponding to the received signal level, and output to the AZD converter 205.
- RSSI electric field strength signal
- a peak value is detected instead of an average value.
- a reset signal is given to reset the peak detection circuit (Peak Det) 2021 and observe the maximum peak value thereafter.
- FIG. 9 is a diagram showing output characteristics of received signal power observation section 202 with respect to the input level of the received signal.
- the horizontal axis represents the input level
- the vertical axis represents the voltage of the field strength signal RRS I.
- the voltage of the field strength signal RSSI changes linearly from 0 V to 2 V when the input level is in the range of 70 dBB to 120 dBBV. ing.
- the A / D converter 203 converts the analog reception signal RX output from the automatic gain control amplifier 201 into a digital signal, and outputs the digital reception signal RXD to the reception signal processing unit 206.
- the DZA converter 204 converts the gain control signal Vagc generated by the amplification gain control unit 211 from a digital signal to an analog signal, and outputs it to the automatic control gain amplification unit 201.
- the AZD converter 205 converts the electric field strength signal RS SI output from the received signal power observation unit 202 from an analog signal to a digital signal RS S ID and outputs the signal to the amplification gain control unit 211.
- Received signal processing section 206 converts digital received signal RXD into baseband signals bb-re (real part) and bb-im (imaginary part), and reduces the sampling frequency of the baseband signal to a lower frequency.
- the signal is converted (down-sampled) and subjected to complex multiplication based on the error detection frequency ⁇ f by the burst detection unit 209 to correct the frequency offset to generate a signal S 206 (sy—re and sy—im).
- FIG. 10 is a circuit diagram showing a specific configuration example of received signal processing section 206 in FIG.
- the received signal processing unit 206 includes a baseband conversion circuit 2061, digital low-pass filters (LPF) 2062, 2063, down-conversion circuits 2064, 2065, and a frequency offset correction circuit. 2066.
- LPF digital low-pass filters
- the base-span conversion circuit 206 1 is composed of a local oscillator 206 1 1 and multipliers 206 1 2, 206 13.
- the baseband conversion circuit 2061 multiplies the received signal RXD (if) by the carrier frequency fcw in the multipliers 20612 , 20613 to obtain the input reception signal as shown in the equation (1).
- the signal RXD (if) is converted to baseband signals b b_r e, bb—im and supplied to LPFs 2062 and 2063, respectively.
- the LPFs 2062 and 2063 have a transversal circuit configuration of, for example, a linear phase FIR (finite impulse response).
- the LPF 2062 is connected in cascade with respect to the input line of the baseband signal bb-re to form a shift register (n_ 1) delay units 1 re- 1 to lre- n- 1 and the input Multipliers 2 re for multiplying the output signals of the baseband signal bb—re and the delay units 1 re—l to lre—n_l by filter coefficients h (0) to h (n—1), respectively _ l ⁇ 2 re—n and n multipliers 2 r It is composed of an adder 3re that adds the output signals of e-1 to 2re-n and outputs the result to the down-conversion circuit 2064.
- the LPF 2063 is composed of (n_l) delay units 1 im_l to 1 im—n-1 that are cascaded to the input line of the base band signal bb—im and constitute a shift register. Filler coefficients h (0) and more for the input 'baseband signal bb-im and the output signals of the delay units 1 im-1 to 1 im-nl, respectively! ! (n-1) multiplied by n multipliers 2 im— 1 to 2 im— n and n multipliers 2 im— 1 to 2 im— It consists of an adder 3 im that outputs.
- LPFs 2062 and 2063 and down-converting circuits 2064 and 2065 convert the sampling frequency of the baseband signals bb-re and bb-im to a signal dc-re from 100 MHz to 25 MHz, for example. You.
- the LPFs 2062 and 2063 restrict the band of the baseband signal b b—re and b b—im so that adjacent carriers do not return.
- the down-sampling timing in the down-converting circuits 2064 and 2065 is such that the clock is thinned out after receiving the supply of the signal En.
- the frequency offset correction circuit 2066 includes a local oscillator 2061, multipliers 2062 to 20665, and adders 20666 and 20667.
- the frequency offset correction circuit 2066 reflects the error detection frequency ⁇ f given by the burst detection unit 209 on the oscillation output of the local oscillator 2061, and multiplies the oscillation output and the signal d c_r e by the multiplier 20662.
- 20665 complex multiplication, the oscillation output and the signal dc—im are complex multiplied by the multipliers 20663 and 20664
- the adder 20666 adds the output of the multiplier 20662 and the output of the multiplier 20663
- the adder 20667 adds the output of the multiplier 20664 and the output of the multiplier 20665, whereby the following equations (2) and (3) are obtained.
- the signals sy-re and syim are generated as shown in (1) and output to the OFDM demodulation section 207, delay section 208, cost detection section 209, and amplification gain control section 211.
- the signals sy-re and sy-im are subjected to high-speed discrete Fourier transform in synchronization with the FFT timing signal TFFT supplied from the timing control section 210 to demodulate the OFDM signal, and Output to the processing circuit.
- the delay unit 208 delays the output signal S206 of the received signal processing unit 206, that is, the signals sy_re and sy_im by the burst period for burst detection, and detects the burst as the signal S208. Output to section 209.
- a burst of 16 clock cycles is detected using the delay amount of the delay unit 208 as 16 clocks.
- the delay amount of the delay unit 208 is
- Burst detection for the first 5 cycles as 2 clocks and burst detection for the second 5 cycles can be performed by setting the delay amount of the delay unit 208 to 16 clock delays, but two delay means with different delays I need. [0 1 6 7] In the burst detection of the W irelessl 394 system, a burst of the first 5 cycles can be detected by setting the delay amount of the delay unit 208 to 32 clocks, and a burst of the second 5 cycles with the same delay amount can be detected. Burst detection can also be performed.
- Burst detection section 209 correlates signal S 206 (sy-re and sy-im) from received signal processing section 206 with delayed signal S 208 from delay section 208, and determines a communication system. Detects the period signal, detects the parameters related to the packet and frame structure, and synchronizes with the timing signal TMNG (X, Y, C) by the timing control unit 210 as a synchronous timing window signal.
- the first and second synchronization detection signals S209W (xpulse, ypulse) are generated and output to the amplification gain control unit 211.
- the burst detection unit 209 outputs a predetermined correlation result and a valid signal S209C that is a reference of the timing signal output to the timing control unit 210.
- burst detection section 209 calculates an error frequency from the phase difference between the real part and the imaginary part of the received signal based on the correlation result, generates error detection frequency ⁇ f, Output to 206.
- the timing control section 210 generates the first and second synchronization detection signals S 209 W (xpulse, ypulse) by the burst detection section 209 using the trigger signal r xwn dw as a trigger.
- the timing signal TMNG (X, Y, C) is output to the burst detector 209.
- the timing control unit 210 observes the peak timing from the correlation result by the burst detection unit 209, and outputs the third synchronization detection signal S210 (cpulse) a predetermined time after this peak timing. Output to amplification gain control section 211, and outputs FFT timing signal TFFT to OFDM demodulation section 207.
- FIG. 11 is a circuit diagram showing a specific configuration example of the burst detection unit 209 and the timing control unit 210 in FIG. [0 1 74]
- the burst detection unit 209 includes an autocorrelation circuit 20901, a cross-correlation circuit 20902, a coefficient table 20903, delay units 20904 and 20905 with a delay amount set to 32 clocks, and a delay amount of 48.
- Delay section set for clocks 2 0906 to 20909, Moving average circuit 209 10 to 209 15, Absolute value calculation circuit 209 16 to 209 18, Threshold circuit 209 19, 20920, Comparison circuit 20 92 1 , 20922, timing window X circuit 20923, timing window Y circuit 20924, timing window C circuit 20925, frequency error detection circuit 20926, and latch circuit 20927.
- the timing control section 210 has a peak search circuit 21 001, and a timing counter 210 002.
- the signals sy_re and sy-im supplied from the received signal processing circuit 206 are input to an autocorrelation circuit 20901, a cross-correlation circuit 20902, and an absolute value calculation circuit 20916.
- the signal sy-re is delayed by the delay unit 208 re by 16 clocks and input to the autocorrelation circuit 20901.
- the signal sy—im is delayed by 16 clocks in the delay unit 208im and input to the autocorrelation circuit 20901.
- FIG. 12 is a circuit diagram showing a configuration example of an autocorrelation circuit.
- the autocorrelation circuit 20901 includes, as shown in FIG. 12, multipliers 11 to 14 and adders 15 and 16.
- the autocorrelation circuit 20901 uses the fact that the X and Y sections in the first half of the brimble signal added to the head of the received signal are periodic functions of 16 clocks, and the input signal sy_r e And sy—im and 16-clock delay sections 208 re and 208 im output sy—re * and sy_im * are conjugate-complexed to obtain auto-correlation outputs acre and acim, and delay sections 20904 to 20907 and And moving average circuit 20 9 10 to 209 13 [0 1 8 1] Specifically, a multiplier 11 multiplies the input signal s y_r e and the delay signal s y_r e * by a complex, and multiplies the input signal s y_r e and the delay signal s y_ im * Multiplier 13 multiplies the input signal sy—im and the delayed signal s y_r e * in a multiplier 13 and multiplies the input
- An elementary multiplication is performed, and an adder 15 adds an output of the multiplier 11 to an output of the multiplier 15 to obtain an autocorrelation output signal acre, and an adder 16 outputs the output of the multiplier 12 and the multiplier 14 To obtain an autocorrelation output signal acim.
- the cross-correlation circuit 20902 is cascaded to the input line of the signal sy-re to form a shift register (m-1) delay units 2 lre_l to 21 re-m-1 and the input signal sy-re and each delay 2 1 re- ;! M multipliers for multiplying the output signals of 22 1 re -m-1 by the coefficients set in the coefficient table 2 090 3, respectively. And an adder 23 re for adding the output signals of 22 re-l to 22 re-m and outputting the correlation output signal cc-re to the absolute value calculation circuit circuit 20918.
- the cross-correlation circuit 20902 is connected in cascade to the input line of the signal sy_im and constitutes a shift register (m_ 1) delay units 2 1 im—
- the coefficient table 20903 is set for 1 to 21 i mm-1 and the input signal s y_ im and the output signal of each delay unit 2 1 im—1 to 21 i mm-1.
- an adder 23 im that adds the output signals of 2222 im ⁇ m and outputs a cross-correlation output signal c c ⁇ im to the absolute value calculation circuit circuit 209 18.
- the cross-correlation circuit 20902 writes the input signals sy-re and sy-im sequentially into the shift register, and stores the value of each tap with the value of the coefficient table 209 03 and each multiplier 22 re-l to 22. re—m, 22 im—l to 22 im_m To obtain the cross-correlation outputs cc-re and cc-im.
- the coefficient table stores the data value of 32 clocks before the C64 section in the latter half of the preamble signal.
- the output signal a cr e of the autocorrelation circuit 2090 1 is a moving average circuit 2
- the signal is input to 09 12 directly and delayed by 48 clocks via the delay unit 20906, averaged (integrated), and input to the absolute value calculation circuit 209 17.
- the output signal ac im of the autocorrelation circuit 20901 is input to the moving average circuit 209 13 directly and delayed by 48 clocks via the delay unit 20907, and is averaged. (Integrated) is input to the absolute value calculation circuit 209 17.
- the autocorrelation power ACP is obtained by calculating the absolute value (re 2 + im 2 ) by squaring the real part re and the imaginary part im in the absolute calculation circuit 20917. Output to circuit 20 92 1.
- the output signal acre of the autocorrelation circuit 20901 is input to the moving average circuit 20910 directly and delayed by 32 clocks via the delay unit 20904, and is averaged (integrated). ) Is input to the frequency error detection circuit 20926.
- the output signal acim of the autocorrelation circuit 20901 is input to the moving average circuit 209111 directly and after being delayed by 32 clocks via the delay unit 20905, and is averaged. (Integrated) is input to the frequency error detection circuit 20926.
- the output signal of the absolute value calculation circuit 20916 is input to the moving average circuit 20915 directly and delayed by 32 clocks via the delay unit 20909, and is averaged (integrated). ) Is input to the threshold circuit 20930.
- a threshold value of autocorrelation th—ac is defined and supplied to the comparison circuit 20921.
- the threshold value of the cross-correlation t h — c c is defined and supplied to the comparison circuit 20922.
- the autocorrelation power ACP is compared with the autocorrelation threshold value th_ac, and the result is output to the timing window X circuit 20923 and the timing window Y circuit 20924. You.
- the peak timing of the cross-correlation power C CP by the burst detection section 209 is observed by the peak search circuit 21001, and the timing is output to the timing counter 2 1002.
- the timing counter 2 1002 increments the counter with the trigger signal r xwn dw input as a trigger, and at a predetermined timing, the evening timing signals TX and TYTC are set to the timing window of the burst detection unit 209.
- the timing window is multiplied by the comparison result of the comparison circuits 20923, 20924, and 20925, and the first synchronization is performed from the timing window X circuit 20923.
- the detection signal xpu 1 se is output from the timing window Y circuit 20924 to the second synchronization detection signal ypu 1 se to the amplification gain control unit 211.
- peak search circuit 21001 receives the peak timing of cross-correlation power CCP, and timing counter 21002 performs third synchronization after a certain time from the peak timing.
- the detection signal cpu 1 se is output to the amplification gain control section 211, and the FFT timing signal TFFT is output to the OFDM demodulation section 207.
- FIGS. 14A to 14G are diagrams showing timing charts from the autocorrelation processing of the burst detection unit to the output of the synchronization detection signals xpu1se and ypu1se.
- FIG. 14A shows a preamble and reference portion of input signal S206 (sy-re, sy_im), and Fig. 14B shows a delay obtained by delaying signal S206 by delay section 208.
- FIG. 14C shows the autocorrelation power ACP
- FIG. 14D shows the timing window X
- FIG. 14E shows the timing window Y
- FIG. 14F shows the first synchronization detection signal X p U 1 se
- FIG. 14G shows the second synchronization detection signal ypulse.
- the preamble signal of the Wirelessl 394 has five X periods and five Y periods, each having 16 clock periods. As shown in FIG. In the X and Y sections, the autocorrelation power AC P increases.
- FIG. 5 is a diagram showing an evening timing chart until a synchronization detection signal cpuise and an FFT timing signal TFFT are output.
- FIG. 15A shows an input signal S 206 (sy_r e, sy__ im), and FIG. 15B shows a cross-correlation power CCP.
- 5C shows the evening timing window C
- FIG. 15D shows the valid signal ccVa1id output from the timing window circuit 20925
- FIG. 15E shows the third synchronization detection signal cpulse.
- FIG. 15F shows the FFT timing signal TFFT.
- Fig. 15C more accurate peak detection can be performed by setting the timing window C before and after the timing when the cross-correlation power C CP is maximized. After 32 clocks from the peak timing detected in this way, as shown in FIGS. 15E and 15F, the third synchronization detection signal cuise and the FFT timing signal TFFFT are output.
- the FFT timing signal TFFT is output after 64 clocks, and thereafter, it is repeatedly output in 72 clock cycles.
- the frequency error detection circuit 2 0 9 2 6 calculates the phase difference from the real part and the imaginary part of the autocorrelation output signal, and calculates the error frequency A; f from the following equation (4). calculate.
- ⁇ f tan one 1 (acim / aere) X ( 1/3 2) X 20 x 1 0 6 (Hz)
- Amplification gain control section 211 receives digital received signal S 206 after gain control by automatic gain control amplification section 201 from reception signal processing section 206, and A / D converter
- the digital electric field strength signal RS SID indicating the peak level of the received signal RS of the received signal power observation unit 202 by the bar signal 205 and the first and second signals as the synchronization timing window signal from the burst detection unit 209
- the timing control unit 210 Based on the synchronization detection signal S209W (xpu1se, ypu1se) and the third synchronization detection signal S210 (cpu1se) by the timing control unit 210, the details will be described below.
- the control for controlling the gain of the automatic gain control amplifier 201 is performed in accordance with the synchronous burst detection timing, and the gain is controlled by changing the gain voltage Vagc so that the received signal has the optimum signal level. Then, the gain control signal Vagc is output to the automatic gain control amplifier 201 via the D / A converter 204.
- the gain control signal Vagc is output from the amplification gain control section 2 1 1 at the maximum value (ST 2), and automatic gain control amplification is performed.
- the gain of the unit 201 is set to the maximum (first gain) (ST3), and burst detection is performed by a combination of the delay unit 208 and the burst detection unit 209.
- burst detection can be performed without lowering the detection rate because the autocorrelation circuit 20901 is used in the burst detector 209. It is.
- the received signal power is observed by the received signal power observation unit 202 and the electric field strength signal RS SI, which is the received signal power signal, is converted into an AZD converter 20 Input as a digital signal RS SID via 5 (ST 5).
- a peak value (peak value) is detected instead of an average value.
- a reset signal is given, the peak detection circuit is reset, and the maximum peak value thereafter is observed.
- the digital electric field strength signal RS SID The gain is calculated based on the level (ST8), the gain control signal Vagc is set to the calculated value CVI (ST9), and the gain of the automatic gain control amplifier 201 is calculated via the DZA comparator 204 CVI (Second gain) (ST 10).
- control gain CG1 at this time is calculated based on the following equation.
- VRS SI indicates the received signal power value observed by the received signal power observation unit 202
- Vrefl indicates the first reference signal power value that is an appropriate value that does not distort the A / D converter 203. ing.
- the gain of the automatic gain control amplification unit 201 includes analog signal processing in the process of calculating the peak value of the received signal power, includes a slight variation, and is rough. Gain control is performed.
- the amplification gain control unit 211 integrates the digital value of the received signal and measures the accurate signal power (ST 1 1).
- the second synchronization detection signal S209W (ypu1se) is received by the burst detection unit 209. (ST 13), calculates the gain based on the digital integrated value of the received signal S 206 passed through the A / D converter 203 without distortion (ST 13), and sets the gain control signal Vagc to the calculated value CV 2 Then (ST14), the gain of the automatic gain control amplification unit 201 is set to the calculated value CV2 (third gain) via the DZA converter 204 and optimized (ST15).
- Control gain CG2 at this time is calculated based on the following equation.
- VI is the received signal power value after passing through the AZD converter 203 integrated by the amplification gain control unit 211
- Vref2 is the second reference signal power value
- the received signal after gain control The optimum values of the power are shown.
- the optimized gain value is fixed until the end of the data signal and the start of the next burst detection (ST16).
- a reset signal is supplied to received signal power observation section 202 to reset peak detection circuit 2021 and observe the maximum peak value thereafter.
- FIG. 19 is a circuit diagram showing a specific configuration example of the amplification gain control section 211 of FIG.
- the amplification gain control section 2 11 1 has an initial gain table 2 1 1 0 1.
- the amplification gain control unit 211 is configured to generate a synchronization detection timing pulse, that is, a trigger signal r xwn dw, a first synchronization detection signal xpu 1 se by the burst detection unit 209, and a second synchronization detection. It has a state machine configuration based on the signal yp u 1 se and the third synchronization detection signal cuise by the timing control unit 210, and different gains agc of the automatic gain control amplification unit 201 are output in each of the states 0 to 3. Is controlled to be.
- FIGS. 2OA to 20H are diagrams each showing an evening timing chart for explaining the operation of the amplification gain control unit in FIG.
- Fig. 20A shows an input signal S206 (sy_re, sy_im)
- Fig. 20B shows a trigger signal rx wn dw
- Fig. 20C shows a first synchronization detection
- 20D shows the signal xP u 1 se
- FIG. 20D shows the second synchronization detection signal ypu 1 se
- FIG. 20E shows the third synchronization detection signal cpulse
- FIG. 20F shows the state
- FIG. The gain control signal Vagc is shown
- FIG. 20H shows the received signal RX output from the automatic gain control amplifier 201.
- An appropriate gain is selected from the initial gain table 21101 based on the flag signal StationID.
- the initial gain table 2 110 1 is set so as to have the maximum gain.
- the trigger signal r xwn dw is passed through the gain selection circuit 21 1 13 at the rising timing, and the gain is obtained from the control gain adjustment table 2 1 1 14 Output as control signal Vagc and state Move to 1.
- the initial gain (maximum gain) determined by the initial F gain table 2111 is output as the gain control signal Vagc.
- RSI gain gain-rssi is calculated in adder 211108 as in equation (6). Then, as shown in FIGS. 20C, 20F, and 20G, at the input timing of the first synchronization detection signal xpu 1 se, the selection gain of the gain selection circuit 21 1 13 is added from the initial gain to the adder 2 1 1 Switch to the RS SI gain gain rssi by 08, output the gain control signal Vagc from the control gain adjustment table 21 114, and go to state 2.
- rssiref is a value obtained by subtracting 40 in advance because the bit width is set to 8 bits with the R SSI reference value, and 40 is added and corrected during gain calculation.
- the R SSI gain gain—rssi is output as the gain control signal Vagc.
- Multiplier 2 1 103 squares input signal sy_r e, squares input signal sy—im in multiplier 2 1104, squares input signal sy—im, and adds these in adder 2 1 105 to input received signal.
- the digital integrated value is calculated through the adder 2 1106, the delay unit 2110 9, and the delay unit 2110, and the received signal level adssi is calculated by the logarithmic converter 2 1 1 1 1 into the formula ( Calculate as in 7).
- the adssi gain gain—rssi is expressed as in equation (8). Is calculated.
- the selection gain of the gain selection circuit 2 1 1 1 2 is set to the RS SI gain. Switch from rssi to adssi gain gain_rss i by adder 2 1 1 0 7, output as gain control voltage signal Vagc from control gain adjustment table 2 1 1 1 4, and transition to state 3.
- adssi gain gain—rssi is output as a gain control signal Vagc.
- the gain control voltage signal Vagc holds the ad ss i gain gain—rs s i.
- the gain control signal Vagc is set to the maximum value and output from the amplification gain control unit 211 with the trigger signal rxwndw as a trigger.
- the gain control signal Vagc is converted into an analog signal by the D / A converter 204 and supplied to the automatic gain control amplifier 201.
- the automatic gain control amplifying section 201 receives the gain control signal, which is an analog signal. In response to the signal Vagc, the gain is set to the maximum first gain.
- the preamble signal at the head of received signal RS is input to automatic gain control amplification section 201.
- the substantially X section in the first half of the preamble signal of the received signal RS is amplified with the maximum gain and output to the AZD comparator 203 as the signal RX.
- the preamble signal of the received signal RS is input to the received signal fog observation unit 202.
- the received signal R is input to the received signal fog observation unit 202.
- RS SI which is a voltage signal that takes a value according to the input received signal level, and is converted to an A / D converter.
- the electric field strength signal RS SI which is the received signal power signal is input to the amplification gain control section 211 as a digital signal RS SI D via the A / D converter 205.
- the preamble signal portion of received signal RS is converted from an analog signal to a digital signal, and is supplied to received signal processing section 206 as signal RXD.
- input digital received signal RXD is converted into baseband signals bb_re (real part) and bb-im (imaginary part), and the sampling frequency of the baseband signal is lower. Is converted to
- the output signal S206 of the reception signal processing unit 206 that is, the signals sy_r e and sy—im are delayed by the burst period for burst detection, and the burst is detected as the signal S208.
- burst detection section 209 autocorrelation and cross-correlation between signal S206 (sy-re and sy-im) by reception signal processing section 206 and delayed signal S208 by delay section 208 are obtained.
- a first synchronization detection signal S209W (which indicates that the first X section of the preamble signal has been detected) xpu 1 se) is generated and output to the amplification gain control unit 211.
- burst detection can be performed without reducing the detection rate because the autocorrelation circuit is used in the burst detection unit 209.
- an error frequency is calculated from the phase difference between the real part and the imaginary part of the received signal based on the autocorrelation result, and error detection frequency ⁇ f is generated. Is output to
- Amplification gain control section 211 receives burst synchronization detection signal S209W (xpulse) from burst detection section 209, calculates gain based on the level of digital field strength signal RSSID, and controls gain.
- the signal Vagc is set to the calculated value CV1.
- the gain control signal Vagc is converted to an analog signal by the DZA converter 204 and supplied to the automatic gain control amplifier 201.
- Automatic gain control amplification section 201 receives gain control signal Vagc, which is an analog signal, and sets the gain to the second gain of the calculated value.
- the gain of the automatic gain control amplification section 201 is Analog signal processing is included in the process of calculating the peak value of the signal power, and there is some variation, resulting in rough gain control.
- automatic gain control amplification section 201 the remaining X section and second half Y section of the preamble signal of received signal RS are amplified with a second gain according to the received signal level, and A is used as signal RX.
- Output to / D Comparator 203 the remaining X section and second half Y section of the preamble signal of received signal RS are amplified with a second gain according to the received signal level, and A is used as signal RX.
- the preamble signal portion of the received signal RS is converted from an analog signal to a digital signal and supplied to the received signal processing unit 206 as a signal RXD.
- the input digital received signal RXD is converted into baseband signals bb-re (real part) and bb-im (imaginary part), and the sampling frequency of the baseband signal is lower. Is converted to
- the frequency offset is corrected based on the error detection frequency ⁇ ⁇ ⁇ f by the burst detection unit 209 to generate a signal S206 (sy_re and sy_im), and the OFDM demodulation unit 207, the delay unit 208 and the burst detection unit 209.
- the output signal S206 of the received signal processing unit 206 that is, the signals sy_r e and sy-im are delayed by the burst period for burst detection, and the burst is detected as the signal S208.
- burst detection section 209 autocorrelation and cross-correlation between signal S206 (sy__re and sy-im) by reception signal processing section 206 and delay signal S2 ⁇ 8 by delay section 208 are obtained.
- a synchronization detection signal S209W (ypu1se) is generated and output to the amplification gain control section 211.
- the burst detector 209 calculates an error frequency from the phase difference between the real part and the imaginary part of the received signal based on the autocorrelation result, generates an error detection frequency ⁇ f, and generates the received signal. Output to the processing unit 206.
- Amplification gain control section 211 receives signal S206 passed through AZD converter 203 without distortion with a gain based on the received signal power, and integrates the digital value of the received signal. And the exact signal power is measured.
- the amplification gain control unit 211 receives the second synchronization detection signal S209W (ypulse) from the north detection unit 209, and turns off the A / D converter 203.
- the gain is calculated based on the integration value of the digitized signal of the received signal S206 passed through the distortion, and the gain control signal Vagc is set to the calculated value CV2.
- the gain control signal Vagc is converted into an analog signal by the DZA converter 204 and supplied to the automatic gain control amplifier 201.
- Automatic gain control amplification section 201 receives gain control signal Vagc, which is an analog signal, and sets the gain to the third gain of the optimum calculated value.
- the automatic gain control amplification section 201 the remaining Y section of the preamble signal of the received signal RS, the reference C 64 and data after C 16 and the data having the third gain corresponding to the received signal level are provided. It is amplified and output to AZD converter 203 as signal RX.
- the reference C64 and the data portion of the received signal RS are converted from an analog signal to a digital signal and supplied to the received signal processing unit 206 as a signal RXD.
- the frequency offset is corrected based on the error detection frequency ⁇ f by the burst detection unit 209, and the signal S206 (sy—re and sy—
- output signal S206 of received signal processing section 206 that is, signals sy-re and sy-im are delayed by a burst cycle for detecting a noise, and signal S2 Output to burst detector 209 as 208
- the autocorrelation and cross-correlation with 208 are taken.
- the cross-correlation power which is the cross-correlation result, is supplied to the timing control unit 210, based on which the peak timing is observed, and after a predetermined time from this peak timing, the third synchronization detection signal S 210 (cpu 1 se) is output to the amplification gain control section 211, and the FFT timing signal TFFT is output to the OFDM demodulation section 207.
- the amplification gain control unit 211 Upon receiving the third synchronization detection signal S210 (cp1se), the amplification gain control unit 211 returns to the initial mode, that is, the standby mode for the trigger signal rxwndw.
- the optimized gain value is fixed until the end of the data signal and the start of the next burst detection.
- the output signal S206 of the reception signal processing section 206 that is, the signals sy_re and sy__im are output from the timing control section 2
- the fast discrete Fourier transform is performed in synchronization with the FFT timing signal TFFT supplied by 10 and 0 FDM signal is demodulated.
- the automatic gain control amplification unit 201 amplifies the input received signal level with a gain according to the gain control signal, and the automatic gain control amplification
- the output of the AZD converter 203 that converts the output signal of the unit 201 from an analog signal to a digital signal, the received signal power observation unit 202 that detects the power of the received signal, and the output of the automatic gain control amplifier Performs burst detection based on the correlation operation between the digital received signal and the output signal of the delay unit, and outputs the first burst synchronization detection signal when the first half of the preamble signal is detected.
- a gain control signal is automatically used to amplify with a maximum value.
- the signal is output to the control amplification unit, and when the first burst synchronization detection signal is received by the burst detection unit, the second gain is calculated based on the received signal power value detected by the received signal power observation unit, and the second gain is calculated.
- a gain control signal is output to the automatic gain control amplification unit so as to amplify with a gain, and the digital reception signal amplified with the second gain is integrated to obtain a received signal power value.
- an amplification gain control that calculates a third gain based on the obtained received signal power value and outputs a gain control signal to the automatic gain control amplification unit so as to amplify with the third gain. Since the section 211 is provided, the following effects can be obtained.
- the preamble signal can be burst detected in two stages, coarse gain control is performed when the first burst is detected, and precise gain control is performed when the next burst is detected. Recovery when the burst detection timing is incorrect Lee can do.
- a pattern of a signal to be digitally integrated can be specified, and more accurate level acquisition can be performed.
- a reference signal is inserted into the data signal at regular intervals in order to support the synchronous transfer mode.
- the gain control signal output from the amplification gain control section 21 1 at the timing of the reference signal uses the above (6) based on the digital integration value in the C64 section of the previous reference signal. Can be calculated.
- the automatic gain control circuit and method of the present invention, and the demodulation device Since it is possible to perform high-speed and accurate level acquisition, it can be applied to burst synchronous communication systems such as wireless LAN.
- the automatic gain control circuit and method and the demodulation apparatus of the present invention perform level acquisition in a multipath environment by performing fine adjustment of level acquisition for each reference signal. Because it can be realized more accurately, in systems that support synchronous transfer mode, such as the W ire 1 ess 1 3 9 4 system, the reference signal is inserted at regular intervals during the de-evening signal. Applicable.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Circuits Of Receivers In General (AREA)
- Control Of Amplification And Gain Control (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60221526T DE60221526T2 (de) | 2001-06-25 | 2002-06-25 | Regelverstärkung und Verfahren und Demodulationsvorrichtung |
US10/362,295 US7397872B2 (en) | 2001-06-25 | 2002-06-25 | Automatic gain control circuit and method thereof and demodulation apparatus using the same |
EP02741298A EP1401134B1 (en) | 2001-06-25 | 2002-06-25 | Automatic gain control circuit and method and demodulation apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001190994A JP3599001B2 (ja) | 2001-06-25 | 2001-06-25 | 自動利得制御回路およびその方法、並びにそれらを用いた復調装置 |
JP2001-190994 | 2001-06-25 |
Publications (1)
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WO2003001714A1 true WO2003001714A1 (fr) | 2003-01-03 |
Family
ID=19029684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2002/006364 WO2003001714A1 (fr) | 2001-06-25 | 2002-06-25 | Circuit de commande de gain automatique et procede correspondant, ainsi que dispositif de demodulation faisant intervenir leur utilisation |
Country Status (6)
Country | Link |
---|---|
US (1) | US7397872B2 (ja) |
EP (1) | EP1401134B1 (ja) |
JP (1) | JP3599001B2 (ja) |
CN (1) | CN100512070C (ja) |
DE (1) | DE60221526T2 (ja) |
WO (1) | WO2003001714A1 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
DE60221526D1 (de) | 2007-09-13 |
EP1401134B1 (en) | 2007-08-01 |
DE60221526T2 (de) | 2008-05-15 |
US7397872B2 (en) | 2008-07-08 |
JP2003008676A (ja) | 2003-01-10 |
CN1465151A (zh) | 2003-12-31 |
EP1401134A1 (en) | 2004-03-24 |
EP1401134A4 (en) | 2006-01-04 |
US20040037378A1 (en) | 2004-02-26 |
JP3599001B2 (ja) | 2004-12-08 |
CN100512070C (zh) | 2009-07-08 |
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