Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
  • H10D84/141—VDMOS having built-in components
  • H10D84/148—VDMOS having built-in components the built-in components being breakdown diodes, e.g. Zener diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation

Definitions

• the present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
• DMOS Double diffused MOS transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions.
• MOSFET Metal On Semiconductor Field Effect Transistor
• DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications.
• DMOS transistors provide higher current per unit area when low forward voltage drops are required.
• a typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel.
• the individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon.
• the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor.
• DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain.
• the trench which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance.
• Examples of trench DMOS transistors are disclosed in U.S. Patent Nos. 5,072,266, 5,541,425, and 5,866,931.
• Electrostatic Discharge (ESD) presents a problem for semiconductor devices, particularly for DMOS structures.
• the high voltage transient signal from a static discharge can bias an object with more than 10,000 Volts.
• the unique hazard in DMOS devices is the high electric field that can develop across a relatively thin gate dielectric used in the normal course of operation of the device.
• the gate dielectric which is often oxide, can rupture under high electric field conditions when the charge built up on the gate penetrates the gate oxide, which normally acts as an insulator.
• the effects of the permanent damage caused by the rupture may not be immediately apparent; therefore, the possibility of gate oxide rupture constitutes a realistic reliability concern.
• ESD conditions are common in many working environments, many commercial DMOS devices are equipped with self- contained ESD protection systems. These can be discrete or integrated with the main functional circuitry.
• One method for protecting the gate of the devices from voltage above the oxide breakdown value employs a zener diode connected between the gate and source of the DMOS.
• a zener diode connected between the gate and source of the DMOS.
• An example of such a method and device is shown in U.S. Patent No. 5,602,046. This technique improves the ESD rating of the MOSFET gate and helps avoid over-voltage damage.
• the present invention provides a trench DMOS transistor having overvoltage protection.
• the transistor includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate.
• An insulating layer lines the trench and overlies the body region.
• a conductive electrode is deposited in the trench so that it overlies the insulating layer.
• a source region of the first conductivity type is formed in the body region adjacent to the trench.
• An undoped polysilicon layer overlies a portion of the insulating layer.
• a plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
• the undoped polysilicon layer overlies a portion of the insulating layer that is vertically displaced from the body region.
• the plurality of cathode regions and the anode region are disposed in the portion of the insulating layer vertically displaced from the trench.
• the plurality of cathode regions include boron implanted therein.
• the source region and the plurality of cathode regions are formed in simultaneous deposition steps.
• FIG. 1 shows the circuit equivalent for a typical N-channel DMOS in which a zener diode is located between the source and gate of the DMOS.
• FIG. 2 shows a cross-section of a conventional trench DMOS structure.
• FIGS. 3-12 illustrate a sequence of process steps forming a DMOS transistor having overvoltage protection constructed in accordance with the present invention.
• FIG. 1 shows the circuit equivalent for a typical N-channel DMOS in which a zener diode is located between the source and gate of the DMOS.
• the zener diode breaks down when the gate to source voltage exceeds a specified voltage value.
• FIG. 2 illustrates an example of a conventional trench DMOS structure.
• the structure includes an n + substrate 100 on which is grown a lightly n-doped epitaxial layer 104. Within doped epitaxial layer 104, a body region 1 16 of opposite conductivity is provided. An n-doped epitaxial layer 140 that overlies most of the body region 116 serves as the source.
• a rectangularly shaped trench 124 is provided in the epitaxial layers, which is open at the upper surface of the structure and defines the perimeter of the transistor cell.
• a gate oxide layer 130 lines the sidewalls of the trench 124.
• the trench 124 is filled with polysilicon, i.e., polycrystalline silicon.
• a drain electrode is connected to the back surface of the semiconductor substrate 100, a source electrode is connected to the two source regions 140 and the body region 116, and a gate electrode is connected to the polysilicon that fills the trench 124.
• a zener diode is incorporated into the trench DMOS structure shown in FIG. 2 in such a way that no additional masking steps are required.
• FIG. 11 shows the resulting device in cross-section.
• the zener diode comprises cathodes 145 and anode 148.
• the structure shown in FIG. 1 1 is advantageous because the source regions 140 of the DMOS transistor and n+ cathode regions 145 of the zener diode can be formed in the same mask and implantation steps.
• FIGs. 3-12 show a series of exemplary steps that are performed to form the inventive DMOS device.
• an N- doped epitaxial layer 104 is grown on a conventionally N+ doped substrate 100.
• Epitaxial layer 104 is typically 5.5 microns in thickness for a 30 V device.
• P-body region 116 is formed in an implantation and diffusion step. Since the P-body implant is uniform across the substrate, no mask is needed.
• the P-body regions are boron implanted at 40 to 60 KeV with a dosage of about 5.5x10* /cm .
• a mask layer is formed by covering the surface of epitaxial layer 104 with an oxide layer, which is then conventionally exposed and patterned to leave mask portions 120.
• Mask portions 120 are used for defining the location of the trenches.
• the patterned mask portions 120 define the trench sidewalls.
• Trenches 124 are dry etched through the mask openings by reactive ion etching to a depth that typically ranges from 1.5 to 2.5 microns.
• a dry chemical etch may be used to remove a thin layer of oxide (typically about 500 - 1000 A) from the trench sidewalls to eliminate damage caused by the reactive ion etching process.
• a sacrificial silicon dioxide layer (not shown) is grown over trenches 124 and mask portions 120.
• the sacrificial layer, as well as mask portions 120, are removed either by a buffer oxide etch or an HF etch so that the resulting trench sidewalls are as smooth as possible.
• the gate oxide layer 130 is then deposited on the entire structure so that it covers the trench walls and the surface of p-body 116. Gate oxide layer 130 typically has a thickness in the range of 500-800 angstroms.
• the trenches 124 are filled with polysilicon 152, i.e., polycrystalline silicon.
• the polysilicon Prior to deposition, the polysilicon is typically doped with phosphorous chloride or implanted with arsenic or phosphorous to reduce its resistivity, typically within the range of 20 ⁇ /m.
• the polysilicon may be deposited in a two-step process. In the first step, a layer of undoped polysilicon is deposited to line the sidewalls of the trenches. The undoped polysilicon layer is followed by the deposition of a layer of doped polysilicon. Typically, the thickness of the doped polysilicon layer is greater than the thickness of the undoped polysilicon layer.
• the ratio of the thickness of the doped polysilicon layer to the undoped polysilicon layer may be 7: 1 , with a total thickness of about 8,000 A.
• the undoped polysilicon layer is advantageously employed as a buffer layer inhibits the penetration of dopant material through the gate oxide layer and into the p-body, thus further reducing punch-through.
• the polysilicon layer 152 is etched to optimize its thickness and to expose the portion of the gate oxide layer 130 that extends over the surface of p-body 1 16.
• an undoped polysilicon layer 160 is deposited over the gate oxide layer 130 and the exposed surface of doped polysilicon layer 152.
• Undoped polysilicon layer 160 which defines the layer in which the zener diode will be formed, typically has a thickness in the range of 5,000 to 10,000 angstroms. [0025] In FIG. 9, undoped polysilicon layer 160 is etched back so that it is completely removed from the region in which the DMOS transistor is defined. That is, undoped polysilicon layer 160 is removed so that is does not overlie the trench and body regions of the DMOS. Accordingly, the undoped polysilicon layer 160 only remains in the region in which the zener diode will be formed. [0026] Next, in FIG. 10, a photoresist masking process is used to form patterned masking layer 170.
• Patterned masking layer 170 defines source regions 140 of the DMOS transistor and n+ cathode regions 145 of the zener diode. Source and cathode regions 140 and 145 are then formed by an implantation and diffusion process. For example, the source regions may be implanted with arsenic at 80 KeV to a concentration that is typically in the range of 8xl0 15 to 1.2xl0 16 . After implantation, the arsenic is diffused to a depth of approximately 0.5 microns. In FIG. 11, masking layer 170 is removed in a conventional manner and neutral boron is implanted into the cathode regions 145 and anode region 148 to achieve the desired breakdown voltage of the zener diode.
• the trench DMOS transistor is completed in a conventional manner by forming and patterning a BPSG layer over the structure to define BPSG regions associated with the source and gate electrodes. Also, a drain contact layer is formed on the bottom surface of the substrate. Finally, a pad mask is used to define pad contacts.

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2001
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