WO2002056381A1 - Semiconductor device and production method therefor - Google Patents
Semiconductor device and production method therefor Download PDFInfo
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- WO2002056381A1 WO2002056381A1 PCT/JP2002/000247 JP0200247W WO02056381A1 WO 2002056381 A1 WO2002056381 A1 WO 2002056381A1 JP 0200247 W JP0200247 W JP 0200247W WO 02056381 A1 WO02056381 A1 WO 02056381A1
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- semiconductor layer
- semiconductor
- inductor
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- semiconductor device
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which an inductor is formed together with other active elements on the same semiconductor substrate and a method of manufacturing the same.
- the inductor as a passive element has been usually formed by a so-called external method in which an active element such as a transistor is formed on a semiconductor substrate and then connected by a wire bond wire.
- an active element such as a transistor
- the inductance of the connecting wires cannot be ignored.
- a method has been adopted in which an inductor is formed simultaneously with another active element on the same semiconductor substrate.
- the main part of the inductor 60 is a spiral A1 wiring layer 62 formed in a spiral shape using a low-resistance wiring material such as A1.
- the spiral A 1 wiring layer 62 is formed by a field oxide film 66 formed on the semiconductor substrate 64 and an interlayer insulating film. It is formed on the film 68.
- the gap between the spiral A 1 wiring layer 62 and the semiconductor substrate 64 is formed, and the field oxide film 66 and the interlayer insulating film 68 are interposed between the spiral A 1 wiring layer 62 and the semiconductor substrate 64.
- the parasitic capacitance generated between them has been reduced.
- a field oxide film 66 and an interlayer insulating film 68 provide Since there is a semiconductor substrate 64 having a certain degree of resistivity, at high frequencies, current flows on the semiconductor substrate 64 side, and the loss due to the current cannot be ignored, and the Q value, which is one index of the inductor characteristics, May occur. Further, the magnetic flux generated in the inductor 60 generates an eddy current in the semiconductor substrate 64, which causes a decrease in the inductance. In other words, these phenomena prevent the improvement of the device characteristics of the inductor 60 and bring about a great disadvantage in manufacturing a high-performance semiconductor integrated circuit.
- an inductor formed simultaneously with other active elements on the same semiconductor substrate has better device characteristics such as Q value than an inductor formed by an external method after forming other active elements. It was difficult to implement, and there were many disadvantages in producing high-performance integrated circuits.
- the present invention has been made in view of the above circumstances, and is directed to a semiconductor device and a method for manufacturing the same, in which an inductor is formed simultaneously with other active elements on the same semiconductor substrate, and a method for manufacturing the same. It is possible to prevent a decrease in the Q value and inductance due to the loss caused by the flow of current and to manufacture a semiconductor device having an inductor having good element characteristics and an inductor having such good element characteristics. It is an object of the present invention to provide a method of manufacturing a semiconductor device which is possible.
- a high-resistance layer may be interposed between the interlayer insulating film and the field oxide film below the inductor and the semiconductor substrate.
- a high resistance layer is interposed between the interlayer insulating film and the field oxide film below the inductor and the semiconductor substrate.
- the productivity decreases as the number of processes increases and the cost increases. Will be invited.
- this high-resistance layer is also used as an n-type epitaxial layer forming an n-type collector region of a normal NPN bipolar transistor.
- the n-type epitaxial layer is made to have a high resistance, disadvantages in the characteristics of the bipolar transistor arise, such as a decrease in the breakdown voltage between the collector and the emitter in the NPN bipolar transistor. Not desirable.
- the inductor is formed on the field oxide film in order to reduce the parasitic capacitance, but the n-type epitaxial layer forming the collector region is oxidized when the field oxide film below the inductor is formed. Therefore, the thickness of the n-type epitaxial layer under the field oxide film is inevitably reduced.
- a high-resistance layer is preferably interposed between the semiconductor substrate and the interlayer insulating film and the field oxide film below the inductor. How to form a high-resistance layer remains a challenge even today.
- a semiconductor device includes a substrate (a so-called semiconductor substrate), a semiconductor layer formed on the substrate and having an impurity concentration lower than that of the substrate (a so-called high-resistance semiconductor layer), and a semiconductor layer formed on the semiconductor layer. Characterized by having an insulating film formed and an inductor formed on the insulating film.
- the inductor is preferably made of a conductive film formed in a spiral shape.
- the substrate may be of the first conductivity type, and the semiconductor layer may be of the first conductivity type.
- the thickness of the semiconductor layer is preferably 5 to 15 m.
- the semiconductor layer preferably has an impurity concentration of 1 ⁇ 10 13 to 1 ⁇ 10 14 cm ⁇ 3 .
- the substrate is of a first conductivity type
- the semiconductor layer is formed of a first semiconductor layer of the first conductivity type
- a semiconductor layer is formed between the insulating film and the first semiconductor layer. It is characterized in that a second semiconductor layer of the second conductivity type is formed.
- the thickness of the first semiconductor layer is preferably larger than the thickness of the second semiconductor layer, for example, 5 to 15 m.
- the impurity concentration of the first semiconductor layer is set to 1 X 1 0 1 3 to 1 X 1 0 14 c ni one 3, the impurity concentration of the second half-conductor layer is a 1 X 1 0 15 to 1 X 1 0 16 cm- 3 It is preferable to do so.
- a semiconductor device is characterized in that, in each of the above semiconductor devices, the bipolar transistor and the photodiode are formed on the same substrate.
- the first semiconductor layer may constitute a photodiode anode or a force source
- the second semiconductor layer may constitute a photodiode cathode or an anode. I like it. That is, when the first semiconductor layer forms a photodiode, for example, an anode, the second semiconductor layer forms a photodiode, for example, a force diode, and conversely, the first semiconductor layer forms a photodiode.
- the first semiconductor layer constitutes a photodiode, for example, a force source
- the first semiconductor layer constitutes a photodiode, for example, an anode.
- the second semiconductor layer preferably forms a collector of a bipolar transistor.
- a region having a higher impurity concentration than the high-resistance semiconductor layer is formed below the region other than the region where the inductor is formed.
- a method of manufacturing a semiconductor device includes a step of forming a semiconductor layer (so-called high-resistance semiconductor layer) having a lower impurity concentration than a substrate (so-called semiconductor substrate), and forming an insulating film on the semiconductor layer. Forming a conductive film on the insulating film, and forming the inductor by patterning the conductive film in a spiral shape.
- the substrate can be of the first conductivity type, and the semiconductor layer can be of the first conductivity type.
- the thickness of the semiconductor layer is preferably 5 to 15 / m.
- the impurity concentration of the semiconductor layer is arbitrarily preferred to a 1 X 1 0 1 3 to 1 X 1 0 1 4 cm- 3 .
- the method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device according to the above, wherein the semiconductor layer is formed of a first semiconductor layer of a first conductivity type; A step of continuously forming a second semiconductor layer of the second conductivity type on the first semiconductor layer.
- the thickness of the first semiconductor layer is equal to the thickness of the second semiconductor layer. Thickness is preferred, for example 5 to 15 m.
- the impurity concentration of the first semiconductor layer is set to 1 X 1 0 1 3 to 1 X 1 0 1 4 cm one 3, the impurity concentration of the second semiconductor layer is 1 X 1 0 1 [delta] to 1 X 1 0 1 6 cm- A value of 3 is preferred.
- a method of manufacturing a semiconductor device according to the present invention is characterized in that, in the method of manufacturing each of the above semiconductor devices, a step of forming a bipolar transistor and a photodiode on the same substrate is provided.
- the first semiconductor layer is configured as an anode or a force source of a photodiode
- the second semiconductor layer is configured as a cathode or a cathode of a photodiode.
- the second semiconductor layer is formed so as to function as a collector of the bipolar transistor.
- the impurity concentration is higher than that of the high-resistance semiconductor layer (semiconductor layer or first semiconductor layer) below the region other than the region where the conductor is formed. It is preferable that the method further includes a step of forming a region.
- a substrate, a semiconductor layer formed on the substrate and having an impurity concentration lower than the impurity concentration of the substrate, an insulating film formed on the semiconductor layer By having the formed inductor, a semiconductor layer having a low impurity concentration, that is, a high-resistance semiconductor layer is interposed between the insulating film and the substrate below the inductor. Therefore, even at a high frequency, it is possible to reduce the current flowing through the high-resistance semiconductor layer or the substrate, and to suppress the loss due to the current.
- the substrate is of the first conductivity type
- the semiconductor layer is formed of the first semiconductor layer of the first conductivity type.
- the first semiconductor layer of the first conductivity type (high-resistance semiconductor layer) and the second semiconductor layer of the second conductivity type are interposed between the insulating film below the inductor and the substrate. 2 A structure in which a pn junction formed with the semiconductor layer is interposed.
- the first semiconductor layer (high-resistance semiconductor layer) of the first conductivity type and the second semiconductor layer of the second conductivity type are provided. Since a relatively small pn junction capacitance is added in series, the overall parasitic capacitance can be significantly reduced. Therefore, it is possible to realize a high-performance inductor having a high Q value and a high inductance and good element characteristics as compared with the conventional case, and further to realize a semiconductor integrated circuit having higher functions and higher performance.
- the bipolar transistor and the photo diode are further formed on the same substrate, so that a high performance and high performance having an inductor, a bipolar transistor and a photo diode are mounted.
- a semiconductor integrated circuit can be realized.
- Photodiodes are widely used in, for example, optical sensors that convert optical signals into electrical signals in various photoelectric conversion devices.
- the first semiconductor layer of the first conductivity type is used as a photodiode anode or When the second semiconductor layer of the second conductivity type is formed as a force diode or anode of a photodiode, the first conductivity type which is a high resistance semiconductor layer is used.
- the first semiconductor layer of the second conductivity type is also used as the p-type semiconductor layer serving as the anode of the PN photodiode or the n-type semiconductor layer serving as the card, and the second semiconductor layer of the second conductivity type is used as the PN photodiode.
- the second semiconductor layer When the second semiconductor layer is configured as a collector of a bipolar transistor, the second semiconductor layer is also used as a semiconductor layer serving as a collector region of the bipolar transistor, so that a special process dedicated to forming the inductor is used. Need not be increased. Therefore, a high-performance inductor with good device characteristics and a high Q value and high inductance can be realized without incurring a decrease in productivity or an increase in cost.
- the semiconductor integrated circuit of the present invention can be realized. '
- a high-resistance semiconductor layer is formed under a region other than a region corresponding to a region where the inductor is formed.
- a semiconductor layer having a lower impurity concentration than the substrate is formed on the substrate, an insulating film is formed on the semiconductor layer, and a conductive film is formed on the insulating film. Then, this conductive film is By forming the inductor by patterning in a spiral shape, a semiconductor layer having a low impurity concentration, that is, a structure in which a high-resistance semiconductor layer is interposed between the insulating film and the substrate below the inductor is easily formed. . Therefore, even at a high frequency, the current flowing in the high-resistance semiconductor layer or the substrate can be reduced, and the loss due to the current can be suppressed.
- the semiconductor layer is formed of a first semiconductor layer of a first conductivity type
- the first semiconductor layer of the first conductivity type (high) is provided between the insulating film below the inductor and the substrate.
- a structure in which the resistive semiconductor layer) and the second semiconductor layer of the second conductivity type are interposed by pn junction is easily formed. Therefore, between the inductor and the substrate, in addition to the capacitance formed by the insulating film, a comparison is made between the first semiconductor layer (high-resistance semiconductor layer) of the first conductivity type and the second semiconductor layer of the second conductivity type.
- An extremely small pn junction capacitance is added in series, and the overall parasitic capacitance can be reduced significantly.
- a step of forming a photo diode a high-performance and high-performance semiconductor integrated circuit equipped with an inductor, a bipolar transistor, and a photo diode can be manufactured.
- This photodiode is widely used in, for example, optical sensors that convert optical signals into electrical signals in various photoelectric conversion devices.
- the first semiconductor layer of the first conductivity type is configured as an anode or cathode of a photodiode
- the second semiconductor layer of the second conductivity type is a photodiode or a power source.
- the first semiconductor layer interposed between the insulating film below the inductor and the substrate serves as an anode of a PN photodiode or a p-type semiconductor layer.
- the second semiconductor layer is formed simultaneously with the n-type semiconductor layer serving as a force source of the PN photodiode or the p-type semiconductor layer serving as the anode. Since it is formed in a complicated manner, it is not necessary to increase the number of special steps dedicated for forming the inductor. As a result, high-performance semiconductors with high Q value and high inductance and good device characteristics are realized without incurring a drop in productivity or increase in cost. An integrated circuit can be realized.
- the second semiconductor layer When the second semiconductor layer is formed so as to function as a collector of the bipolar transistor, the second semiconductor layer interposed between the insulating film below the inductor and the substrate is formed by the semiconductor layer serving as a collector region of the bipolar transistor. Since they are formed simultaneously, there is no need to increase the number of special steps dedicated for forming the inductor. Obedience Therefore, a high-performance inductor with good device characteristics and a high Q value and high inductance has been realized without incurring a decrease in productivity or an increase in cost. A circuit can be realized.
- the high-resistance semiconductor is formed under a region other than a region where the inductor is formed.
- Layer (semiconductor layer, first semiconductor layer) ' which has a higher impurity concentration than that of the first semiconductor layer, a highly reliable semiconductor integrated circuit that is unlikely to cause latch-up problems.
- FIG. 1 shows a photodiode according to an embodiment of the present invention.
- FIG. 9 is a process cross-sectional view (part 1) for describing a method for manufacturing a semiconductor integrated circuit mixedly mounted on the same semiconductor substrate together with a diode and a bipolar transistor.
- FIG. 2 is a process cross-sectional view for explaining a method of manufacturing a semiconductor integrated circuit in which an inductor according to an embodiment of the present invention is mounted together with a photodiode and a bipolar transistor on the same semiconductor substrate (part 2). It is.
- FIG. 3 is a process cross-sectional view for explaining a method of manufacturing a semiconductor integrated circuit in which an inductor according to an embodiment of the present invention is mounted together with a photodiode and a bipolar transistor on the same semiconductor substrate. ).
- FIG. 4 is a process cross-sectional view illustrating a method of manufacturing a semiconductor integrated circuit in which an inductor according to an embodiment of the present invention is mounted together with a photodiode and a bipolar transistor on the same semiconductor substrate.
- FIG. 5 is a process cross-sectional view for explaining a method of manufacturing a semiconductor integrated circuit in which an inductor according to an embodiment of the present invention is mounted together with a photodiode and a bipolar transistor on the same semiconductor substrate. (Part 5).
- FIG. 6 shows that the inductor according to the embodiment of the present invention is a photodiode.
- FIG. 10 is a process cross-sectional view (part 6) for describing the method of manufacturing the semiconductor integrated circuit mixedly mounted on the same semiconductor substrate together with the bipolar transistor and the bipolar transistor.
- FIG. 7 is a process cross-sectional view for explaining a method of manufacturing a semiconductor integrated circuit in which an inductor according to an embodiment of the present invention is mounted together with a photodiode and a bipolar transistor on the same semiconductor substrate (part 7). It is.
- FIGS. 8A and 8B are a plan view and a cross-sectional view taken along the line AA, respectively, showing an inductor completed through the steps shown in FIGS.
- 9A and 9B are a plan view showing a modification of the inductor shown in FIGS. 8A and 8B, respectively, and a sectional view taken along line AA.
- FIG. 10A and FIG. 10B are a plan view and a cross-sectional view taken along line AA, respectively, of a conventional inductor.
- FIGS. 1 to 7 show that an inductor according to an embodiment of the present invention is mounted on a same semiconductor substrate together with a photodiode and a bipolar transistor.
- FIG. 4 is a process cross-sectional view for describing a mixedly mounted semiconductor integrated circuit and a method of manufacturing the same.
- FIGS. 8A and 8B are a plan view and a plan view, respectively, showing the completed ink through the steps shown in FIGS. 1 to 7.
- FIG. 2 is a sectional view taken along line A.—A of FIG. 9A and 9B are cross-sectional views showing a modification of the inductor shown in FIGS. 8A and 8B.
- the formation regions of the inductor, the photodiode, and the bipolar transistor formed on the semiconductor substrate are referred to as an inductor formation region A and a photodiode region, respectively.
- the description will be made with the tip formation region B and the bipolar transistor formation region C.
- a thin thermal oxide film is formed on the surface of a p-type semiconductor substrate 10 having an impurity concentration of about 1 ⁇ 10 15 cm ⁇ 3, and a photo resist patterned by a usual photolithography technique is used as a mask. and, to Lee down inductor-forming region a to the entire region, using conventional Inpura Ntesho emission technology, acceleration voltage 3 0 ke V, a dose of 1 x 1 0 1 S cm one about two conditions by, for example, boron ( Selectively implant p-type impurities such as B).
- the high-concentration p-type impurity ions implanted into the surface of the p-type semiconductor substrate 1Q are activated by heat treatment at a temperature of 1200 ° C. for about 1 hour, and diffused into the surface of the p-type semiconductor substrate 10; A high concentration p + -type semiconductor region 12 having a peak concentration of about 1 ⁇ 10 18 cm— s is formed. Then, the above-mentioned thin thermal oxide film is entirely separated using hydrofluoric acid (HF) (see Fig. 1).
- HF hydrofluoric acid
- a low-concentration P ⁇ -type epitaxial layer 1 having a thickness of about 10 m and an impurity concentration of about 2 ⁇ 10 Hcm ⁇ 3 is formed on the p-type semiconductor substrate 10 and the P + -type semiconductor region 12.
- This p-type epitaxial layer 14 is for forming a photodiode diode later (see Fig. 2).
- a thin thermal oxide film is formed on the surface of the p-type epitaxial layer 14, and the photo resist patterned by a usual photolithography technique is used as a mask to form the inductor formation region A and the photo resist.
- P-type epitaxy in all regions except the photodiode formation region B To the layer 1 4, using conventional Ion'i Npurate one sucrose emission technology ', the acceleration voltage 5 0 0 ke V, to p.
- Type impurity such as more example Poron to dose 1 x 1 0 12 cm 2 about conditions Inject ion selectively.
- low-concentration p-type impurity ions are implanted into the p-type epitaxial layer 14 such as the bipolar transistor formation region C and activated and diffused by heat treatment at a temperature of 1200 ° C. for about 1 hour.
- a low-concentration p-type shoulder 16 having an impurity concentration near the surface of about 1 ⁇ 10 15 cm 3 is formed.
- the above-described thin thermal oxide film is entirely separated using hydrofluoric acid.
- the impurity concentration in the vicinity of the surface of the p-type well layer 16 corresponds to the substrate concentration of the bipolar transistor, the characteristic matching with the bipolar transistor formed in the bipolar transistor formation region C is required. Becomes possible (see Fig. 3) o
- a vapor phase of antimony (Sb) is deposited on the surface of the p-type p-type layer 16 in the bipolar transistor formation region C, for example, at a temperature of 110 ° to 125 ° C. for about 30 to 60 minutes.
- Antimony which is an n-type impurity, is selectively added by diffusion to form a high-concentration n + -type buried layer 18 for reducing parasitic resistance.
- the thermal diffusion processing for forming the p-type well layer 16 in the step shown in FIG. 3 is also used as the thermal diffusion processing for forming the p + -type buried layer 18. It is also possible to reduce the number of times. Then, the whole substrate, that is,!
- n-type epitaxial layer 20 of about 15 cm 3 is formed (see FIG. 4).
- a field oxide film 22 having a thickness of about 400 to 150 O nm is formed on the inductor formation region A and the photo diode formation region. It is selectively formed in the element isolation portion (field portion) of B and the bipolar transistor formation region C. That is, a stacked film of a Si oxide film and a Si nitride film is formed on an n- type epitaxial layer and a 20 as usual, and the stacked film is patterned by photolithography technology.
- LOCOS Local Oxidation of Silicon; selective oxidation
- the exposed n-type epitaxial layer 20 is removed.
- the stacked layer is selectively oxidized using the Si nitride film as a mask to form a final oxide film 22.
- the n-type epitaxial layer 20 may not remain in the inductor formation region A.
- the invention is not so limited.
- the case where the n-type epitaxial layer 20 remains between the p-type epitaxial layer 14 and the p-type dielectric layer 16 and the field oxide film 22 is shown in FIG. 5).
- an n + -type collector extraction region 24 connected to the n + -type buried layer 18 of the bipolar transistor formation region C is formed in accordance with the manufacturing process of the bipolar transistor and the photodiode, thereby forming a photodiode.
- a p + type anode extraction region 26 connected to the p ⁇ type epitaxial layer 14 in the region B is formed, and a p + type element isolation region 28 is formed under the field oxide film 22 to form a photodiode. Separation of the head formation region B and the bipolar transistor formation region C is performed.
- the n-type epitaxial layer 20 under the field oxide film 22 in the inductor formation region A is thereafter formed into a photodiode with the n-type semiconductor layer 20a.
- the n- type epitaxial layer 20 in region B is replaced with the n-type force source layer 20
- the n-type epitaxial layer 20 in the transistor formation region C is called an n-type collector layer 20 c, and the p-type epitaxial layer 14 below the field oxide film 22 in the inductor formation region A is p-type high.
- the resistive semiconductor layer 14a and the p-type epitaxial layer 14 below the n-type force source layer 20b in the photodiode formation region B will be referred to as a p-type anode layer 14b.
- an n + -type cathode extraction region 30 is formed on the surface of the n-type force source layer 20 b in the photodiode formation region B, and the n-type collector layer 2 in the bipolar transistor formation region C is formed.
- a p-type base region 32 is formed on the 0 c surface, and a p + -type base extraction region 34 is formed on the surface of the p-type base region 32.
- an emitter extraction electrode 36 made of polysilicon doped with n-type impurities on the mold base region 32 impurity diffusion from the emitter extraction electrode 36 causes P
- An n + -type emitter region 38 is formed on the surface of the mold base region 32.
- a first interlayer insulating film 40 made of, for example, a Si oxide film is formed on the entire surface of the substrate, the photo diode forming region B and the bipolar are formed by using photolithography technology and etching technology.
- a contact hole is formed at a predetermined position in the transistor forming region C.
- the A1 film is subjected to a patterning process using a photolithography technique and an R1E method.
- a lead A1 wiring layer 42 for taking out a terminal of an inductor to be formed later from the inside is formed.
- the photodiode formation region B the anode A 1 connected to the p + -type anode extraction region 26 and the n + -type cathode extraction region 30 and the electrode 42 a and the force source A
- One electrode 4 2 b is formed.
- the emitter extraction electrode 36 is used. Taken out to the n + -type emitter Tsu evening region 3 is connected to the 8 E Mi jitter A 1 electrode 4 2 E, p + -type base contact base connected to the region 3 4 A 1 electrode 4 2 B, and the n + -type collector A collector A 1 electrode 4 2 C connected to the region 24 is formed.
- a PN photodiode 44 is completed in the photodiode forming region B
- an NPN bipolar transistor 46 is completed in the bipolar transistor forming region C (see FIG. 6).
- the steps of forming the PN photodiode 44 and the NPN bipolar transistor 46 are basically described as being performed in accordance with the existing manufacturing process, the p-type of the inductor formation region A is described.
- the p_ type epitaxial layer 14 for forming the p-type anode layer 14 b of the p-type anode layer 14 b and the p-type anode layer 14 b of the PN photodiode 44 and the n of the inductor forming region A N-type epitaxial layer for forming the type semiconductor layer 20a, the n-type force source layer 20b of the PN photodiode 44, and the n-type collector layer 20c of the NPN bipolar transistor 46.
- the lead A 1 wiring layer 42 in the inductor formation region A is composed of the anode A 1 electrode 42 a and the force source A 1 electrode 42 b of the PN photodiode 44 and the NPN bipolar transistor.
- 46 Emitter A1 electrode 42E, base A1 electrode 42B, and collector A1 electrode 42C are formed simultaneously in the same process, but different There is no problem even if it is formed separately.
- the A.1 film is patterned using photolithography technology and the R1E method to form a spiral A1 wiring layer 50a on the interlayer insulating film 48 in the inductor formation region A.
- an A1 terminal electrode 50b for external connection connected to the spiral A1 wiring layer 50a through the A1 wiring layer 42 is formed at the inner end of the spiral A1 wiring layer 50a.
- an inductor 52 including the spiral A1 wiring layer 50a, the lead A1 wiring layer 42, and the A1 terminal electrode 50b for external connection is completed in the inductor formation region A. (See Figure 7).
- an overcoat film is formed on the entire surface of the substrate, and a bad portion is opened at a predetermined position.
- the photodiode and the bipolar are formed on the same p-type semiconductor substrate 10.
- the inductor 52 completed by the above steps will be described with reference to FIGS. 8A and 8B.
- the spiral A 1 wiring layer 50 a of the inductor 52 has its inner end pulled out and the A 1 wiring layer
- Such an inductor 52 is formed on a p-type semiconductor substrate 10 by forming a p ⁇ type high-resistance semiconductor layer 14 a, an ⁇ -type semiconductor layer 20 a, a field oxide film 22, and a The first and second interlayer insulating films 40 and 48 are formed. In other words, a p-type high-resistance semiconductor having a pn junction between the p-type semiconductor substrate 10 and the field oxide film 22 and the first and second interlayer insulating films 40 and 48. 14a and the n-type semiconductor layer 20a are interposed.
- Spiral A1 forming the main part of the inductor 5 between the p-type semiconductor substrate 10 under the wiring layer 50a and the field oxide film 22 and the first and second interlayer insulating films 40.48
- the p-type high-resistance semiconductor layer 14a not only intervenes, but also this! ) — Type high resistance semiconductor layer 1
- a structure is also formed in which an n-type semiconductor layer 20a that is in pn junction with 4a is interposed, a field oxide film 22 between the inductor and the p-type semiconductor substrate 10 is formed.
- a relatively small pn junction capacitance of the p-type high resistance semiconductor layer 14a and the n-type semiconductor layer 20a is added in series Therefore, the overall parasitic capacitance is greatly reduced compared to the conventional case, and even at high frequencies, the n-type semiconductor layer 20a, the p-type high-resistance semiconductor layer 14a, and the p-type semiconductor layer
- the current flowing through the substrate 10 can be reduced, and the loss due to the current can be suppressed.
- the p-type high-resistance semiconductor layer 14a below the spiral A1 wiring layer 50a of the inductor 52 is formed in the same process as the p-type anode layer 14b of the PN photodiode 44.
- the n-type semiconductor layer 20a is formed simultaneously, and the n-type force source layers 2Ob and N of the PN photodiode 44 are formed. Since the n-type collector layer 20 of the PN bipolar transistor 46 is formed simultaneously with the same process in the same process, it is not necessary to add a special process dedicated for forming the inductor 52.
- a high-performance inductor having high Q value and high inductance and good device characteristics can be realized without incurring a decrease in productivity and a rise in cost, and as a result, a semiconductor with higher performance and higher performance An integrated circuit can be realized.
- the n-type epitaxial layer 20 is selectively oxidized by the LOCOS method to form the field oxide film 22, the formation of the field oxide film 22 is performed. It is stated that if a method of removing part or all of the previously exposed n-type epitaxial layer 20 is employed, the n-type epitaxial layer 20 may not remain in the inductor formation region A. However, the present modified example relates to an inductor in a case where there is no residual.
- the inductor 54 according to the present modification has the same planar shape as that shown in FIG. 8A of the above embodiment, but as shown in FIG. 9B.
- the spiral A 1 wiring layer 50 a of the inductor 52 is formed on the p-type semiconductor substrate 10 by a p-type high resistance. It is formed via a semiconductor layer 14a, a field oxide film 22, and first and second interlayer insulating films 40 and 48. In other words, only the p-type high resistance semiconductor layer is interposed between the type semiconductor substrate 10 and the field oxide film 22 and the first and second interlayer insulating films 40 and 48. ing.
- the p-type semiconductor substrate 10 below the spiral A1 wiring layer 50a, which is the main part of the inductor 54, and the field oxide film 22 and the first and second layers Insulation film 40, 4 8 Since a structure in which the p ⁇ type high resistance semiconductor layer 14 a is interposed therebetween is formed, the P ⁇ type high resistance semiconductor layer 14 a and the p type semiconductor substrate 10 are formed even at a high frequency. The current flowing through the current can be reduced, and the loss due to the current can be suppressed. Further, in the manufacturing process, as in the case of the above-described embodiment, it is not necessary to increase the number of special steps dedicated to forming the inductor 54. Therefore, the same effect as in the case of the above embodiment can be obtained.
- the inductor 52 is simultaneously provided on the same p-type semiconductor substrate 10 together with the n-type force source layer 20 b of the PN photodiode 44 and the NPN bi-bora transistor 46.
- a bipolar transistor having another structure is used instead of the NPN bipolar transistor 46.
- a transistor or a PNP bipolar transistor having a different polarity may be formed, or a CMOS (Complementary Metal Oxide Semiconductor) transistor may be formed.
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US10/221,802 US7227222B2 (en) | 2001-01-16 | 2002-01-16 | Semiconductor device and manufacturing method thereof |
JP2002556948A JPWO2002056381A1 (ja) | 2001-01-16 | 2002-01-16 | 半導体装置及びその製造方法 |
KR1020027011901A KR20020084177A (ko) | 2001-01-16 | 2002-01-16 | 반도체 장치 및 그 제조 방법 |
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JP2001007519 | 2001-01-16 | ||
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PCT/JP2002/000247 WO2002056381A1 (en) | 2001-01-16 | 2002-01-16 | Semiconductor device and production method therefor |
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US (1) | US7227222B2 (ja) |
JP (1) | JPWO2002056381A1 (ja) |
KR (1) | KR20020084177A (ja) |
WO (1) | WO2002056381A1 (ja) |
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KR100510913B1 (ko) * | 2002-07-26 | 2005-08-25 | 동부아남반도체 주식회사 | 알에프 반도체소자 제조방법 |
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JP4355128B2 (ja) * | 2002-07-04 | 2009-10-28 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
SE526360C2 (sv) | 2004-01-09 | 2005-08-30 | Infineon Technologies Ag | Monolitiskt integrerad krets |
KR100725714B1 (ko) * | 2006-08-29 | 2007-06-07 | 동부일렉트로닉스 주식회사 | 인덕터 및 인덕터 제조방법 |
KR100747657B1 (ko) * | 2006-10-26 | 2007-08-08 | 삼성전자주식회사 | 매크로 및 마이크로 주파수 튜닝이 가능한 반도체 소자 및이를 갖는 안테나와 주파수 튜닝 회로 |
JP2009260160A (ja) * | 2008-04-21 | 2009-11-05 | Panasonic Corp | 光半導体装置 |
KR200454325Y1 (ko) * | 2008-09-10 | 2011-06-28 | 한윤교 | 냉각 테이블 발광장치 |
JP6532848B2 (ja) * | 2016-09-15 | 2019-06-19 | 株式会社東芝 | 半導体装置 |
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JPS52116002A (en) * | 1976-03-25 | 1977-09-29 | Fujitsu Ltd | Photo receiving circuit |
JPS55101066U (ja) * | 1979-01-10 | 1980-07-14 | ||
JPH05264347A (ja) * | 1991-04-26 | 1993-10-12 | Mitsubishi Electric Corp | 光電変換回路 |
EP0999579A2 (en) * | 1998-11-04 | 2000-05-10 | Lucent Technologies Inc. | An inductor or low loss interconnect in an integrated circuit |
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US2001A (en) * | 1841-03-12 | Sawmill | ||
JPS55101066A (en) | 1979-01-29 | 1980-08-01 | Toshiba Corp | Fault detector of rotary rectifier |
US5268309A (en) * | 1984-09-01 | 1993-12-07 | Canon Kabushiki Kaisha | Method for manufacturing a photosensor |
US5578860A (en) * | 1995-05-01 | 1996-11-26 | Motorola, Inc. | Monolithic high frequency integrated circuit structure having a grounded source configuration |
US6236101B1 (en) * | 1997-11-05 | 2001-05-22 | Texas Instruments Incorporated | Metallization outside protective overcoat for improved capacitors and inductors |
US6225182B1 (en) | 1999-08-30 | 2001-05-01 | Agere Systems Guardian Corp. | Simplified high Q inductor substrate |
-
2002
- 2002-01-16 US US10/221,802 patent/US7227222B2/en not_active Expired - Fee Related
- 2002-01-16 WO PCT/JP2002/000247 patent/WO2002056381A1/ja active Application Filing
- 2002-01-16 KR KR1020027011901A patent/KR20020084177A/ko not_active Application Discontinuation
- 2002-01-16 JP JP2002556948A patent/JPWO2002056381A1/ja active Pending
Patent Citations (4)
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JPS52116002A (en) * | 1976-03-25 | 1977-09-29 | Fujitsu Ltd | Photo receiving circuit |
JPS55101066U (ja) * | 1979-01-10 | 1980-07-14 | ||
JPH05264347A (ja) * | 1991-04-26 | 1993-10-12 | Mitsubishi Electric Corp | 光電変換回路 |
EP0999579A2 (en) * | 1998-11-04 | 2000-05-10 | Lucent Technologies Inc. | An inductor or low loss interconnect in an integrated circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100510913B1 (ko) * | 2002-07-26 | 2005-08-25 | 동부아남반도체 주식회사 | 알에프 반도체소자 제조방법 |
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US20030151115A1 (en) | 2003-08-14 |
US7227222B2 (en) | 2007-06-05 |
JPWO2002056381A1 (ja) | 2004-05-20 |
KR20020084177A (ko) | 2002-11-04 |
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