WO2001096956A2 - Procede pour produire un masque plat sur des surfaces a reliefs - Google Patents

Procede pour produire un masque plat sur des surfaces a reliefs Download PDF

Info

Publication number
WO2001096956A2
WO2001096956A2 PCT/DE2001/002070 DE0102070W WO0196956A2 WO 2001096956 A2 WO2001096956 A2 WO 2001096956A2 DE 0102070 W DE0102070 W DE 0102070W WO 0196956 A2 WO0196956 A2 WO 0196956A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
mask
planar
producing
topology
Prior art date
Application number
PCT/DE2001/002070
Other languages
German (de)
English (en)
Other versions
WO2001096956A3 (fr
Inventor
Maik Stegemann
Ines Uhlig
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001096956A2 publication Critical patent/WO2001096956A2/fr
Publication of WO2001096956A3 publication Critical patent/WO2001096956A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface

Definitions

  • the present invention relates to a method for producing a planar mask on topology-containing surfaces and in particular to a method for producing a planar STI hard mask for realizing structures smaller than 170 nm in DRAM cells.
  • FIG. 1 shows a simplified sectional view of a conventional photo resist soft mask for realizing, for example, shallow trench isolation (STI) in a DRAM cell.
  • a grave Canal- of capacitors' 20 are formed in a semiconductor substrate 10 having at an upper region an insulating collar or collar 21 aufwei- sen and in a lower region, a dielectric 22, which acts as the capacitor dielectric.
  • Trench capacitors have, for example, a polysilicon filling 23 in their interior, which acts as an electrode of the trench capacitor 20.
  • a counter electrode, not shown, is located in the lower region of the trench capacitor 20 in the semiconductor substrate 10, as a result of which a capacitor with sufficient charge holding capacity is created.
  • shallow trench isolation In which the semiconductor substrate 10 or the polysilicon filler material 23 is preferably up to the insulation collar 21 removed and filled with insulating material.
  • STI shallow trench isolation
  • the semiconductor substrate 10 or the polysilicon filler material 23 is preferably up to the insulation collar 21 removed and filled with insulating material.
  • the pad layer 11 preferably consists of Si 3 N 4 .
  • an organic antireflection layer 3 ' is applied to the surface in the conventional photo-resist soft mask according to FIG. 1, which results in an improved (planar) surface.
  • a photo resist 4 is spun on, exposed using conventional photolithographic processes and developed, whereby the mask shown in FIG. 1 is obtained.
  • a disadvantage of such a conventional method for producing a is the insufficient planarity of the organic anti-reflection layer 3 ', which requires a relatively thick photoresist layer 4.
  • the lithography process window is thereby reduced, which makes subsequent subsequent formation of firmly defined, shallow trench insulation (STI) difficult.
  • this method has the disadvantage that at a later ITM-etching the organic antireflection layer 3 ⁇ and the pad layer 11 is a high paint consumption occurs. If the paint mask or the photo resist 4 is too thin, this can lead to the etching of active areas on the side walls in the semiconductor substrate 10, as a result of which the yield is significantly reduced.
  • FIGS 2 and 3 show simplified sectional views of a conventional BSG hard mask with an organic and an inorganic anti-reflection layer.
  • the same reference numerals here again designate the same or similar layers, which is why a repeated description is omitted below.
  • the topology-containing surfaces of the semiconductor substrate 10 with its trench capacitors 20 are compensated for using so-called hard masks.
  • a hard mask layer 5 made of, for example, borosilicate glass (BSG) is formed on the pad layer 11 or the intervening depressions, which results in an almost planar surface.
  • BSG borosilicate glass
  • this almost planar surface can be further leveled by depositing an organic antireflection layer 3 'or can only be coated with an inorganic antireflection layer 3 according to FIG. 3.
  • a photoresist or photo is again applied to the organic antireflection layer 3 'or the inorganic antireflection layer 3.
  • the invention is therefore based on the object of creating a method for producing a planar mask on topology-containing surfaces which enables greater accuracy and thus greater yield with very small structure sizes.
  • a completely planar mask is obtained which can be made as thick as desired, as a result of which both a larger lithography process and a larger etching process are Window received.
  • a selective oxidation method for depositing silicon dioxide is used only for filling up the depressions within the depressions. In this way, a particularly simple and inexpensive manufacturing process is obtained using a pad layer.
  • An inorganic and / or organic antireflection layer is preferably used as the antireflection layer, as a result of which a homogeneous thickness is obtained both over a strongly topology-containing cell field and in an edge region with larger structures.
  • Figure 1 is a simplified sectional view of a conventional photo resist soft mask
  • FIG. 2 shows a simplified sectional view of a conventional BSG hard mask with an organic anti-reflection layer
  • FIG. 3 shows a simplified sectional view of a conventional BSG hard mask with an inorganic anti-reflection layer
  • FIGS. 4A to 4 F show simplified sectional views to illustrate the respective method steps for producing a planar mask according to the present invention
  • FIGS. 5A to 5C simplified sectional views to illustrate the method steps for producing a flat trench isolation in DRAM cells with the mask produced in FIGS. 4A to 4F.
  • FIGS. A to 4F show simplified sectional views to illustrate respective method steps for producing a planar mask according to the present invention, the same reference symbols denoting the same or similar elements or layers as in FIGS. 1 to 3 and to avoid repetition of a detailed description is subsequently waived.
  • the method for producing a planar mask according to the invention on topology-containing surfaces is again described in accordance with FIGS. 4A to 4F using a DRAM memory circuit as an example.
  • the invention is not restricted to this and rather encompasses all other manufacturing methods for realizing a planar mask on topology-containing surfaces, such as e.g. in bipolar circuits, embedded circuits etc.
  • a multiplicity of trench capacitors 20 are located in a semiconductor substrate 10, which are formed as deep trenches in the semiconductor substrate 10. To prevent leakage currents or for insulation, these have Benkondensatoren 20 in their upper region insulation collars
  • the trench capacitors 20 are here filled with a conductive filler 23, which consists, for example, of doped polysilicon and serves as an electrode for the trench capacitor 20.
  • a dielectric layer 22, which essentially represents a storage dielectric, is located on the walls of the trench capacitors 20 for isolation from the semiconductor substrate 10.
  • a further electrode, not shown, is located in a lower region of the trench capacitor 20 within the semiconductor substrate 10, as a result of which a counter electrode to the filling material 23 is realized.
  • depressions V are formed on the surface, which are formed, for example, in a pad layer 11 and the semiconductor substrate 10.
  • the pad layer 11 preferably consists of Si 3 N 4 .
  • a selective filling of the depressions V in the topology-containing surface of the semiconductor substrate 10 or of the wafer is now carried out in a first method step.
  • This selective filling of the depressions V is preferably implemented by a selective oxidation method, as is known for example from the publication WO98 / 03992.
  • SELOX process an oxide 1 (for example SiO 2 ) is deposited selectively to the pad layer 11 only in the depressions V until the height of the pad layer 11 is reached. In this way, an almost complete planar surface is obtained.
  • a conformal mask layer 2 is deposited over the entire area on the surface of the semiconductor substrate 10 or of the wafer in a subsequent step.
  • this mask layer 2 one preferably uses a silicon O xid existing hard mask layer. Then at the
  • the antireflection layer 3 can either consist of an inorganic antireflection layer such as Si x O y N ( i- x - y ) or an organic one
  • Lacquer layer such as DUV30.
  • an organic antireflection layer 3 In contrast to the prior art according to FIGS. 1 and 2, when an organic antireflection layer 3 is used, its layer thickness is the same in all areas of the wafer, since it is not misused to level out unevenness.
  • the antireflection layer 3 thus serves, in particular, to reduce or completely eliminate disturbing reflections during a subsequent exposure of a photo lacquer or photo resist.
  • this photoresist or photo resist 4 is formed, exposed and developed over the entire surface in a subsequent step and with a layer thickness that is relatively small compared to the prior art according to FIGS. 1 to 3, thereby realizing a photomask. Due to the very small layer thicknesses for the photomask 4 for the first time, a sufficiently sharp mask is obtained, which is why structure sizes below 170 nm can also be realized reliably and with a high yield.
  • a so-called HM etching is carried out, in which both the antireflection layer 3 and the mask layer 2 up to the SELOX oxide 1 and the pad layer 11 are removed using the photoresist or photo resist 4.
  • the photo resist 4 and the antireflection layer 3 are completely removed in a subsequent process step (resist strip) and a so-called ITM etching is carried out into the semiconductor substrate 10.
  • both the SELOX oxide 1 and the exposed pad layer 11 are completely removed and the semiconductor substrate 10 or the polysilicon filling material 23 of the trench capacitors 20 is slightly etched.
  • the photo resist 4 can be eliminated in the method described above and the method steps according to FIGS. 4E and 4F can be carried out in a common etching step.
  • FIGS. 5A to 5C show simplified sectional views for illustrating method steps for producing a shallow trench isolation in DRAM cells.
  • the same reference numerals again designate the same elements or Layers as in Figures 1 to 4, which is why a repeated description is omitted below.
  • FIG. 5A using the planar mask produced in FIGS. 4A to 4F, so-called IT etching is used to form a shallow trench isolation (STI) in the semiconductor substrate 10 in such a way that a depression is formed up to the insulation collars 21 of the trench capacitors 20 .
  • This etching step shown in FIG. 5A can preferably also be combined with the etching steps shown in FIGS. 4E and 4F, which results in a further simplification of the process.
  • the SELOX oxide 1 and the remaining hard mask layer 2 are completely removed and an HDP-Si0 2 layer 6 (high density plasma) is deposited on the surface or in the depression.
  • an HDP-Si0 2 layer 6 high density plasma
  • the adjacent trench capacitors 20 are isolated from one another, only an open region of the trench capacitor 20 serving as charge supply and discharge to a field effect transistor, not shown.
  • the SELOX oxide 1 and the hard mask layer 2 can optionally remain on the surface.
  • the surface of the wafer is then planarized, preferably using chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the invention has been described above using a planar mask for shallow trench isolation in DRAM cells. However, it is not restricted to this and rather encompasses all further methods for producing a planar mask on topology-containing surfaces, as can occur, for example, in bipolar circuits and / or embedded circuits.

Abstract

L'invention concerne un procédé pour produire un masque plat sur des surfaces à reliefs. Selon l'invention, des évidements (V) sont remplis d'un oxyde sélectif (1), puis une couche de masquage (2), de forme correspondante, et une couche antireflet (3) sont appliquées. Cette planéité améliorée permet d'obtenir une fenêtre de processus lithographique de taille plus importante. L'utilisation de couches antireflet organiques plus minces permet simultanément de réduire la consommation de résine photosensible pendant l'attaque et d'obtenir ainsi une fenêtre de processus d'attaque améliorée.
PCT/DE2001/002070 2000-06-14 2001-06-01 Procede pour produire un masque plat sur des surfaces a reliefs WO2001096956A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000129288 DE10029288A1 (de) 2000-06-14 2000-06-14 Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen
DE10029288.7 2000-06-14

Publications (2)

Publication Number Publication Date
WO2001096956A2 true WO2001096956A2 (fr) 2001-12-20
WO2001096956A3 WO2001096956A3 (fr) 2002-04-11

Family

ID=7645695

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/002070 WO2001096956A2 (fr) 2000-06-14 2001-06-01 Procede pour produire un masque plat sur des surfaces a reliefs

Country Status (3)

Country Link
DE (1) DE10029288A1 (fr)
TW (1) TW492072B (fr)
WO (1) WO2001096956A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210313227A1 (en) * 2018-10-31 2021-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an interconnect structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2806410A1 (de) * 1977-02-15 1978-08-17 Westinghouse Electric Corp Halbleiteranordnung und verfahren zu deren herstellung
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
DE19629766C2 (de) * 1996-07-23 2002-06-27 Infineon Technologies Ag Herstellverfahren von Shallow-Trench-Isolationsbereiche in einem Substrat
US5858621A (en) * 1997-01-22 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-layer silylation process using anti-reflective-coatings (ARC) for making distortion-free submicrometer photoresist patterns
US6030541A (en) * 1998-06-19 2000-02-29 International Business Machines Corporation Process for defining a pattern using an anti-reflective coating and structure therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2806410A1 (de) * 1977-02-15 1978-08-17 Westinghouse Electric Corp Halbleiteranordnung und verfahren zu deren herstellung
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HORN M W: "ANTIREFLECTION LAYERS AND PLANARIZATION FOR MICROLITHOGRAPHY" SOLID STATE TECHNOLOGY, COWAN PUBL.CORP. WASHINGTON, US, Bd. 34, Nr. 11, 1. November 1991 (1991-11-01), Seiten 57-62, XP000240827 ISSN: 0038-111X *
SCHATTENBURG M L ET AL: "OPTICALLY MATCHED TRILEVEL RESIST PROCESS FOR NANOSTRUCTURE FABRICATION" JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, Bd. 13, Nr. 6, 1. November 1995 (1995-11-01), Seiten 3007-3011, XP000558373 ISSN: 0734-211X *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210313227A1 (en) * 2018-10-31 2021-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an interconnect structure
US11901226B2 (en) * 2018-10-31 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an interconnect structure

Also Published As

Publication number Publication date
TW492072B (en) 2002-06-21
WO2001096956A3 (fr) 2002-04-11
DE10029288A1 (de) 2002-01-03

Similar Documents

Publication Publication Date Title
DE19933480B4 (de) Verfahren zur Herstellung eines zylindrischen Kondensators
DE19638684C2 (de) Halbleitervorrichtung mit einem Kontaktloch
DE10021385B4 (de) Verfahren zur Herstellung eines Kondensators mit Erzeugung einer unteren Kondensatorelektrode unter Verwendung einer CMP-Stoppschicht
DE102015213529A1 (de) Vorrichtung mit einer Floating-Gate-Elektrode und einer Schicht aus ferroelektrischem Material und Verfahren zu ihrer Herstellung
DE10054109C2 (de) Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist
DE10360537B4 (de) Verfahren zum Ausbilden tiefer Isolationsgräben bei der Herstellung integrierter Schaltungen
DE19930295C2 (de) Säulenförmiger Speicherknoten eines Kondensators und Verfahren zur Herstellung desselben
DE19719699A1 (de) Verfahren zur Bildung eines dynamischen Speichers mit hoher Dichte und wahlfreiem Zugang
DE102005054431A1 (de) Verfahren zum Herstellen eines Flaschengrabens und eines Flaschengrabenkondensators
DE10347462A1 (de) Bodenelektrode eines Kondensators einer Halbleitervorrichtung und Verfahren zur Herstellung derselben
DE102006037751A1 (de) Verfahren zur Ausbildung eines dotierten Abschnitts und eines Transistors
DE102016119019B4 (de) Halbleiterbauelement und Herstellungsverfahren dafür
DE4233486B4 (de) Grabenkondensator-Speicherzelle und Verfahren zu deren Herstellung
DE102004020938B3 (de) Verfahren zum Herstellen einer ersten Kontaktlochebene in einem Speicherbaustein
DE10109564A1 (de) Grabenkondensator und Verfahren zu seiner Herstellung
DE102005022574A1 (de) Halbleiterspeicherbauelement mit Isolationsgrabenstruktur und zugehöriges Herstellungsverfahren
DE10120302B4 (de) Verfahren zur Herstellung eines Halbleiter-Bauteils
DE19852763B4 (de) Verfahren zur Herstellung eines Graben-Kondensators
DE19822048A1 (de) Verfahren zum Ätzen von Tantaloxidschichten
DE10029036C1 (de) Verfahren zur Erhöhung der Trenchkapazität
DE10233195A1 (de) Halbleitervorrichtung mit Grabenisolierung und Verfahren zu deren Herstellung
DE10020259A1 (de) Verfahren zur Herstellung floatender Gates in einem Halbleiterbauelement
WO2001096956A2 (fr) Procede pour produire un masque plat sur des surfaces a reliefs
WO2006066755A1 (fr) Procede de production de structures a tranchee profonde
DE10324055A1 (de) Integrierter Stapelkondensator und Verfahren zu dessen Herstellung

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

NENP Non-entry into the national phase

Ref country code: JP