DE10029288A1 - Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen - Google Patents

Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen

Info

Publication number
DE10029288A1
DE10029288A1 DE2000129288 DE10029288A DE10029288A1 DE 10029288 A1 DE10029288 A1 DE 10029288A1 DE 2000129288 DE2000129288 DE 2000129288 DE 10029288 A DE10029288 A DE 10029288A DE 10029288 A1 DE10029288 A1 DE 10029288A1
Authority
DE
Germany
Prior art keywords
layer
mask
planar
topology
reflection layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE2000129288
Other languages
German (de)
English (en)
Inventor
Maik Stegemann
Ines Uhlig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE2000129288 priority Critical patent/DE10029288A1/de
Priority to PCT/DE2001/002070 priority patent/WO2001096956A2/fr
Priority to TW90114273A priority patent/TW492072B/zh
Publication of DE10029288A1 publication Critical patent/DE10029288A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
DE2000129288 2000-06-14 2000-06-14 Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen Withdrawn DE10029288A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE2000129288 DE10029288A1 (de) 2000-06-14 2000-06-14 Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen
PCT/DE2001/002070 WO2001096956A2 (fr) 2000-06-14 2001-06-01 Procede pour produire un masque plat sur des surfaces a reliefs
TW90114273A TW492072B (en) 2000-06-14 2001-06-13 Method to produce a planar mask at a topology-containing surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2000129288 DE10029288A1 (de) 2000-06-14 2000-06-14 Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen

Publications (1)

Publication Number Publication Date
DE10029288A1 true DE10029288A1 (de) 2002-01-03

Family

ID=7645695

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2000129288 Withdrawn DE10029288A1 (de) 2000-06-14 2000-06-14 Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen

Country Status (3)

Country Link
DE (1) DE10029288A1 (fr)
TW (1) TW492072B (fr)
WO (1) WO2001096956A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069570B2 (en) * 2018-10-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an interconnect structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
DE19629766A1 (de) * 1996-07-23 1998-01-29 Siemens Ag Herstellverfahren von Shallow-Trench-Isolationen auf einem Substrat
US5858621A (en) * 1997-01-22 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-layer silylation process using anti-reflective-coatings (ARC) for making distortion-free submicrometer photoresist patterns
US6030541A (en) * 1998-06-19 2000-02-29 International Business Machines Corporation Process for defining a pattern using an anti-reflective coating and structure therefor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2380637A1 (fr) * 1977-02-15 1978-09-08 Westinghouse Electric Corp Procede de traitement de circuits integres cmos et circuits obtenus
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
DE19629766A1 (de) * 1996-07-23 1998-01-29 Siemens Ag Herstellverfahren von Shallow-Trench-Isolationen auf einem Substrat
US5858621A (en) * 1997-01-22 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-layer silylation process using anti-reflective-coatings (ARC) for making distortion-free submicrometer photoresist patterns
US6030541A (en) * 1998-06-19 2000-02-29 International Business Machines Corporation Process for defining a pattern using an anti-reflective coating and structure therefor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BASHIR, R. et.al.: PLATOPI A Novel Planarized Trench Isolation. In: IEEE Transaction on Elec- tron Devices, Vol. 17, No. 7, July 1996, pp.352-4 *
JP 54-14165 A. In: Patent Abstracts of Japan *

Also Published As

Publication number Publication date
WO2001096956A2 (fr) 2001-12-20
TW492072B (en) 2002-06-21
WO2001096956A3 (fr) 2002-04-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8139 Disposal/non-payment of the annual fee