WO2001096956A3 - Procede pour produire un masque plat sur des surfaces a reliefs - Google Patents

Procede pour produire un masque plat sur des surfaces a reliefs Download PDF

Info

Publication number
WO2001096956A3
WO2001096956A3 PCT/DE2001/002070 DE0102070W WO0196956A3 WO 2001096956 A3 WO2001096956 A3 WO 2001096956A3 DE 0102070 W DE0102070 W DE 0102070W WO 0196956 A3 WO0196956 A3 WO 0196956A3
Authority
WO
WIPO (PCT)
Prior art keywords
reliefs
producing
planar mask
processing window
antireflecting
Prior art date
Application number
PCT/DE2001/002070
Other languages
German (de)
English (en)
Other versions
WO2001096956A2 (fr
Inventor
Maik Stegemann
Ines Uhlig
Original Assignee
Infineon Technologies Ag
Maik Stegemann
Ines Uhlig
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Maik Stegemann, Ines Uhlig filed Critical Infineon Technologies Ag
Publication of WO2001096956A2 publication Critical patent/WO2001096956A2/fr
Publication of WO2001096956A3 publication Critical patent/WO2001096956A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

L'invention concerne un procédé pour produire un masque plat sur des surfaces à reliefs. Selon l'invention, des évidements (V) sont remplis d'un oxyde sélectif (1), puis une couche de masquage (2), de forme correspondante, et une couche antireflet (3) sont appliquées. Cette planéité améliorée permet d'obtenir une fenêtre de processus lithographique de taille plus importante. L'utilisation de couches antireflet organiques plus minces permet simultanément de réduire la consommation de résine photosensible pendant l'attaque et d'obtenir ainsi une fenêtre de processus d'attaque améliorée.
PCT/DE2001/002070 2000-06-14 2001-06-01 Procede pour produire un masque plat sur des surfaces a reliefs WO2001096956A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000129288 DE10029288A1 (de) 2000-06-14 2000-06-14 Verfahren zur Herstellung einer planaren Maske auf topologiehaltigen Oberflächen
DE10029288.7 2000-06-14

Publications (2)

Publication Number Publication Date
WO2001096956A2 WO2001096956A2 (fr) 2001-12-20
WO2001096956A3 true WO2001096956A3 (fr) 2002-04-11

Family

ID=7645695

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/002070 WO2001096956A2 (fr) 2000-06-14 2001-06-01 Procede pour produire un masque plat sur des surfaces a reliefs

Country Status (3)

Country Link
DE (1) DE10029288A1 (fr)
TW (1) TW492072B (fr)
WO (1) WO2001096956A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069570B2 (en) * 2018-10-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an interconnect structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2806410A1 (de) * 1977-02-15 1978-08-17 Westinghouse Electric Corp Halbleiteranordnung und verfahren zu deren herstellung
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
DE19629766C2 (de) * 1996-07-23 2002-06-27 Infineon Technologies Ag Herstellverfahren von Shallow-Trench-Isolationsbereiche in einem Substrat
US5858621A (en) * 1997-01-22 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-layer silylation process using anti-reflective-coatings (ARC) for making distortion-free submicrometer photoresist patterns
US6030541A (en) * 1998-06-19 2000-02-29 International Business Machines Corporation Process for defining a pattern using an anti-reflective coating and structure therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2806410A1 (de) * 1977-02-15 1978-08-17 Westinghouse Electric Corp Halbleiteranordnung und verfahren zu deren herstellung
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HORN M W: "ANTIREFLECTION LAYERS AND PLANARIZATION FOR MICROLITHOGRAPHY", SOLID STATE TECHNOLOGY, COWAN PUBL.CORP. WASHINGTON, US, vol. 34, no. 11, 1 November 1991 (1991-11-01), pages 57 - 62, XP000240827, ISSN: 0038-111X *
SCHATTENBURG M L ET AL: "OPTICALLY MATCHED TRILEVEL RESIST PROCESS FOR NANOSTRUCTURE FABRICATION", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 13, no. 6, 1 November 1995 (1995-11-01), pages 3007 - 3011, XP000558373, ISSN: 0734-211X *

Also Published As

Publication number Publication date
WO2001096956A2 (fr) 2001-12-20
DE10029288A1 (de) 2002-01-03
TW492072B (en) 2002-06-21

Similar Documents

Publication Publication Date Title
EP1248305A3 (fr) Procédé de fabrication de mémoire magnétique
MY114849A (en) Surface treatment process of metallic material and metallic obtained thereby
EP1580607A3 (fr) Solutions de traitement contenant des tensioactifs
WO2002080239A3 (fr) Procede permettant de former des elements de photoresine de dimensions sous-lithographiques
EP1432023A4 (fr) Dispositif a semiconducteur et son procede de production
EP1388902A3 (fr) Procédé de fabrication pour diode Gunn
WO2002061801A3 (fr) Procede de fabrication de grille double au moyen d'une couche moleculaire auto-assemblee
WO2004065934A3 (fr) Procede de production de semi-conducteurs destine a la production de petits dispositifs
WO2002029865A3 (fr) Procede de fabrication d'un composant a semi-conducteur et composant ainsi obtenu
TW350972B (en) Semiconductor and the manufacturing method
TW587279B (en) Method for forming bi-layer photoresist and application thereof
WO2004025714A3 (fr) Procede de fabrication d'une structure a semiconducteur
WO2001096956A3 (fr) Procede pour produire un masque plat sur des surfaces a reliefs
EP1223607A4 (fr) Substrat pour masque de transfert, masque de transfert et son procede de fabrication
WO2004003980A3 (fr) Structure d'interconnexion et procede de realisation
EP1011135A3 (fr) Structure d'interconneciton pour semiconducteur utilisant une couche diélectrique inorganique PECVD, et son procédé de fabrication
CA2355614A1 (fr) Procede combine de polissage chimico-mecanique/gravure permettant de realiser une mince couche plane sur la surface d'un dispositif
WO2002042846A3 (fr) Fabrication de circuit integre
JP2002319573A (ja) 半導体装置の製造方法
WO2003005411A3 (fr) Procede d'obtention d'une structure etagee sur un substrat
WO2003046961A3 (fr) Procede pour realiser une structure dans un substrat semi-conducteur
JP3551183B2 (ja) 半導体装置の製造方法
TW325583B (en) Method of etching a polysilicon layer
TW200504831A (en) Method for fabricating poly patterns
TW368732B (en) Manufacturing method for integrated circuit dual damascene

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

NENP Non-entry into the national phase

Ref country code: JP