WO2001096956A2

WO2001096956A2 - Method for producing a planar mask on surfaces having reliefs

Info

Publication number: WO2001096956A2
Application number: PCT/DE2001/002070
Authority: WO
Inventors: Maik Stegemann; Ines Uhlig
Original assignee: Infineon Technologies Ag
Priority date: 2000-06-14
Filing date: 2001-06-01
Publication date: 2001-12-20
Also published as: TW492072B; DE10029288A1; WO2001096956A3

Abstract

The invention relates to a method for producing a planar mask on surfaces having reliefs, whereby recesses (V) are filled with a selective oxide (1) and a mask layer (2) conforming to the shape thereof and an antireflecting layer (3) are subsequently formed. A larger lithography processing window is obtained due to this improved planarity. At the same time, the use of thinner organic antireflecting coated layers results in reducing the amount of lacquer used during etching thus providing an improved etching processing window.

Description

description

Process for the production of a planar mask on topology-containing surfaces

The present invention relates to a method for producing a planar mask on topology-containing surfaces and in particular to a method for producing a planar STI hard mask for realizing structures smaller than 170 nm in DRAM cells.

Due to the progressive integration in integrated semiconductor circuits, structure sizes below 170 n are now required. In particular for a photolithography of structures of this type below 170 nm, a planar surface of the wafers is absolutely necessary. In the case of so-called DRAM memory circuits in particular, a lithography process window, for example for the formation of the active regions with their deep trench capacitors and related products, approaches zero. Since due to the ever smaller structures of lithography, a required increase in resolution is accompanied by a decreasing depth of field, additional unevenness of the wafer or wafer surface intensifies this problem. For the firmly defined and clean formation of corresponding structures in a substrate, unevenness in the wafer disks must therefore be eliminated or thinner lacquer layers used.

FIG. 1 shows a simplified sectional view of a conventional photo resist soft mask for realizing, for example, shallow trench isolation (STI) in a DRAM cell. According to Figure 1, a grave Vielzahl- of ^capacitors' 20 are formed in a semiconductor substrate 10 having at an upper region an insulating collar or collar 21 aufwei- sen and in a lower region, a dielectric 22, which acts as the capacitor dielectric. Trench capacitors have, for example, a polysilicon filling 23 in their interior, which acts as an electrode of the trench capacitor 20. A counter electrode, not shown, is located in the lower region of the trench capacitor 20 in the semiconductor substrate 10, as a result of which a capacitor with sufficient charge holding capacity is created.

To isolate the adjacent trench capacitors shown in FIG. 1 and at the same time the transistors formed later, shallow trench isolation (STI) is required, in which the semiconductor substrate 10 or the polysilicon filler material 23 is preferably up to the insulation collar 21 removed and filled with insulating material. When the trench capacitors 20 are formed beforehand, however, a surface with a high topology arises, which is caused in particular by the lack of layer regions of the pad layer 11 above the trench capacitors 20. The pad layer 11 preferably consists of Si ₃ N ₄ . To level this topology-containing surface, an organic antireflection layer 3 'is applied to the surface in the conventional photo-resist soft mask according to FIG. 1, which results in an improved (planar) surface. Subsequently, a photo resist 4 is spun on, exposed using conventional photolithographic processes and developed, whereby the mask shown in FIG. 1 is obtained. A disadvantage of such a conventional method for producing a However, a planar mask is the insufficient planarity of the organic anti-reflection layer 3 ', which requires a relatively thick photoresist layer 4. The lithography process window is thereby reduced, which makes subsequent subsequent formation of firmly defined, shallow trench insulation (STI) difficult. Further, this method has the disadvantage that at a later ITM-etching the organic antireflection layer 3 ^λ and the pad layer 11 is a high paint consumption occurs. If the paint mask or the photo resist 4 is too thin, this can lead to the etching of active areas on the side walls in the semiconductor substrate 10, as a result of which the yield is significantly reduced.

Figures 2 and 3 show simplified sectional views of a conventional BSG hard mask with an organic and an inorganic anti-reflection layer. The same reference numerals here again designate the same or similar layers, which is why a repeated description is omitted below.

According to FIGS. 2 and 3, the topology-containing surfaces of the semiconductor substrate 10 with its trench capacitors 20 are compensated for using so-called hard masks. Here, a hard mask layer 5 made of, for example, borosilicate glass (BSG) is formed on the pad layer 11 or the intervening depressions, which results in an almost planar surface. According to FIG. 2, this almost planar surface can be further leveled by depositing an organic antireflection layer 3 'or can only be coated with an inorganic antireflection layer 3 according to FIG. 3. Finally, a photoresist or photo is again applied to the organic antireflection layer 3 'or the inorganic antireflection layer 3. Resist 4 spun on, exposed and developed, whereby the mask shown in FIG. 2 or FIG. 3 is obtained. ^'The disadvantage, however, with such a BSG hard mask that existing topologies the surface but are still present, although in a weakened form. Since the anti-reflection layer 3 or 3 'is also absolutely necessary for the lithography in this case for optical reasons (avoidance of disturbing reflections), however, there are again the disadvantages of etching process windows that are much too narrow. In particular when using the organic anti-reflection layer 3 ^x according to FIG. 2, the advantage of a relaxed paint budget is in turn negated by the disadvantage of the organic anti-reflection layer. In particular with structure sizes below 170 nm, such conventional planar masks only provide insufficiently sharp or exact coverage of the areas to be etched.

The invention is therefore based on the object of creating a method for producing a planar mask on topology-containing surfaces which enables greater accuracy and thus greater yield with very small structure sizes.

This object is achieved by the measures of claim 1.

In particular, by selectively filling depressions in the topology-containing surface and then forming a conformal mask layer and an anti-reflection layer, a completely planar mask is obtained which can be made as thick as desired, as a result of which both a larger lithography process and a larger etching process are Window received. Preferably, a selective oxidation method for depositing silicon dioxide is used only for filling up the depressions within the depressions. In this way, a particularly simple and inexpensive manufacturing process is obtained using a pad layer.

An inorganic and / or organic antireflection layer is preferably used as the antireflection layer, as a result of which a homogeneous thickness is obtained both over a strongly topology-containing cell field and in an edge region with larger structures.

Further advantageous refinements of the invention are characterized in the subclaims.

The invention is described below using an exemplary embodiment with reference to the drawing.

Show it:

Figure 1 is a simplified sectional view of a conventional photo resist soft mask;

FIG. 2 shows a simplified sectional view of a conventional BSG hard mask with an organic anti-reflection layer;

FIG. 3 shows a simplified sectional view of a conventional BSG hard mask with an inorganic anti-reflection layer; FIGS. 4A to 4 F show simplified sectional views to illustrate the respective method steps for producing a planar mask according to the present invention; and

FIGS. 5A to 5C simplified sectional views to illustrate the method steps for producing a flat trench isolation in DRAM cells with the mask produced in FIGS. 4A to 4F.

FIGS. A to 4F show simplified sectional views to illustrate respective method steps for producing a planar mask according to the present invention, the same reference symbols denoting the same or similar elements or layers as in FIGS. 1 to 3 and to avoid repetition of a detailed description is subsequently waived.

The method for producing a planar mask according to the invention on topology-containing surfaces is again described in accordance with FIGS. 4A to 4F using a DRAM memory circuit as an example. However, the invention is not restricted to this and rather encompasses all other manufacturing methods for realizing a planar mask on topology-containing surfaces, such as e.g. in bipolar circuits, embedded circuits etc.

According to FIG. 4A, a multiplicity of trench capacitors 20 are located in a semiconductor substrate 10, which are formed as deep trenches in the semiconductor substrate 10. To prevent leakage currents or for insulation, these have Benkondensatoren 20 in their upper region insulation collars

21 or collars. The trench capacitors 20 are here filled with a conductive filler 23, which consists, for example, of doped polysilicon and serves as an electrode for the trench capacitor 20. A dielectric layer 22, which essentially represents a storage dielectric, is located on the walls of the trench capacitors 20 for isolation from the semiconductor substrate 10. A further electrode, not shown, is located in a lower region of the trench capacitor 20 within the semiconductor substrate 10, as a result of which a counter electrode to the filling material 23 is realized. When these trench capacitors 20 are formed, depressions V are formed on the surface, which are formed, for example, in a pad layer 11 and the semiconductor substrate 10. The pad layer 11 preferably consists of Si ₃ N ₄ .

According to FIG. 4B, a selective filling of the depressions V in the topology-containing surface of the semiconductor substrate 10 or of the wafer is now carried out in a first method step. This selective filling of the depressions V is preferably implemented by a selective oxidation method, as is known for example from the publication WO98 / 03992. In this so-called SELOX process, an oxide 1 (for example SiO ₂ ) is deposited selectively to the pad layer 11 only in the depressions V until the height of the pad layer 11 is reached. In this way, an almost complete planar surface is obtained.

According to FIG. 4C, a conformal mask layer 2 is deposited over the entire area on the surface of the semiconductor substrate 10 or of the wafer in a subsequent step. For this mask layer 2, one preferably uses a silicon _O xid existing hard mask layer. Then at the

_O berfläche the hard mask layer 2, an antireflective layer

3 trained all over. The antireflection layer 3 can either consist of an inorganic antireflection layer such as Si _x O _y N ₍ i- _x - _y ) or an organic one

Lacquer layer such as DUV30.

In contrast to the prior art according to FIGS. 1 and 2, when an organic antireflection layer 3 is used, its layer thickness is the same in all areas of the wafer, since it is not misused to level out unevenness. The antireflection layer 3 thus serves, in particular, to reduce or completely eliminate disturbing reflections during a subsequent exposure of a photo lacquer or photo resist.

According to FIG. 4D, this photoresist or photo resist 4 is formed, exposed and developed over the entire surface in a subsequent step and with a layer thickness that is relatively small compared to the prior art according to FIGS. 1 to 3, thereby realizing a photomask. Due to the very small layer thicknesses for the photomask 4 for the first time, a sufficiently sharp mask is obtained, which is why structure sizes below 170 nm can also be realized reliably and with a high yield.

In the method step according to FIG. 4E, a so-called HM etching is carried out, in which both the antireflection layer 3 and the mask layer 2 up to the SELOX oxide 1 and the pad layer 11 are removed using the photoresist or photo resist 4. According to FIG. 4F, the photo resist 4 and the antireflection layer 3 are completely removed in a subsequent process step (resist strip) and a so-called ITM etching is carried out into the semiconductor substrate 10. Here, both the SELOX oxide 1 and the exposed pad layer 11 are completely removed and the semiconductor substrate 10 or the polysilicon filling material 23 of the trench capacitors 20 is slightly etched.

According to the manufacturing process described above, complete planarization is thus obtained through the SELOX oxide 1 and the conforming hard mask 2, which results in a thin planar organic ARC layer, which in this case only has to have the function of an anti-reflection layer. Due to this improved planarity, a larger lithography process window is achieved. At the same time, the use of thinner organic ARC layers enables less paint consumption during the etching and thus an improved etching process window. In this way, thinner photo lacquer thicknesses can be made possible, which in turn allows structure widths below 170 nm to be realized with great precision and high yield.

Alternatively, the photo resist 4 can be eliminated in the method described above and the method steps according to FIGS. 4E and 4F can be carried out in a common etching step.

FIGS. 5A to 5C show simplified sectional views for illustrating method steps for producing a shallow trench isolation in DRAM cells. The same reference numerals again designate the same elements or Layers as in Figures 1 to 4, which is why a repeated description is omitted below.

According to FIG. 5A, using the planar mask produced in FIGS. 4A to 4F, so-called IT etching is used to form a shallow trench isolation (STI) in the semiconductor substrate 10 in such a way that a depression is formed up to the insulation collars 21 of the trench capacitors 20 , This etching step shown in FIG. 5A can preferably also be combined with the etching steps shown in FIGS. 4E and 4F, which results in a further simplification of the process. Alternatively, however, only the etching steps shown in Figure 4F and 5A, in a common etching step carried ^■ are leads.

According to FIG. 5B, the SELOX oxide 1 and the remaining hard mask layer 2 are completely removed and an HDP-Si0 ₂ layer 6 (high density plasma) is deposited on the surface or in the depression. In this way, the adjacent trench capacitors 20 are isolated from one another, only an open region of the trench capacitor 20 serving as charge supply and discharge to a field effect transistor, not shown. However, the SELOX oxide 1 and the hard mask layer 2 can optionally remain on the surface.

In a method step according to FIG. 5C, the surface of the wafer is then planarized, preferably using chemical mechanical polishing (CMP). In this way, in particular when producing DRAM cells, the required process steps can be simplified and particularly small structure sizes can be realized.

The invention has been described above using a planar mask for shallow trench isolation in DRAM cells. However, it is not restricted to this and rather encompasses all further methods for producing a planar mask on topology-containing surfaces, as can occur, for example, in bipolar circuits and / or embedded circuits.

Claims

claims

1. A method for producing a planar mask on topology-containing surfaces with the steps: a) selective filling of depressions (V) in the topology-containing surface; b) forming a conformal mask layer (2) on the filled surface; c) forming an anti-reflection layer (3) on the mask layer (2); d) forming a photomask (4) on the anti-reflection layer (3); e) removing part of the anti-reflection layer (3) and the mask layer (2) using the photomask (4); and f) removing the photomask (4) and the anti-reflection layer (3).

2. The method according to claim 1, so that a selective oxidation method is used in step a) to fill up the depressions (V).

3. The method according to claim 1 or 2, so that a compliant hard mask layer (2) is formed from silicon oxide in step d).

4. The method according to any one of claims 1 to 3, so that an organic and / or inorganic antireflection layer (3, 3) is formed in step c).

5. The method according to claim 4, characterized in that the inorganic anti-reflection layer (3) has Si _x O _y N ₍ ι. _x . _y) .

6. The method according to any one of claims 1 to 5, so that the planar mask is an STI mask for shallow trench isolation (6) in DRAM cells.