WO2001071806A1 - Dispositif a semi-conducteur, procede de realisation d'un dispositif electronique, dispositif electronique, et terminal d'informations portable - Google Patents

Dispositif a semi-conducteur, procede de realisation d'un dispositif electronique, dispositif electronique, et terminal d'informations portable Download PDF

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Publication number
WO2001071806A1
WO2001071806A1 PCT/JP2001/002171 JP0102171W WO0171806A1 WO 2001071806 A1 WO2001071806 A1 WO 2001071806A1 JP 0102171 W JP0102171 W JP 0102171W WO 0171806 A1 WO0171806 A1 WO 0171806A1
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WO
WIPO (PCT)
Prior art keywords
wiring board
mounting
thickness
semiconductor chip
board
Prior art date
Application number
PCT/JP2001/002171
Other languages
English (en)
French (fr)
Inventor
Tsuneo Hamaguchi
Kenji Kagata
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Priority to JP2001569887A priority Critical patent/JP3967133B2/ja
Priority to EP01912489A priority patent/EP1189282A4/en
Priority to US09/979,188 priority patent/US6633078B2/en
Publication of WO2001071806A1 publication Critical patent/WO2001071806A1/ja
Priority to US10/614,525 priority patent/US6905911B2/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/1901—Structure
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    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09018—Rigid curved substrate
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/306—Lifting the component during or after mounting; Increasing the gap between component and PCB
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor device on which a semiconductor chip is mounted with high density, a method for manufacturing an electronic device such as a portable information terminal to which the semiconductor device is mounted, an electronic device, and a portable information terminal.
  • a board for mounting connection is provided between the wiring board and the mounting board, and the wiring board is connected to the mounting board via the connection board. It can be mounted without touching the board.
  • FIG. 11 is a cross-sectional view of a conventional electronic device mounted by such a method, for example, a cross-sectional view of a conventional electronic device disclosed in Japanese Patent Application Laid-Open No. 7-240496. It is.
  • a semiconductor device is mounted on a mounting board 108 to constitute an electronic device.
  • the semiconductor device has a structure in which semiconductor chips 101a and 101 are mounted on the front and back surfaces of one wiring board 103, respectively.
  • the wiring board 103 is the connection board 1 It is joined and electrically connected to the mounting board 108 via the wiring 106.
  • the electrical connection between the electrode 104 of the wiring board 103 and the electrode 116 of the connection board 106, and the electrode 116 of the connection board 106 and the mounting board 108 The electrical connection with the electrodes 109 is realized by the solder bumps 107.
  • the thickness of the semiconductor chip 101 b is set to be smaller than the total thickness of the connection board 106 and the solder bump 107 so as not to hinder the connection to the mounting board. I have.
  • the wiring board 103 and the first and second semiconductor chips 101 a and 101 b are electrically connected to each other by electrodes 102.
  • the connection between the wiring board 103 and the first and second semiconductor chips 101 a and 101 b, and the connection between the wiring board 103 and the connection substrate 106 are made of a sealing resin. Sealed by 105.
  • a recess is provided on the back surface of the wiring board, and the semiconductor chip is mounted so as to fit into the recess.
  • the semiconductor chip on the back surface is mounted without touching the mounting board. You can do it.
  • FIG. 12 is a cross-sectional view of a conventional electronic device implemented by such a method.
  • a concave portion is provided on the back surface of the wiring board, and the semiconductor chip 101b is mounted so as to fit into the concave portion.
  • the wiring board 103 and the first and second semiconductor chips 101 a and 101 b are electrically connected to each other by the electrode 102. Further, a connection portion between the wiring board 103 and the first and second semiconductor chips 101 a and 101 b is sealed with a sealing resin 105.
  • the wiring board can be mounted on the mounting board so that the semiconductor chip on the back surface does not contact the mounting board.
  • the first method requires the use of expensive connection boards, which increases the manufacturing cost of electronic devices.
  • the wiring board and the mounting board are joined via the connecting board, there is a problem that the connecting board is sandwiched between the wiring board and the mounting board, and it is difficult to reduce the thickness.
  • the thickness of the semiconductor chip 101 b should be as small as possible. It is conceivable to make it smaller. However, in this case, there has been a problem that the rigidity is reduced due to the reduced thickness of the semiconductor chip 101b and the reliability is reduced.
  • a wiring board for forming fine wiring usually has a larger coefficient of linear expansion than a mounting board due to its material composition, and the wiring board and the mounting board have different linear expansion coefficients.
  • the heat shrinkage of the wiring board when returned to room temperature is larger than that of the mounting board, as shown in Fig. 13.
  • the wiring board 103 warps in a convex shape toward the mounting board 108 side. Accordingly, the semiconductor chip 101 b mounted on the rear surface of the wiring board 103 also warps in a convex shape toward the mounting board, so that the semiconductor chip 101 b contacts the mounting board 108. There was a problem of damage.
  • the gap between the semiconductor chip 101b and the mounting board 103 is small, even if the semiconductor chip 101b does not contact the mounting board 108 during mounting, the mounting When bending or torsional stress occurs in the semiconductor chip 108, the surface of the semiconductor chip 101b comes into contact with the mounting substrate 108, and the semiconductor chip 101b is damaged. Disclosure of the invention
  • the present invention has been made to solve the above-mentioned conventional problems, and is intended to manufacture low-cost semiconductor devices and electronic devices in which semiconductor chips are arranged on both sides of a wiring board without deteriorating electrical characteristics. It aims to provide a method, an electronic device and a personal digital assistant.
  • a semiconductor device includes a wiring substrate having electrodes on the front surface and the back surface; a protruding electrode provided on one surface of the wiring substrate so as to have a predetermined height; A semiconductor chip provided on the one surface of the wiring substrate so as to be connected and having a thickness smaller than the height of the protruding electrode; and the one surface side of the wiring substrate being warped concavely and An electronic component is provided on the other surface of the wiring board so as to be electrically connected to an electrode of the wiring board and has a thickness larger than the thickness of the semiconductor chip.
  • the wiring board is warped toward the side on which the protruding electrode (bump) is provided (a recess is formed on the side on which the protruding electrode is provided), and the wiring board on which the semiconductor chip is mounted is mounted.
  • the semiconductor chip does not come into contact with the mounting substrate and can be mounted without damaging the semiconductor chip.
  • a connection substrate is not used or a recess is not formed in a wiring substrate, a semiconductor device can be manufactured at low cost.
  • the magnitude and direction of the warpage are mostly determined by the electronic component and the wiring board. What is necessary is just to make it smaller than the linear expansion coefficient. Further, it is preferable that the value of the coefficient of linear expansion of the electronic component be equal to or less than the value of the coefficient of linear expansion of the semiconductor chip.
  • the difference between the height and the peripheral part be 100 / m or less. Also, since it is necessary to generate warpage, it is more preferable that the height difference between the central part and the peripheral part of the wiring board be 5/111 to 100111. It is good to be 10 ⁇ m ⁇ 40 / m.
  • the electronic component may be a single semiconductor chip, or may be a laminate of a plurality of semiconductor chips.
  • the thickness of the electronic component is preferably at least 0.3 mm in order to surely increase the rigidity and suppress the deterioration of the electrical characteristics.
  • the thickness of the electronic part is unnecessarily increased, the thickness of the semiconductor device is increased, which is contrary to the reduction in thickness. Therefore, the thickness is preferably about 0.65 mm or less.
  • the electronic component may be larger than the semiconductor chip in a planar size.
  • the wiring substrate for example, it is preferable to use a printed substrate, a substrate having a fine wiring layer formed by plating an epoxy resin on the surface of the printed substrate, or a resin substrate made of polyimide resin and a conductor.
  • another semiconductor device includes a wiring substrate having electrodes on front and rear surfaces, a protruding electrode provided on one surface of the wiring substrate so as to have a predetermined height, and A semiconductor chip provided on the one surface of the wiring board and having a thickness smaller than the height of the protruding electrode so as to be electrically connected to the electrode of the wiring board; and electrically connected to the electrode of the wiring board.
  • An electronic part provided on the other surface of the wiring board, the thickness of which is larger than the thickness of the semiconductor chip, and whose linear expansion coefficient is smaller than the linear expansion coefficient of the wiring board; Goods.
  • the wiring board is warped to the side on which the protruding electrodes are provided, and the semiconductor chip is mounted on the mounting board.
  • the semiconductor chip does not come into contact with the mounting board and can be mounted without damaging the semiconductor chip.
  • a connection substrate is not used or a concave portion is not formed in a wiring substrate, a semiconductor device can be manufactured at low cost.
  • the thickness of the electronic component is 0.3 mm or more.
  • a semiconductor device in which a protruding electrode and a semiconductor chip are provided on a mounting side and an electronic component is provided on a side opposite to the mounting side is provided via the protruding electrode.
  • a method of manufacturing an electronic device wherein the semiconductor chip is mounted on a mounting board to manufacture the electronic device, wherein the thickness of the semiconductor chip is smaller than the height of the projecting electrode, and the thickness of the electronic component is larger than the thickness of the semiconductor chip.
  • the semiconductor device whose mounting side is warped concave is aligned with the mounting board, and the semiconductor device is pressed against the mounting board in a state where the semiconductor device is warped, and the semiconductor device is pressed through the projecting electrode.
  • the device is mounted on the mounting board.
  • the mounting board is bent in a state where the mounting board side of the wiring board is concave. Since the semiconductor chip is mounted on the mounting substrate, the semiconductor chip is mounted without contacting the mounting substrate, and the semiconductor chip can be prevented from being damaged by contacting the mounting substrate.
  • the wiring board is warped to the side on which the protruding electrodes are provided. What is necessary is just to make the linear expansion coefficient smaller than the linear expansion coefficient of the wiring board.
  • the coefficient of linear expansion of the wiring board is larger than the coefficient of linear expansion of the electronic component, the amount of shrinkage during cooling is larger for the wiring board than for the electronic component.
  • the wiring board shrinks more greatly than the electronic component, and the wiring board is accompanied by a bowl-shaped warping in which the electronic component side is convex.
  • the value of the linear expansion coefficient of the electronic component be equal to or less than the value of the linear expansion coefficient of the semiconductor chip.
  • the semiconductor device includes a step of bonding the electronic component to the wiring board while heating and then cooling, and mounting the electronic component on the wiring board so that the side on which the wiring board is mounted is warped concavely. It may be manufactured by a manufacturing process including a step of mounting a semiconductor chip on the side where the wiring board is mounted and a step of forming a protruding electrode on the side where the wiring board is mounted.
  • an electronic device includes: a mounting board; a wiring board having electrodes on front and back surfaces mounted on the mounting board via protruding electrodes having a predetermined height; A semiconductor provided on a surface of the wiring board on the mounting board side so as to be arranged in a space between the wiring board and electrically connected to an electrode of the wiring board, and having a thickness smaller than a height of the protruding electrode; A chip, provided on a surface of the wiring board opposite to the mounting board so as to be electrically connected to the electrodes of the wiring board, the thickness of the wiring board being larger than the thickness of the semiconductor chip, and a coefficient of linear expansion of the wiring board; It has electronic components smaller than the coefficient of linear expansion.
  • a portable information terminal includes a housing, a mounting board arranged in the housing, a logic LSI chip arranged on the mounting board, and a projection having a predetermined height on the mounting board.
  • a wiring board having electrodes on the front surface and the back surface attached via the electrodes, and so as to be arranged in a space between the mounting board and the wiring board and to be electrically connected to the electrodes of the wiring board. Is provided on the surface of the wiring board on the mounting board side and the thickness is A memory or logic LSI chip smaller than the pole height, and a thickness greater than the thickness of the semiconductor chip provided on the surface of the wiring board opposite to the mounting board side so as to be electrically connected to the electrodes of the wiring board.
  • a semiconductor chip such as a memory or a logic LSI chip can be arranged at a predetermined distance without contact with a mounting board, and is mounted without damaging the semiconductor chip. It is possible to provide electronic devices and portable information terminals which are excellent in use.
  • the electronic component has a thickness of 0.3 mm or more.
  • FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a sectional view showing a schematic configuration of a semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 3 is a sectional view showing a schematic configuration of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 4 is a sectional view showing a schematic configuration of the semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 5 is a plan view showing a schematic configuration of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 6 is a process chart showing a method of manufacturing the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a sectional view showing a schematic configuration of a semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 7 is a process diagram showing a method for manufacturing an electronic device according to Embodiment 7 of the present invention.
  • FIG. 8 is a perspective view showing a schematic configuration of a portable information terminal according to Embodiment 8 of the present invention.
  • FIG. 9 shows a portable device according to the eighth embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of an information terminal.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of a portable information terminal according to Embodiment 9 of the present invention.
  • FIG. 11 is a cross-sectional view of a conventional semiconductor device. Show the schematic configuration FIG. 12 is a cross-sectional view, FIG. 12 is a cross-sectional view showing a schematic configuration of a conventional semiconductor device, and
  • FIG. 13 is a cross-sectional view showing a schematic configuration of a conventional semiconductor device.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention, in which warpage is emphasized more than it actually is.
  • the first semiconductor chip la (electronic component) and the second semiconductor chip lb are disposed on the front and back surfaces of the wiring board 3, respectively, and are provided on the respective surfaces.
  • the connection electrode 2 and the electrode 4 of the wiring board 3 are electrically connected.
  • the connection portions of these electrodes are covered and protected by the sealing resin 5.
  • solder bumps 7, which are connection protruding electrodes for electrically connecting to electrodes of a mounting board (not shown), are formed on the back surface of the wiring board 3.
  • the thickness of the second semiconductor chip 1b is smaller than the height of the solder bump 7, so that the second semiconductor chip 1b can be mounted on the back surface of the wiring board 3, that is, between the mounting board and the wiring board. It has become.
  • the thickness of the first semiconductor chip 1a is made larger than the thickness of the second semiconductor chip 1b so that the rigidity of the semiconductor device 10 can be ensured.
  • the wiring board 3 is configured so that the second semiconductor chip 1b does not come into contact with the mounting board so as to be concavely warped on the back surface side on which the second semiconductor chip 1b is mounted.
  • a first semiconductor chip 1 a having a thickness of about 0.4 mm and a second semiconductor chip 1 b having a thickness of about 0.15 mm are connected to a wiring board 3 having a thickness of about 0.4 mm, Also, keep the solder bump 7 at a height (thickness) of about 0.3 mm or less.
  • the semiconductor device 10 which is a composite of these causes a warpage of about 10 m without causing a slight undulation. The warpage does not cause deterioration of the electrical characteristics.
  • the warpage can be controlled by changing the thickness of the first semiconductor chip 1a and the second semiconductor chip 1b.
  • the thickness of the second semiconductor chip 1b is preferably about 66% or less of the thickness of the first semiconductor chip 1a, and is preferably about 50 / m or more from the viewpoint of securing rigidity.
  • the warpage of the wiring board 3 becomes a bowl-like warp of the same length and width, and when the dimensions are not the same, the degree of the warp differs between the vertical and horizontal directions. It becomes warped. If the warpage is too large, the bumps 7 provided on the mounting substrate cannot absorb light, and the electrical characteristics of the first semiconductor chip 1 a or the second semiconductor chip 1 b deteriorate, so that the wiring
  • the warpage of the substrate 3 is preferably such that the difference in height between the central portion and the peripheral portion of the wiring substrate 3 is 100 zm or less. In addition, since it is necessary to generate warpage, it is more preferable that the height difference between the central part and the peripheral part of the wiring board 3 is about 5100 ⁇ m. ⁇ ⁇ ⁇ ! ⁇ 40 m is good.
  • the thickness of the first semiconductor chip 1a is desirably 0.3 mm or more in order to surely increase rigidity and suppress deterioration of electrical characteristics. On the other hand, if the thickness of the electronic portion is unnecessarily increased, the thickness of the semiconductor device 10 becomes large, which is contrary to the reduction in the thickness of the semiconductor device.
  • the first semiconductor chip 1a has a linear expansion coefficient of about 3.5 10 -6 (1 / ° C), a silicon chip having a thickness of 0.3 mm or more, and a wiring board 3 having a linear expansion coefficient of 1 mm. 6 X 1 0- 6 (1 / ° C) or so, and a thickness of 0. 6 mm about print wiring board. Since the resin to protect the connection portion of the electrode was used as the linear expansion coefficient is as large as 5 0 X 1 0- 6 (1 / ° C) degree, is as small as 03 mm extent 0. thickness, warpage Does not significantly affect size or direction.
  • the magnitude and direction of the warpage can be determined by the first semiconductor chip 1a and the wiring board 3, and the wiring board 3 having a large amount of shrinkage upon cooling is smaller than the first semiconductor chip 1a. As a result, concave warpage can be formed on the second semiconductor chip 1b side.
  • the height difference h between the central part and the peripheral part of the wiring board 3 in FIG. 1 was about 10 ⁇ m.
  • the height difference h is desirably 100 / ⁇ 1 or less in order to secure the connection between the solder bumps 7 and the electrodes of the wiring board 3.
  • the thickness of the first semiconductor chip 1a is calculated.
  • the height is less than 0.3 mm, the stiffness is greatly reduced and the warpage increases sharply. Therefore, it is preferable to set the thickness of the first semiconductor chip la to 0.3 mm or more so as not to reduce the rigidity of the semiconductor device 1 as a composite.
  • a first semiconductor chip 1a is a silicon chip having a linear expansion coefficient of about 3.5 ⁇ 10 16 (1 / ° C), a thickness of about 0.15 mm, and a second semiconductor chip.
  • linear expansion coefficient 1 b 5. 7 1 0- 6 ( 1 / ° C) of about the thickness 0. 1 5 mm approximately gallium arsenide (GaAs) chip, a wiring board 3 linear expansion coefficient 1 6 X 1 0-
  • the printed circuit board was about 6 (1 / ° C) and about 0.6 mm thick.
  • the magnitude and direction of the warpage can be determined by the first semiconductor chip 1a and the second semiconductor chip 1b, and the second semiconductor chip 1b having a large amount of shrinkage upon cooling is the second semiconductor chip 1b.
  • the wiring board 3 can be warped concavely toward the second semiconductor chip 1b by shrinking more than the first semiconductor chip 1a.
  • FIG. 2 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a fourth embodiment of the present invention, in which warpage is emphasized more than it actually is.
  • the first semiconductor chip la (electronic component) and the second semiconductor chip lb are disposed on the front and back surfaces of the wiring board 3, respectively, and are provided on the respective surfaces.
  • the connection electrode 2 and the electrode 4 of the wiring board 3 are electrically connected.
  • the connection portions of these electrodes are covered and protected by the sealing resin 5.
  • solder bumps 7, which are connection protruding electrodes for electrically connecting to electrodes of a mounting board (not shown) are formed on the back surface of the wiring board 3.
  • the first semiconductor chip 1a and the second semiconductor chip 1b are different in planar size. Moreover, since the larger one is connected as the first semiconductor chip 1a, the wiring board 3 can be deflected similarly to the first embodiment, the rigidity is improved, and the suppression of minute buckling is further improved. It can be more reliable.
  • FIG. 3 shows a schematic configuration of a semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 4 is a sectional view showing a schematic configuration of another semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 5 is a schematic plan view of the semiconductor device shown in FIG.
  • the electronic component 1a is composed of two semiconductor chips, and the total thickness of these two chips is equal to that of the second semiconductor chip 1b mounted on the opposite surface of the wiring board 3. It is configured to be thicker than the thickness. Further, on the back surface of the wiring board 3, solder bumps 7, which are connection protruding electrodes for electrically connecting to electrodes of a mounting board (not shown), are formed.
  • the thickness of the second semiconductor chip 1b is smaller than the height of the solder bump 7, so that the second semiconductor chip 1b can be mounted on the back surface of the wiring board, that is, between the mounting board and the wiring board. ing.
  • the thickness of the electronic component 1a is made larger than the thickness of the second semiconductor chip 1b so that the rigidity of the semiconductor device can be secured.
  • the wiring board 3 is configured so that the second semiconductor chip 1b does not come into contact with the mounting board so that the wiring board 3 is concavely warped on the back surface side on which the second semiconductor chip 1b is mounted.
  • the thickness of the electronic component la composed of two semiconductor chips is preferably 0.3 mm or more.
  • the thickness of the second semiconductor chip 1b is preferably about 66% or less of the thickness of the electronic component 1a.
  • the mounting method of the two chips is not particularly limited.For example, two semiconductor chips are bonded with an adhesive, and the electrodes of the upper semiconductor chip and the electrodes of the wiring board 3 are connected by wires. I just need.
  • FIG. 6 is a process chart showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.
  • the connection electrode 2 of the electronic component 1a is aligned with the electrode 4 of the wiring board 3, and the connection is made by, for example, a flip chip bonding method.
  • the gap between the electronic component 1 a and the wiring board 3 is filled with a sealing resin 5 to enhance connection reliability.
  • the coefficient of linear expansion is about 15 to 40 X 1 (T B (1 / ° C)), and it is composed of a semiconductor such as silicon gallium arsenide.
  • connection electrode 2 of the second semiconductor chip 1b was aligned with the electrode 4 on the other surface of the wiring board 3, and heated and cooled in the same manner and connected. Thereafter, the gap between the second semiconductor chip 1 b and the wiring board 3 is filled with the sealing resin 5 to improve connection reliability.
  • the second semiconductor chip 1b is thinner than the electronic component 1a and the force for bending the wiring board 3 is small, the wiring board 3 remains warped to the electronic component 1a side.
  • the warpage is about 10 / m.
  • projecting electrodes 7 are formed around the wiring board 3.
  • a solder ball 7 is arranged on the electrode 4 of the wiring board 3 and heated to melt the solder.
  • a bump electrode can also be formed by printing cream solder on the electrode 4 of the wiring board 3 and heating it.
  • the solder ball spacing 0.5 mm the diameter
  • a solder ball of about 0.3 mm may be used.
  • the height of the protruding electrode 7 is about 0.23 mm. Therefore, when mounting the protruding electrodes 7 on a mounting board (not shown), the second semiconductor chip 1 b has a thickness of 0.15 mm and the second semiconductor chip 1 b is connected to the wiring board 3.
  • the gap between the second semiconductor chip 1b and the mounting board can be secured at about 30 / m.
  • the second semiconductor chip 1b does not contact the mounting substrate even if the semiconductor device 10 is pressed against the mounting substrate by external pressure or the like.
  • the semiconductor device 10 can be manufactured with the wiring board 3 warped.
  • an example of flip-chip bonding is shown as a method for mounting the electronic component 1a on the wiring board 3.
  • the anisotropic conductive adhesive film (the conductive particles are formed on an epoxy resin film) is used.
  • a heated semiconductor chip was pressed against the film.
  • the anisotropic conductive adhesive film is made of, for example, a thermosetting epoxy adhesive, the resin is cured while the electronic component 1a is pressed against the wiring board 3 while being heated.
  • solder flip chip bonding using solder
  • An alloy such as lead tin or silver tin is used for the solder, and can be formed by, for example, vapor deposition, printing of a solder base, or ball bonder. Gold or copper may be used instead of solder.
  • the connection can be performed with a conductive adhesive or conductive particles interposed between the connection electrode 2 and the electrode 4 of the wiring board 3. Further, the connection may be made by interposing a solder between the connection electrode 2 and the electrode 4 of the wiring board 3. Also, instead of flip chip bonding, wire bonding May be used.
  • the wiring board 3 is made of a resin material such as a printed board or polyimide resin.
  • a resin material such as a printed board or polyimide resin.
  • FIG. 7 is a process chart showing a method of manufacturing an electronic device according to Embodiment 7 of the present invention.
  • a conductive material 16 for connection is arranged on an electrode 9 of a mounting board 8.
  • the conductive material 16 for connection is, for example, in the form of a cream in which fine solder particles are dissolved in a solvent, and is arranged by printing.
  • the height of the connecting conductive material 10 depends on the electrode spacing, but when the electrode spacing is 0.5 mm, the height is about 0.1 mm.
  • FIG. 7 (b) shows a state where the semiconductor device 10 is mounted on the mounting substrate 8 after the electrodes 9 on the mounting substrate 8 are aligned with the protruding electrodes 7 of the semiconductor device 16 (FIG. 7B). No heating is done).
  • the warpage of the wiring substrate 3 was set to be within 100 zm, and the protruding electrode 7 of the semiconductor device 10 was sufficiently brought into contact with the conductive material 10 for connection.
  • Fig. 7 (c) shows a state where the above mounting board is heated at about 240 ° C, the solder is melted, and the temperature is returned to room temperature. If a glass epoxy resin, such as glass fiber, is used for the mounting board, the mounting board has a smaller coefficient of linear expansion than the wiring board 3 made of a resin material or a composite material having a high resin material ratio. The shrinkage is smaller than that of the wiring board, and the warpage of the wiring board 3 is alleviated from the state shown in FIG. 7 (b).
  • a glass epoxy resin such as glass fiber
  • the amount of warpage that is reduced from the state shown in FIG. 7 (b) to the state shown in FIG. 7 (c) is about 10 ⁇ m. Therefore, the second semi-conductor The distance between the body chip 1 b and the mounting board 8 is several tens / zm.
  • connection conductive material 16 is set to 100 im.
  • the connection conductive material 1 is set to 100 im.
  • the amount of warpage of the wiring board 3 may be appropriately determined.
  • the warpage of the wiring board 3 is set to 100 // m or less, it is preferably about 10 to 40 m.
  • FIG. 8 is a perspective view showing a schematic configuration of a portable information terminal according to Embodiment 8 of the present invention.
  • FIG. 9 is a sectional view showing a schematic configuration of the portable information terminal according to Embodiment 8 of the present invention. 2 shows a signal processing area of a substrate.
  • FIG. 8 shows a schematic configuration of a mobile phone as an example of a mobile information terminal.
  • the mobile phone 21 includes a housing 22, a keypad 23, a display 24, an antenna 25, and a plurality of mobile phones. It is composed of a mounting board 8 on which the above devices are mounted, a battery (not shown), and the like.
  • FIG. 9 shows a signal processing area of the mounting board 8 arranged in the housing 22.
  • a logic LSI 11 having a CPU function for performing basic signal processing of a portable information terminal, a memory package 12, chip components 20 such as resistors and capacitors, and a semiconductor device 10 are mounted.
  • the semiconductor device 10 includes a logic LSI (electronic component) 1 a, a logic LSI (semiconductor chip) lb, and a wiring board 3, and is mounted on a mounting board 8 with protruding electrodes 7.
  • the logic LSI 1a and the logic LSI 1b have, for example, an image signal processing function requiring a dog capacity memory function and a memory function because they can be reduced in area, thickness, and cost.
  • an example has been described in which the logic LSI 11 and the memory package 12 are separately mounted, but they may be mounted on both sides using a wiring board.
  • FIG. 10 is a cross-sectional view showing a schematic configuration of a portable information terminal according to Embodiment 9 of the present invention, showing a signal processing area of a mounting board.
  • reference numeral 8 denotes a mounting board arranged in a housing 22, on which chip parts 20 such as a semiconductor device 10, a resistor, and a capacitor are mounted.
  • the semiconductor device 10 includes a logic LSI (electronic component) l a, a logic LSI (semiconductor chip) l b, and a wiring board 3, and is mounted on a mounting board 8 with protruding electrodes 7.
  • logic LSI 1a and logic LSI 1b have both a CPU function for performing basic signal processing of a portable information terminal, an additional function such as image signal processing, and a memory function.
  • the semiconductor device 10 is configured by two logic LSIs.
  • the semiconductor device 10 may be configured by a plurality of semiconductor chips, and even if some of the semiconductor chips do not include a logic function. Good.
  • the semiconductor device 10 according to the present embodiment and the eighth embodiment is manufactured by any one of the configurations of the first to sixth embodiments or the manufacturing method of the seventh embodiment, the mounting density is reduced. It can be made high, thin and low cost.
  • the logic LSIs are mounted on both sides of the wiring board 3, the warpage of the wiring board 3 can be reduced as compared with mounting on only one side, and the thickness or coefficient of linear expansion of the logic LSIs 1a and 1b can be reduced.
  • the warpage is moderate, the contact between the logic LSI 1 b and the mounting board 8 does not occur.
  • external pressure such as bending or twisting is applied to the mounting board during use, it is mounted on a logic LSI 1b.
  • the distance from the surface of the substrate 8 was about 30 ⁇ m. Industrial applicability
  • the semiconductor device, the method for manufacturing an electronic device, the electronic device, and the portable information terminal according to the present invention include a semiconductor device that requires high-density mounting of a semiconductor chip, an electronic device such as a portable information terminal, and the like. Suitable for use in its manufacture.

Description

明 細 半導体装置、 電子機器の製造方法、 電子機器および携帯情報端末 技術分野
本発明は、 高密度に半導体チップが実装される半導体装置、 この半導 体装置が装着される携帯情報端末等の電子機器の製造方法、 電子機器及 び携帯情報端末に関するものである。 背景技術
携帯電話等の携帯情報端末に代表される電子機器では、 小型化特に薄 型化を図る必要がある。 この小型化のための半導体チップの実装方法は いろいろ提案されているが、 なかでも 2つの半導体チップを相対向させ て配線板の表面と裏面とにそれそれ配置する手法は有用である。 このよ うな、 1つの配線板の表面と裏面とに半導体チップを実装する手法には、 主に 2つの手法がある。
その 1つ目の手法は、 配線板と実装基板との間に実装接続用の基板を 設け、 この接続用の基板を介して配線板を実装基板に接続するもので、 裏面の半導体チップが実装基板に触れることなく実装できるようになつ ている。
第 1 1図は、このような手法で実装された従来の電子機器の断面図で、 例えば、 特開平 7— 2 4 0 4 9 6号公報に開示されている従来の電子機 器の断面図である。 第 1 1図に示すように、 実装基板 1 0 8に半導体装 置が装着されて電子機器が構成されている。 半導体装置は、 1つの配線 板 1 0 3の表面と裏面とにそれそれ半導体チップ 1 0 1 a、 1 0 1わが 実装された構造になっている。 そして、 配線基板 1 0 3は接続用基板 1 0 6を介して実装基板 1 0 8に接合されるとともに電気的に接続されて いる。 つまり、 配線板 1 0 3の電極 1 0 4と接続用基板 1 0 6の電極 1 1 6との電気的な接続、 および接続用基板 1 0 6の電極 1 1 6と実装基 板 1 0 8の電極 1 0 9との電気的な接続は、 いずれもはんだバンプ 1 0 7によって実現されている。 ここで、 半導体チップ 1 0 1 bの厚さは、 実装基板への接続が妨げられないように、 接続用基板 1 0 6とはんだバ ンプ 1 0 7とを合わせた厚さよりも薄く設定されている。 なお、 配線基 板 1 0 3と第 1、 第 2の半導体チップ 1 0 1 a、 1 0 1 bとは電極 1 0 2で電気的に接続されている。 また、 配線板 1 0 3と第 1、 第 2の半導 体チップ 1 0 1 a、 1 0 1 b、 配線板 1 0 3と接続用基板 1 0 6との接 続部は、 封止樹脂 1 0 5によって封止されている。
2つ目の手法は、 配線板の裏面に凹部を設けて、 この凹部に半導体チ ップを嵌め込むように装着するもので、 この手法でも裏面の半導体チッ プが実装基板に触れることなく実装できるようになつている。
第 1 2図は、このような手法で実装された従来の電子機器の断面図で、 例えば、 特開平 1 0— 7 9 4 0 5号公報に開示されている従来の電子機 器の断面図である。 第 1 2図に示すように、 配線板の裏面に凹部を設け て、 この凹部に半導体チップ 1 0 1 bを嵌め込むように装着する。 半導 体チップ 1 0 1 bの凹部への装着により、 はんだバンプ 1 0 7と実装基 板の電極 （図示は省略する） との接続は、 半導体チップ 1 0 l bに妨害 されることなく達成することができる。 なお、 配線基板 1 0 3と第 1、 第 2の半導体チップ 1 0 1 a、 1 0 1 bとは電極 1 0 2で電気的に接続 されている。 また、 配線板 1 0 3と第 1、 第 2の半導体チップ 1 0 1 a、 1 0 1 bとの接続部は、 封止樹脂 1 0 5によって封止されている。
このように、 1つ目、 2つ目の手法では、 裏面の半導体チップが実装 基板に接触しないように配線基板を実装基板に装着することができる。 しかしながら、 1つ目の手法では、 高価な接続用基板を用いなければ ならず電子機器の製造コス トを押し上げてしましまう。 さらに接続用基 板を介して配線基板と実装基板とを接合させているので、 接続用基板を 挟む分厚くなり薄型化が図りにくいという問題点があった。
2つ目の手法では、 配線板に凹部を形成しなければならず、 特別なェ 数を要することより、 この手法でも電子機器の製造コス トを押し上げて しまうという問題点があった。
また、 接続用基板を用いたり配線基板に凹部を形成したりすることな く、 両面に半導体チップが実装された配線基板を実装基板に搭載するに は、 半導体チップ 1 0 1 bの厚みを極力小さくすることが考えられる。 しかしながら、 この場合には、 半導体チップ 1 0 1 bの厚みが小さくな ることで剛性が低下し信頼性が落ちる等の問題点があった。
さらに、 通常、 微細配線を形成する配線基板は、 その材料構成から実 装基板より線膨張係数が大きく、 配線基板と実装基板とでは線膨張係数 が異なっている。 このような線膨張係数が相違する配線基板と実装基板 とを熱処理を伴ってはんだ接合すると、 室温まで戻したときに配線基板 の熱収縮が実装基板より大きいので、 第 1 3図に示すように、 配線基板 1 0 3が実装基板 1 0 8側に凸状に反る。 それに伴ない配線基板 1 0 3 の裏面に実装された半導体チップ 1 0 1 bも実装基板側に凸状に反った 状態になるので、 半導体チップ 1 0 1 bが実装基板 1 0 8に接触して破 損するという問題点があつた。
また、 半導体チップ 1 0 1 bと実装基板 1 0 3との隙間が小さいと、 実装時に半導体チップ 1 0 1 bが実装基板 1 0 8に接触しない場合でも、 製品使用時の外圧などにより実装基板 1 0 8に曲げあるいはねじり応力 が生じると、 やはり、 半導体チップ 1 0 1 bの表面が実装基板 1 0 8に 接触し、 半導体チップ 1 0 1 bが破損してしまうという問題があった。 発明の開示
本発明は、 上記のような従来の問題点を解決するためになされたもの で、 電気特性を劣化させずに配線板の両面に半導体チップを配置した低 コス トの半導体装置、 電子機器の製造方法、 電子機器及び携帯情報端末 を提供することを目的とする。
本発明に係る半導体装置は、表面及び裏面に電極を有する配線基板と、 上記配線基板の一方の面に所定高さを有するように設けられた突起電極 と、 上記配線基板の電極と電気的に接続されるように上記配線基板の上 記一方の面に設けられ厚みが上記突起電極の高さよりも小さい半導体チ ップと、 上記配線基板の上記一方の面側が凹に反るようにかつ上記配線 基板の電極と電気的に接続されるように上記配線基板の他方の面に設け られ厚みが上記半導体チップの厚みより大きい電子部品とを備えている。 かかる半導体装置では、 配線基板が突起電極 （バンプ） を設けた側に 反る （突起電極が設けられている側に凹部ができる） ようになつており、 半導体チップが実装された配線基板を実装基板に搭載する時に、 半導体 チップが実装基板に接触することがなく、 半導体チップを傷つけること なく装着できるようになつている。 さらに、 接続用基板を用いたり配線 基板に凹部を形成したりすることがないので、 安価に半導体装置を製造 することができる。
このように配線基板が突起電極を設けた側に反るようにするには、 反 りの大きさと向きが電子部品と配線基板とでほとんど決まることより、 電子部品の線膨張係数を、 配線基板の線膨張係数よりも小さくすればよ い。 また、 電子部品の線膨張係数の値を半導体チップの線膨張係数の値 以下にするのが好ましい。
配線基板の反りは、 半導体チップの縦横の寸法が同一の場合には縦横 同じの椀状の反りになり、 寸法が同一でない場合には縦方向と横方向と で反りの度合いが異なる椀状の反りになる。 この反りが大きすぎると、 実装基板上に設けた突起電極で吸収ができなくなるため、 また、 電子部 品又は半導体チップでの電気特性が劣化するため、 配線基板の反りは、 配線基板の中央部と周辺部と高さの差が 1 0 0 / m以下になるようにす るのが好ましい。 また、 必ず反りを生じさせる必要があるので、 配線基 板の中央部と周辺部と高さの差は 5 / 111〜 1 0 0 111にするのがより好 ましく、 実際の製造を考慮すると 1 0〃m〜4 0 / mにするのがよい。 また、 電子部品は、 1つの半導体チップであってもよいし、 複数の半 導体チップを複数積層したものであってもよい。 そして、 電子部品の厚 みは、 確実に剛性を高め、 電気特性の劣化を抑制するためには、 0 . 3 m m以上とすることが望ましい。 一方むやみに電子部分の厚みを厚くす ると、 半導体装置として厚くなり薄型化に逆行するので、 0 . 6 5 m m 以下程度とすることが望ましい。 なお、 さらに確実に剛性を高め、 電気 特性の劣化を防止するため、 平面的な大きさにおいて、 電子部品を半導 体チップより大きく してもよい。
また、 配線基板は、 例えばプリント基板、 プリント基板表面にェポキ シ樹脂とめっきにより微細な配線層を形成した基板、 ポリイ ミ ド樹脂と 導体からなる樹脂基板を用いるのが好ましい。
また、 本発明にかかる他の半導体装置は、 表面及び裏面に電極を有す る配線基板と、 上記配線基板の一方の面に所定高さを有するように設け られた突起電極と、 上記配線基板の電極と電気的に接続されるように上 記配線基板の上記一方の面に設けられ厚みが上記突起電極の高さより小 さい半導体チップと、 上記配線基板の電極と電気的に接続されるように 上記配線基板の他方の面に設けられ厚みが上記半導体チップの厚みより 大きくかつ線膨張係数が上記配線基板の線膨張係数よりも小さい電子部 品とを備えている。
かかる半導体装置では、 電子部品の線膨張係数を配線基板の線膨張係 数よりも小さく しているので、 配線基板が突起電極を設けた側に反るよ うになつており、 実装基板に半導体チップが実装された配線基板を搭載 する時に、 半導体チップが実装基板に接触することがなく、 半導体チッ プを傷つけることなく装着できるようになつている。 さらに、 接続用基 板を用いたり配線基板に凹部を形成したりすることがないので、 安価に 半導体装置を製造することができる。
また、 上記で説明したように、 配線基板には、 樹脂基板を用いるのが 好ましく、 電子部品の厚みとしては 0 . 3 m m以上であることが好まし い。
また、 本発明にかかる電子機器の製造方法は、 装着される側に突起電 極及び半導体チップが設けられ上記装着される側と反対側に電子部品が 設けられた半導体装置を上記突起電極を介して実装基板に装着し電子機 器を製造する電子機器の製造方法であって、 上記半導体チップの厚みが 上記突起電極の高さよりも小さく上記電子部品の厚みが上記半導体チッ プの厚みより大きく上記装着される側が凹に反っている半導体装置と上 記実装基板とを位置合わせし、 上記半導体装置が反った状態で上記半導 体装置を上記実装基板に押し付けて上記突起電極を介して上記半導体装 置を上記実装基板に装着するものである。
かかる電子機器の製造方法では、 配線基板に設けられた突起電極の高 さと半導体チップの厚さ （高さ） の差が小さくても、 配線基板の実装基 板側が凹に反つた状態で実装基板に装着されるので、 半導体チップが実 装基板に接触することなく装着され、 半導体チップが実装基板に接触し て傷つくのを防止することができる。
このように配線基板が突起電極を設けた側に反るように、 電子部品の 線膨張係数を、 配線基板の線膨張係数よりも小さくすればよい。 この場 合には、 配線基板の線膨脹係数が電子部品の線膨張係数よりも大きいの で、 冷却時の収縮量は配線基板の方が電子部品よりも大きくなる。 この ため、 配線基板が電子部品に比べてより大きく縮み、 配線基板は電子部 品側が凸状になる椀状の反りを伴なうようになる。 また、 電子部品の線 膨張係数の値を半導体チップの線膨張係数の値以下にするのが好ましい。 この半導体装置は、 加熱しながら配線基板に電子部品を接合した後に 冷却し、 上記配線基板の装着される側が凹に反るように上記配線基板に 上記電子部品を実装する工程と、 上記配線基板の装着される側に半導体 チップを実装する工程と、 上記配線基板の装着される側に突起電極を形 成する工程とを含んだ製造工程で製造すればよい。
また、 本発明にかかる電子機器は、 実装基板と、 上記実装基板上に所 定高さを有する突起電極を介して取付けられた表面及び裏面に電極を有 する配線基板と、 上記実装基板と上記配線基板との間の空間に配置され るようにかつ上記配線基板の電極と電気的に接続されるように上記配線 基板の実装基板側の面に設けられ厚みが上記突起電極の高さより小さい 半導体チップと、 上記配線基板の電極と電気的に接続されるように上記 配線基板の実装基板側と反対側の面に設けられ厚みが上記半導体チップ の厚みより大きくかつ線膨張係数が上記配線基板の線膨張係数よりも小 さい電子部品とを備えている。
また、 本発明にかかる携帯情報端末は、 筐体と、 上記筐体内に配置さ れる実装基板と、上記実装基板上に配置されたロジック L S Iチップと、 上記実装基板上に所定高さを有する突起電極を介して取付けられた表面 及び裏面に電極を有する配線基板と、 上記実装基板と上記配線基板との 間の空間に配置されるようにかつ上記配線基板の電極と電気的に接続さ れるように上記配線基板の実装基板側の面に設けられ厚みが上記突起電 極の高さより小さいメモリ又はロジック L S Iチップと、 上記配線基板 の電極と電気的に接続されるように上記配線基板の実装基板側と反対側 の面に設けられ厚みが上記半導体チップの厚みより大きくかつ線膨張係 数が上記配線基板の線膨張係数よりも小さい電子部品とを備えている。 かかる電子機器、 携帯情報端末では、 実装基板にメモリ又はロジック L S Iチップ等の半導体チップが接触することなく所定距離へだてて配 置でき、 この半導体チップを傷つけることなく装着されるので、 小型化、 軽量化に優れた電子機器、 携帯情報端末を提供することができる。
また、 上記で説明したように、 配線基板には、 樹脂基板を用いるのが 好ましく、 電子部品の厚みとしては 0 . 3 mm以上であることが好まし い o 図面の簡単な説明
第 1図はこの発明の実施の形態 1における半導体装置の概略構成を示 す断面図であり、 第 2図はこの発明の実施の形態 4における半導体装置 の概略構成を示す断面図であり、 第 3図はこの発明の実施の形態 5にお ける半導体装置の概略構成を示す断面図であり、 第 4図はこの発明の実 施の形態 5における半導体装置の概略構成を示す断面図であり、 第 5図 はこの発明の実施の形態 5における半導体装置の概略構成を示す平面図 であり、 第 6図はこの発明の実施の形態 6における半導体装置の製造方 法を示す工程図であり、 第 7図はこの発明の実施の形態 7における電子 機器の製造方法を示す工程図であり、 第 8図は、 この発明の実施の形態 8における携帯情報端末の概略構成を示す斜視図であり、 第 9図はこの 発明の実施の形態 8における携帯情報端末の概略構成を示す断面図であ り、 第 1 0図はこの発明の実施の形態 9における携帯情報端末の概略構 成を示す断面図であり、 第 1 1図は従来の半導体装置の概略構成を示す 断面図であり、 第 1 2図は従来の半導体装置の概略構成を示す断面図で あり、 第 1 3図は従来の半導体装置の概略構成を示す断面図である。 発明を実施するための最良の形態
本発明をより詳細に説述するために、 添付の図面に従ってこれを説明 する。
実施の形態 1 .
第 1図は、 この発明の実施の形態 1における半導体装置の概略構成を 示す断面図であり、 反りを実際よりも強調して示している。 第 1図にお いて、 第 1の半導体チップ l a (電子部品） と第 2の半導体チップ l b とは、 それそれ配線板 3の表面と裏面とに配置され、 それそれの面に設 けられた接続電極 2と配線板 3の電極 4とが電気的に接続されている。 これらの電極の接続部は、 封止樹脂 5により覆われ保護されている。 ま た、 配線板 3の裏面には、 実装基板 （図示せず） の電極と電気的に接続 するための接続用突起電極であるはんだバンプ 7が形成されている。 本実施の形態において、 第 2の半導体チップ 1 bの厚さははんだバン プ 7の高さより小さく構成されており、 配線基板 3の裏面、 すなわち実 装基板と配線基板との間に搭載できるようになつている。 しかも第 1の 半導体チップ 1 aの厚さを第 2の半導体チップ 1 bの厚さより大きく し て、 半導体装置 1 0としての剛性を確保できるように構成されている。 さらに、 配線基板 3は第 2の半導体チップ 1 bが搭載される裏面側に凹 状に反るように、 第 2の半導体チップ 1 bが実装基板と接触しないよう に構成されている。
例えば厚さ 0 . 4 m m程度の配線基板 3に厚さ 0 . 4 m m程度の第 1 の半導体チップ 1 aと、 厚さ 0 . 1 5 m m程度の第 2の半導体チップ 1 bを接続し、 また、 はんだバンプ 7を、 0 . 3 mm程度以下の高さ （厚 さ） に形成すると、 これらの複合体である半導体装置 1 0は、 微小のう ねりを生じずに、 1 0 m程度の反りを生じる。 この反りで、 電気特性 の劣化を生じることはない。
上記反りは、 第 1の半導体チップ 1 aと第 2の半導体チップ 1 bの厚 さを変えれば制御できる。 第 2の半導体チップ 1 b厚さは、 第 1の半導 体チップ 1 aの厚さの 6 6 %程度以下が好ましく、 また剛性を確保する 観点から 5 0 / m程度以上が好ましい。
配線基板 3の反りは、 半導体チップの縦横の寸法が同一の場合には縦 横同じの椀状の反りになり、 寸法が同一でない場合には縦方向と横方向 とで反りの度合いが異なる椀状の反りになる。この反りが大きすぎると、 実装基板上に設けた突起電極 7で吸収ができなくなるため、 また、 第 1 の半導体チップ 1 aまたは第 2の半導体チップ 1 bでの電気特性が劣化 するため、 配線基板 3の反りは、 配線基板 3の中央部と周辺部と高さの 差が 1 0 0 z m以下になるようにするのが好ましい。 また、 必ず反りを 生じさせる必要があるので、 配線基板 3の中央部と周辺部と高さの差は 5 1 0 0〃m程度にするのがより好ましく、 実際の製造を考慮す ると 1 Ο ζ π！〜 4 0 mにするのがよい。
第 1の半導体チップ 1 aの厚みは、 確実に剛性を高め、 電気特性の劣 化を抑制するためには、 0 . 3 mm以上とすることが望ましい。 一方む やみに電子部分の厚みを厚くすると、 半導体装置 1 0として厚くなり薄 型化に逆行するので、 0 . 6 5 m m以下程度とすることが望ましい。
また、 配線基板に微少なうねりとして現れる微少座屈があると、 搭載 される半導体チップの面内で応力のむらが発生し、 電気特性が劣化する が、 この実施の形態では、 局所的な反りではなく、 配線基板が全体的に 反るようにしているので、 全体的な反りは生じるものの、 半導体チヅプ の材料中に実際に生じる歪みや残留応力は、 上記の周期的な微小座屈に 比べれば、 非常に小さい値に限定され、 電気特性が劣化することはない。 実施の形態 2.
第 1図において、 第 1の半導体チップ 1 aを線膨脹係数 3. 5 1 0 -6 ( 1 /°C) 程度、 厚さ 0. 3 mm以上のシリコンチップ、 配線基板 3 を線膨脹係数 1 6 X 1 0— 6 ( 1/°C) 程度、 厚さ 0. 6 mm程度のプリ ント配線板とした。 電極の接続部を保護する樹脂は線膨脹係数が 5 0 X 1 0—6 ( 1/°C) 程度と大きいものを用いたが、 厚さは 0. 03 mm程 度と小さいため、 反りの大きさや方向に大きな影響を及ぼさない。 した がって、 反りの大きさと方向を第 1の半導体チップ 1 aと配線基板 3と で決めることができ、 冷却時の収縮量が大きい配線基板 3が第 1の半導 体チップ 1 aよりも縮み、 第 2の半導体チップ 1 b側に凹状の反りを形 成することができる。
本実施の形態において、 第 1図における配線基板 3の中央部と周辺部 との高さの差 hは、 1 0〃m程度であった。 この高さの差 hは、 はんだ バンプ 7と配線基板 3の電極との接続を確保するために、 1 00/ Π1以 下であることが望ましい。
さらに、 本実施の形態において、 第 1の半導体チップ l a、 第 2の半 導体チップ 1 bの厚さと配線板 3の厚さを種々変えて反りを算出すると、 第 1の半導体チップ 1 aの厚さが 0. 3 mm未満になると、 剛性は大き く低下し、 このために反りは急激に増加する。 したがって、 第 1の半導 体チップ l aの厚さを 0. 3mm以上に設定して、 複合体としての半導 体装置 1の剛性を低下させないことが好ましい。
このように、 第 1の半導体チップ 1 aの厚さを 0. 3 mm以上として、 第 2の半導体チップ 1 bをそれより薄くするのは、 反りの発生促進とと もに、 反りの一定範囲内への抑制という作用を有する。
実施の形態 3. 第 1図において、 第 1の半導体チップ 1 aを線膨脹係数 3. 5 x 1 0 一6 ( 1/°C) 程度、 厚さ 0. 1 5 mm程度のシリコンチップ、 第 2の半 導体チップ 1 bを線膨脹係数 5. 7 1 0-6 ( 1/°C) 程度、 厚さ 0. 1 5 mm程度のガリウム砒素 （GaAs) チップ、 配線基板 3を線膨脹 係数 1 6 X 1 0—6 ( 1/°C) 程度、 厚さ 0. 6 mm程度のプリント配線 板とした。
本実施の形態においては、 反りの大きさと方向を第 1の半導体チップ 1 aと第 2の半導体チップ 1 bで決めることができ、 冷却時の収縮量が 大きい第 2の半導体チップ 1 bが第 1の半導体チップ 1 aよりも縮み、 配線基板 3を第 2の半導体チップ 1 b側に凹状に反らせることができる。 実施の形態 4.
第 2図は、 この発明の実施の形態 4における半導体装置の概略構成を 示す断面図であり、 反りを実際よりも強調して示している。 第 2図にお いて、 第 1の半導体チップ l a (電子部品） と第 2の半導体チップ l b とは、 それそれ配線板 3の表面と裏面とに配置され、 それそれの面に設 けられた接続電極 2と配線板 3の電極 4とが電気的に接続されている。 これらの電極の接続部は、 封止樹脂 5により覆われ保護されている。 ま た、 配線板 3の裏面には、 実装基板 （図示せず） の電極と電気的に接続 するための接続用突起電極であるはんだバンプ 7が形成されている。 本実施の形態において、 第 1の半導体チップ 1 aと第 2の半導体チッ プ 1 bとは平面的な大きさが異なる。 しかも、 大きい方を第 1の半導体 チップ 1 aとして接続しているので、 上記実施の形態 1と同様に配線基 板 3を反らせることができ、 かつ剛性が向上し、 微小座屈の抑制をより 一層確実にすることができる。
実施の形態 5.
第 3図は、 この発明の実施の形態 5における半導体装置の概略構成を 示す断面図である。 第 4図は、 この発明の実施の形態 5における他の半 導体装置の概略構成を示す断面図である。 第 5図は、 第 4図に示した半 導体装置の概略平面図である。
第 3図において、 電子部品 1 aは 2つの半導体チップで構成されてお り、 この 2つのチップのトータル厚さが、 配線基板 3の反対面に搭載さ れた第 2の半導体チップ 1 bの厚さより厚く構成されている。 さらに、 配線板 3の裏面には、 実装基板 （図示せず） の電極と電気的に接続する ための接続用突起電極であるはんだバンプ 7が形成されている。
本実施の形態において、 第 2の半導体チップ 1 bの厚さははんだバン プ 7の高さより小さく構成されており、 配線基板の裏面、 すなわち実装 基板と配線基板との間に搭載できるようになつている。 しかも電子部品 1 aの厚さを第 2の半導体チップ 1 bの厚さより大きく して、 半導体装 置としての剛性を確保できるように構成されている。 さらに、 配線基板 3は第 2の半導体チップ 1 bが搭載される裏面側に凹状に反るように、 第 2の半導体チップ 1 bが実装基板と接触しないように構成されている c 上記実施の形態 1と同様に、 2つの半導体チップで構成された電子部 品 l aの厚さは、 0 . 3 m m以上が好ましい。 また、 第 2の半導体チッ プ 1 bの厚さは、 電子部品 1 aの厚さの 6 6 %以下程度が好ましい。 また、 2つのチップの搭載方法は特に限定するものではないが、 例え ば、 2つの半導体チップを接着剤で貼りあわせ、 上側の半導体チップの 電極と配線基板 3の電極との接続はワイヤを用いればよい。
本実施の形態では、 電子部品 l aとして、 2つの半導体チップを搭載 する例を示したが、 例えば第 4図に示すように、 さらに半導体チップを 搭載して、 電子部品を複数の半導体チップで構成してもよい。 複数の半 導体チップの電極と配線基板との接続は、 例えば第 5図に示すように、 接続配線同士が接触しないようにワイャで接続できる。 実施の形態 6 .
第 6図は、 この発明の実施の形態 6における半導体装置の製造方法を 示す工程図である。 本実施の形態においては、 まず、 第 6図 （a ) に示 すように、 配線基板 3の電極 4に電子部品 1 aの接続電極 2を位置合わ せし、 例えばフリップチップボンディング方法により、 接続電極 2を溶 融させて接続した後、 接続信頼性を高めるために電子部品 1 aと配線基 板 3間の隙間を封止樹脂 5で満たす。 配線基板 3に樹脂で構成される基 板を用いた場合、 線膨張係数は 1 5〜4 0 X 1 (T B ( 1 /°C ) 程度であ り、 シリコンゃガリゥム砒素などの半導体で構成される電子部品 1 aの 3〜6 X 1 0—6 ( 1 /°C) 程度に比べて大きい。 そのため、 電子部品 1 aを加熱状態で配線基板 3上に接続した後、 室温まで冷却すると、 配線 基板 3は電子部品 1 aよりも大きく縮むため、 この時点で電子部品 1 a 側に凸状に反る。
次に第 6図 （b ) に示すように、 配線基板 3の他方の面の電極 4にに 第 2の半導体チップ 1 bの接続電極 2を位置合わせし、 同様にして加熱 冷却して接続した後、 接続信頼性を高めるために第 2の半導体チップ 1 bと配線基板 3間の隙間を封止樹脂 5で満たす。 ここで、 第 2の半導体 チップ 1 bは電子部品 1 aよりも薄く、 配線基板 3を曲げる力は小さい ため、 配線基板 3は電子部品 1 a側に凸状に反ったままとなる。
厚さ 0 . 3 m mの電子部品 1 a、 厚さ 0 . 1 5 m mの第 2の半導体チ ップ l bを用いた場合、 反りは 10 / m程度となる。
次に第 6図 （ c ) に示すように、 配線基板 3の周辺に突起電極 7を形 成する。 その形成方法は、 例えば、 配線基板 3の電極 4上にはんだボ一 ル 7を配置し、 加熱してはんだを溶融する。 クリームはんだを配線基板 3の電極 4に印刷し、 加熱することによって突起電極を形成することも できる。 例えば、 はんだボール間隔を 0 . 5 m mにするためには、 直径 が 0 . 3 m m程度のはんだボールを用いればよい。 この時突起電極 7の 高さは 0 . 2 3 mm程度となる。 したがって、 突起電極 7を実装基板（図 示せず） に実装する場合、 第 2の半導体チップ 1 bの厚さが 0 . 1 5 m m、 第 2の半導体チップ 1 bを配線基板 3に接続するための接続電極 2 の高さが 3 0 z m、 配線基板 3上の電極 4の厚さが 2 0 m、 配線基板 3の反りを 1 0 z mとすると、 実装基板に搭載した時に 1 0〃mの反り のもどりがあるとしても、 第 2の半導体チップ 1 bと実装基板の間隔は 3 0 / m程度確保できる。
この間隔を確保すれば、 外圧などにより半導体装置 1 0が実装基板に 押付けられても、 第 2の半導体チップ 1 bは実装基板に接触しない。 このように、 配線基板 3を反らせた状態で、 半導体装置 1 0を製造す ることができる。
なお、 本実施の形態において、 電子部品 1 aを配線基板 3に実装する 方法として、 フリップチップボンディングの例を示したが、 さらに詳し くは異方性導電接着フィルム （導電粒子をエポキシ樹脂フィルム中含有 させたフィルム） を配線基板 3に配置し、 これに、 加熱した半導体チッ プを押しつけた。 上記異方性導電接着フィルムは例えば熱硬化型のェポ キシ接着剤からなっているために、 加熱しながら電子部品 1 aを配線基 板 3に押しつけている間に樹脂は硬化する。
また、 はんだを用いたフリップチップボンディングでもよい。 はんだ は鉛すずまたは銀すずなどの合金が用いられ、 例えば蒸着、 はんだべ一 ス トを印刷、 ボールボンダなどにより形成できる。 はんだに換えて金や 銅などを用いてもよい。 この場合、 導電性接着剤または導電粒子を接続 電極 2と配線基板 3の電極 4に介在させて接続することができる。 また 接続電極 2と配線基板 3の電極 4との間にはんだを介在させて接続して もよい。 また、 フリップチップボンディングに換えてワイヤボンディン グを用いてもよい。
また、 配線基板 3は例えばプリント基板、 ポリイ ミ ド樹脂などの樹脂 材料が用いられる。 特に電子部品 1 a、 第 2の半導体チップ 1 bの電極 4の間隔が小さい （ 1 00〃m以下） 場合、 プリント基板では小間隔で 電極を形成できないため、 プリント基板上の樹脂層にめっきなどで微細 な配線層を形成するビルトァップ基板を用いることができる。
実施の形態 7.
第 7図は、 この発明の実施の形態 7における電子機器の製造方法を示 す工程図である。 本実施の形態においては、 まず、 第 7図 （a) に示す ように、 実装基板 8の電極 9上に接続用導電材 1 6を配置する。 接続用 導電材 1 6は例えば微細なはんだ粒子を溶剤に溶かしたクリーム状であ つて、 印刷で配置される。 接続用導電材 1 0の高さは電極間隔に依存す るが、 電極間隔が 0. 5 mmの場合、 0. 1 mm程度とする。
第 7図 （b) は、 上記実装基板 8上の電極 9と、 半導体装置 1 6の突 起電極 7の位置合わせをした後、 半導体装置 1 0を実装基板 8上に搭載 した状態を示す （加熱は行っていない） 。 ここで、 配線基板 3の反りは 1 00 zm以内とし、 半導体装置 1 0の突起電極 7を接続用導電材 1 0 に十分接触するようにした。
第 7図 （ c) は上記実装基板を 240°C程度で加熱して、 はんだを溶 融し、 室温に戻した状態を示す。 実装基板に例えばガラス繊維のはいつ たガラスエポキシ樹脂を用いると、 上記実装基板は、 樹脂材料あるいは 樹脂材料比率の高い複合材料で構成される配線基板 3よりも線膨張係数 が小さ,いため、 熱収縮が配線基板よりも小さく、 配線基板 3のそりは第 7図 （b) の状態より緩和される。
本実施の形態において、 第 7図 （b) の状態から第 7図 （ c) の状態 で緩和される反り量は 1 0〃m程度であった。 したがって、 第 2の半導 体チップ 1 bと実装基板 8との間隔は数十/ z m確保できている。
なお、 本実施の形態において、 接続用導電材 1 6の高さを 1 0 0 i m とする例を示したが、 電極 9の間隔が小さくなるほど、 接続用導電材 1
6の高さを低くせざるをえなくなる。 したがって、 第 2の半導体チップ 1 bと実装基板 8との間隔を確保するためには、 適宜上記配線基板 3の 反り量を決めればよい。
配線基板 3の反りを 1 0 0 // m以下としたが、 1 0〜 4 0〃m程度が 好ましい。
実施の形態 8 .
第 8図は、 この発明の実施の形態 8における携帯情報端末の概略構成 を示す斜視図、 第 9図はこの発明の実施の形態 8における携帯情報端末 の概略構成を示す断面図であり、 実装基板の信号処理領域を示す。
第 8図は、携帯情報端末の例として携帯電話の概略構成を示しており、 携帯電話 2 1は、 筐体 2 2、 キ一パッ ト部 2 3、 ディスプレイ 2 4、 ァ ンテナ 2 5、 複数のデバイスを搭載した実装基板 8、 電池 （図示せず） などから構成される。
第 9図は、 筐体 2 2内に配置された実装基板 8の信号処理領域を示し ている。 実装基板 8には、 携帯情報端末の基本信号処理を行う C P U機 能を有するロジック L S I 1 1、 メモリパッケージ 1 2、 抵抗、 コンデ ンサなどのチップ部品 2 0、 および半導体装置 1 0が実装されている。 半導体装置 1 0はロジック L S I (電子部品） 1 a、 ロジック L S I (半 導体チップ） l bと、 配線基板 3で構成されており、 突起電極 7で実装 基板 8に実装される。
上記ロジック L S I 1 a、 ロジック L S I 1 bは例えば犬容量メモリ 機能を要する画像信号処理機能とメモリ機能を併せ持つたものとすれば、 小面積化、 薄型、 低コス ト化ができて好ましい。 本実施の形態において、 ロジック L S I 1 1、 メモリパッケージ 1 2 を別々に実装する例を示したが、配線基板を用いて両面実装してもよい。 実施の形態 9 .
第 1 0図は、 この発明の実施の形態 9における携帯情報端末の概略構 成を示す断面図であり、 実装基板の信号処理領域を示す。
図において、 8は筐体 2 2内に配置される実装基板で、 半導体装置 1 0、 抵抗、 コンデンサなどのチップ部品 2 0が実装されている。 半導体 装置 1 0はロジック L S I (電子部品） l a、 ロジック L S I (半導体 チップ） l bと、 配線基板 3で構成されており、 突起電極 7で実装基板 8に実装される。
上記ロジック L S I 1 a、 ロジック L S I 1 bは、 携帯情報端末の基 本信号処理を行う C P U機能と画像信号処理などの追加機能とメモリ機 能を併せ持つている。
本実施の形態において、 半導体装置 1 0を 2つのロジック L S Iで構 成する例について示したが、 複数の半導体チップで構成してもよく、 そ の一部がロジック機能を含んでいなくてもよい。
本実施の形態、 および上記実施の形態 8における半導体装置 1 0は、 上記実施の形態 1〜 6のいずれかの構成、 あるいは上記実施の形態 7の 製造方法によって製造されているので、 実装密度が高く、 かつ薄く、 低 コス トで構成できる。
また、 配線基板 3の両側にロジック L S Iを実装したので、 片側のみ に実装する場合より配線基板 3の反りを緩和でき、 かつロジック L S I 1 aとロジック L S I 1 bの厚さ、 あるいは線膨張係数を変えて、 適度 な反りをもたせているので、 ロジック L S I 1 bと実装基板 8との接触 も起こらない。 特に、 情報携帯端末にあっては、 使用時に実装基板に曲 げやねじりなどの外圧が加わりたわむため、 ロジック L S I 1 bと実装 基板 8の表面との間隔は 3 0〃m程度とした。 産業上の利用可能性
以上のように、 本発明にかかる半導体装置、 電子機器の製造方法、 電 子機器及び携帯情報端末は、 高密度に半導体チップを実装する必要のあ る半導体装置、 携帯情報端末等の電子機器及びその製造に用いるのに適 している。

Claims

請 求 の 範 囲
1 . 表面及び裏面に電極を有する配線基板と、 上記配線基板の一方の面 に所定高さを有するように設けられた突起電極と、 上記配線基板の電極 と電気的に接続されるように上記配線基板の上記一方の面に設けられ厚 みが上記突起電極の高さよりも小さい半導体チップと、 上記配線基板の 上記一方の面側が凹に反るようにかつ上記配線基板の電極と電気的に接 続されるように上記配線基板の他方の面に設けられ厚みが上記半導体チ ップの厚みより大きい電子部品とを備えた半導体装置。
2 . 電子部品の線膨張係数が、 配線基板の線膨張係数より小さい請求 の範囲第 1項に記載の半導体装置。
3 . 電子部品の線膨張係数の値が、 半導体チップの線膨張係数の値以 下である請求の範囲第 1項に記載の半導体装置。
4 . 反りは椀状の反りで、 配線基板の中央部と周辺部と高さの差が 1 0 以下である請求の範囲第 1項に記載の半導体装置。
5 . 電子部品は複数の半導体チップを積層したものである請求の範囲 第 1項に記載の半導体装置。
6 . 電子部品の厚みが 0 . 3 mm以上である請求の範囲第 1項に記載 の半導体装置。
7 . 平面的な大きさにおいて、 電子部品が半導体チップより大きい請 求の範囲第 1項に記載の半導体装置。
8 . 配線基板が樹脂基板である請求の範囲第 1項に記載の半導体装置。 9 . 表面及び裏面に電極を有する配線基板と、 上記配線基板の一方の 面に所定高さを有するように設けられた突起電極と、 上記配線基板の電 極と電気的に接続されるように上記配線基板の上記一方の面に設けられ 厚みが上記突起電極の高さより小さい半導体チップと、 上記配線基板の 電極と電気的に接続されるように上記配線基板の他方の面に設けられ厚 みが上記第 1の半導体チップの厚みより大きくかつ線膨張係数が上記配 線基板の線膨張係数よりも小さい電子部品とを備えた半導体装置。 1 0 . 配線基板が樹脂基板である請求の範囲第 9項に記載の半導体装
1 1 . 電子部品の厚みが 0 . 3 m m以上である請求の範囲第 9項に記 載の半導体装置。
1 2 . 装着される側に突起電極及び半導体チップが設けられ上記装着 される側と反対側に電子部品が設けられた半導体装置を上記突起電極を 介して実装基板に装着し電子機器を製造する電子機器の製造方法であつ て、
上記半導体チップの厚みが上記突起電極の高さよりも小さく上記電子 部品の厚みが上記半導体チップの厚みより大きく上記装着される側が凹 に反っている半導体装置と上記実装基板とを位置合わせし、 上記半導体 装置が反った状態で上記半導体装置を上記実装基板に押し付けて上記突 起電極を介して上記半導体装置を上記実装基板に装着する電子機器の製 造方法。
1 3 . 電子部品の線膨張係数が、 配線基板の線膨張係数よりも小さい 請求の範囲第 1 2項に記載の電子機器の製造方法。
1 4 . 電子部品の線膨張係数の値が、 半導体チップの線膨張係数の値 以下である請求の範囲第 1 2項に記載の電子機器の製造方法。
1 5 . 半導体装置は、
加熱しながら配線基板に電子部品を接合した後に冷却し、 上記配線基 板の装着される側が凹に反るように上記配線基板に上記電子部品を実装 する工程と、 上記配線基板の装着される側に半導体チップを実装する工程と、 上記配線基板の装着される側に突起電極を形成する工程と
を含んだ製造工程で製造される請求の範囲第 1 2項に記載の電子機器の 製造方法。
1 6 . 実装基板と、 上記実装基板上に所定高さを有する突起電極を介し て取付けられた表面及び裏面に電極を有する配線基板と、 上記実装基板 と上記配線基板との間の空間に配置されるようにかつ上記配線基板の電 極と電気的に接続されるように上記配線基板の実装基板側の面に設けら れ厚みが上記突起電極の高さより小さい半導体チップと、 上記配線基板 の電極と電気的に接続されるように上記配線基板の実装基板側と反対側 の面に設けられ厚みが上記半導体チップの厚みより大きくかつ線膨張係 数が上記配線基板の線膨張係数よりも小さい電子部品とを備えた電子機 器。
1 7 . 配線基板が樹脂基板である請求の範囲第 1 6項に記載の電子機 器。
1 8 . 電子部品の厚みが 0 . 3 m m以上である請求の範囲第 1 6項に 記載の電子機器。
1 9 . 筐体と、 上記筐体内に配置される実装基板と、 上記実装基板上に 配置されたロジック L S Iチップと、 上記実装基板上に所定高さを有す る突起電極を介して取付けられた表面及び裏面に電極を有する配線基板 と、 上記実装基板と上記配線基板との間の空間に配置されるようにかつ 上記配線基板の電極と電気的に接続されるように上記配線基板の実装基 板側の面に設けられ厚みが上記突起電極の高さより小さいメモリ又は口 ジック L S Iチップと、 上記配線基板の電極と電気的に接続されるよう に上記配線基板の実装基板側と反対側の面に設けられ厚みが上記半導体 チップの厚みより大きくかつ線膨張係数が上記配線基板の線膨張係数よ りも小さい電子部品とを備えた携帯情報端末。
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KR20020013551A (ko) 2002-02-20
EP1189282A1 (en) 2002-03-20
CN1207785C (zh) 2005-06-22
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US6905911B2 (en) 2005-06-14
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US20040021212A1 (en) 2004-02-05

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