Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Definitions

• the present invention relates generally to integrated circuits and methods of fabricating such circuits and, more specifically, NAND flash memory cells and methods of fabrication thereof.
• a NAND-structured memory string has several floating gate memory transistors (typically 8 or 16) connected in series between two select gates. The area occupied by the memory transistors is called the core region.
• the control gates of the memory transistors are connected to other parallel NAND strings by wordlines to form a NAND memory array.
• the parallel NAND strings are separated by a core field oxide region.
• NAND flash memory strings are typically fabricated using a "dual-gate oxidation" process where the gate oxide of the select transistors is first thermally grown on a silicon substrate. The select transistor areas are then masked with photo-resist and the gate oxide in the core region is etched away, typically in a buffer oxide etch process, to expose the silicon substrate. The photo-resist is then removed and the gate oxide is thermally regrown to define the final gate oxide thickness of the two select gate transistors and the sixteen floating gate memory transistors. This approach resulted in a select transistor gate oxide thickness of 150A- 180A and a memory transistor gate oxide thickness of 85A-105A, as illustrated in Fig. 1.
• Fig. 1 shows a select transistor area 12 and a core transistor area 13.
• the oxide layer 14 grown over the P-well 11 is thicker in select transistor area 12 than in core transistor area 13.
• the select gate oxide is thicker than the core tunnel oxide in order to prevent band-to-band tunneling current between source/drain region 17 and P-well 11. In order for the select gate to function in spite of the thick select gate oxide, source/drain region 17 must be doped.
• Making the select gate oxide thicker than the core tunnel oxide adds several steps to the fabrication of the NAND string. Additional processing steps increase the cost of fabricating the device. Further, these additional steps can affect the reliability of the NAND string. For example, the masking and etching steps can leave contaminants on the surface of the NAND string or introduce defects into the NAND string. Such contaminants and defects can degrade the core tunnel oxide and, as a result, lead to poor reliability of the memory cells. Also, the masking step increases the amount of space required for the NAND string because imprecision inherent in any masking step requires that a tolerance area be masked in addition to the select gate area.
• the present invention provides a single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the 16 floating gate memory transistors are fabricated in a single oxidation step.
• the oxidation process can be either dry, wet or nitrided.
• the two select gate transistors and the floating gate memory transistors have the same oxide thickness (85A-105A).
• the medium doped source/drain region is doped with Arsenic to a concentration of lO ⁇ -lO 1 /cm 2 .
• FIG. 1 shows a select gate and a memory cell of a NAND flash memory according to the prior art.
• FIG. 2-6 are simplified cross-sectional views of a select gate and a memory cell of a NAND flash memory illustrating various stages in the fabrication of an embodiment of the present invention.
• FIG. 7-11 are simplified top views of a portion of a NAND memory array illustrating various stages in the fabrication of an embodiment of the present invention.
• FIG. 2 shows a simplified cross section of an embodiment of the present invention depicting a select gate area 12 and a core memory cell 13 of a single NAND string at an early stage in fabrication.
• the NAND string also includes several more core memory cells connected in series with depicted core memory cell 13 and an additional select gate connected to the last one of the several more core memory cells.
• the NAND string is connected to several other parallel NAND strings to form a NAND array.
• the portion shown includes a P-well 22 formed in an N-well 21, which is formed in substrate 20.
• the entire NAND array is formed in P-well 22.
• a layer of oxide 24 is formed over P-well 22.
• the portion of oxide layer 24 in area 12 is the select gate oxide.
• oxide layer 24 in area 13 is the tunnel oxide of memory cell 13.
• the select gate oxide and the tunnel oxide are the same thickness.
• oxide layer 24 is 85- 105 A thick.
• Oxide layer 24 may be formed by wet oxidation or dry oxidation, or may be formed by either wet or dry oxidation followed by nitridation.
• FIG. 7 illustrates a top view of a portion of a NAND array. Oxide layer 24 is formed over a P-well (not shown) in substrate 20. A core field oxide layer between the NAND strings is defined before oxide layer 24 is formed.
• First polysilicon layer 30 forms the floating gates of the memory cell transistors.
• FIG. 8 illustrates a top view of a portion of a NAND array.
• First polysilicon layer 30 of FIG. 3 is formed by masking the areas 82 between NAND strings 80 to define the floating gates of the memory cells.
• the first polysilicon layer is etched to remove the polysilicon formed over the core field oxide layer, then a channel stop implant is performed.
• first polysilicon layer 30 is formed by chemical vapor deposition.
• separation layer 40 is formed on first polysilicon layer 30. Separation layer 40 separates the floating gates of the core memory cells from the control gates of the core memory cells.
• separation layer 40 is an ONO layer formed by first depositing an oxide layer by high temperature chemical vapor deposition oxidation, then depositing a nitride layer, then depositing a second oxide layer on top of the nitride layer by wet oxidation.
• separation layer 40 is a nitride layer.
• FIG. 8 illustrates a top view of a portion of a NAND array with a separation layer 90 formed over the NAND array.
• FIG. 5 depicts a select gate and core memory cell after a second polysilicon layer 50 is formed on separation layer 40.
• Second polysilicon layer 50 defines the control gates of the select transistors and the core memory transistors.
• Second polysilicon layer 50 also defines the select lines that connect the select gates of different NAND strings and the word lines that connect the core memory cells of different NAND strings.
• FIG. 10 illustrates a top view of a portion of a NAND array after a second polysilicon layer 100 is formed over the NAND array.
• FIG. 6 depicts the structure of FIG. 5 after a section 60 of oxide layer 24, first polysilicon layer 30, separation layer 40, and second polysilicon layer 50 has been etched away, exposing P-well 22.
• a medium doped source/drain region shared by select transistor 12 and core memory cell 13 is then implanted.
• a careful selection of the medium doped source/drain region implant conditions is necessary to minimize the band-to- band tunneling current, which can degrade the NAND flash cell program operation and damage the select-gate oxides.
• the medium doped source/drain region is doped with Arsenic to a concentration of 10 13 -10 14 /cm 2 .
• the NAND string has a number of medium doped source/drain regions equal to the number of core memory cells plus one.
• FIG. 11 illustrates a top view of a portion of a NAND array after the second polysilicon layer, separation layer, first polysilicon layer, and oxide layer have been etched away. Medium doped source/drain regions 112 indicate where the layers have been etched away.
• the remaining second polysilicon layer forms the control gates of the select transistors and the memory cells.
• the remaining second polysilicon layer forms select line 110 and wordlines 114.
• first polysilicon layer 30A (FIG. 6) and second polysilicon layer 50A of select transistor 12 are shorted together to form a single control gate instead of a floating gate formed in first polysilicon layer 30 and a control gate formed in second polysilicon layer 50.
• the single tunnel gate oxidation process eliminates one major masking step, one thermal cycle and associated cleaning and etching steps.
• a NAND memory array is less expensive to fabricate using the single tunnel gate oxidation process rather than the dual-gate oxidation process described above.
• eliminating the masking step eliminates the tolerance space required for the masking step, thus a more compact NAND string can be fabricated using the single tunnel gate oxidation approach.
• Elimination of the masking step and the associated buffer oxide etch step also results in increased isolation between the NAND strings. As described above, the NAND strings in the array are separated by core field oxide layers.
• NAND memory arrays formed by the single tunnel gate oxidation process are more reliable and more durable than NAND memory arrays formed by the dual gate process, as demonstrated by in-house endurance cycling tests, read disturb tests, and data retention tests.
• NAND memory arrays formed by the single tunnel gate oxidation process show an improved coupling ratio between the floating gate and the control gate.
• the coupling ratio refers to the voltage drop across the dielectric layer separating the floating gate and the control gate.
• a voltage is applied on the control gate, there is a first voltage drop across the dielectric layer separating the floating gate and the control gate, and a second voltage drop across the tunnel oxide layer. It is desirable to maximize the voltage drop across the tunnel oxide layer and minimize the voltage drop across the dielectric layer separating the floating gate and the control gate because the voltage drop across the tunnel oxide layer determines the amount of tunneling current passing through the tunnel oxide during program or erase. As the amount of tunneling current through the tunnel oxide increases, the time required to program or erase the memory device decreases.
• Elimination of a masking step and related steps in the single tunnel gate oxidation process changes the profile of the core field oxide separating the NAND strings, which has a favorable affect on the coupling ratio, which, for a given voltage, decreases the amount of time required to program or erase the memory device.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Non-Volatile Memory (AREA)
• Semiconductor Memories (AREA)

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• 2000
  • 2000-03-09 US US09/522,247 patent/US6429479B1/en not_active Expired - Lifetime
• 2001
  • 2001-03-05 JP JP2001566166A patent/JP2003526915A/ja active Pending
  • 2001-03-05 CN CNB018062393A patent/CN1198322C/zh not_active Expired - Lifetime
  • 2001-03-05 WO PCT/US2001/040259 patent/WO2001067490A2/en not_active Ceased
  • 2001-03-05 EP EP01931109A patent/EP1261987A2/en not_active Ceased
  • 2001-03-05 KR KR1020027011819A patent/KR20020086628A/ko not_active Ceased
  • 2001-03-07 TW TW090105267A patent/TW479284B/zh not_active IP Right Cessation
• 2007
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