Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

• the present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly suitable for use in a nonvolatile semiconductor memory capable of recording 2-bit information in one memory cell.
• non-volatile semiconductor memories that can record two bits of information in one memory cell by changing the carrier injection position have been researched and developed.
• This non-volatile semiconductor memory is a memory in which a carrier is captured by a charge trapping film provided below a gate, and a direction of a voltage applied between source drains when information is written and when information is read out.
• the configuration is such that electrons are independently captured in the charge trapping films at positions corresponding to both ends of the channel region in the opposite direction. Then, two-bit information can be recorded depending on whether or not electrons are captured at each end.
• International Publication WO99Z700000 discloses a nonvolatile semiconductor memory having the above-described configuration.
• FIG. 8 a brief description will be given of the configuration of the nonvolatile semiconductor memory and data write / read operations disclosed in the publication.
• the nonvolatile semiconductor memory 100 has a pair of impurity diffusion layers 102, 100 functioning as a source / drain formed in the surface region of the p-type silicon semiconductor substrate 101. 3 and an insulating film having a three-layer structure formed on the p-type silicon semiconductor substrate 101 between the impurity diffusion layers 102 and 103 and the insulating film having the three-layer structure. And a gate electrode 107.
• the insulating film having a three-layer structure includes a gate insulating film (silicon oxide film) 104, a charge trapping film (silicon nitride film) 105, and a silicon oxide film 106.
• the nonvolatile semiconductor memory 100 is configured to capture electrons independently at positions corresponding to both ends of the channel region in the charge trapping film.
• One bit per GHT BIT and LEFT BIT a total of 2 bits of information can be recorded.
• Information is recorded by injecting electrons into the interface between the gate insulating film 104 and the charge trapping film 105.
• the RI GHT BIT the area 10 shown in FIG.
• electrons are injected into 9 and information is recorded in LEFT BIT, electrons are injected into area 108.
• a source is set to 0 V and a drain is set to about 5 V to generate a potential difference between the source and drain, and a high voltage (about 10 V) is applied to the gate 107.
• a channel 110 is formed between the source and the drain. Since an electric field is caused by the potential difference between the channel 1 1 0 is not formed range 1 2 In the source / drain, channel hot Tereku Tron occurs in the range 1 2, electrons trapped in the area 1 0 9 ( Trap).
• Writing and reading of information to and from the LEFT BIT can be performed in the same way as for RI GHT BIT, and voltages in the opposite direction to the direction of the voltage applied when writing and reading information to and from the RI GHT BIT Can be carried out by applying
• the injection position of the channel hot electron generated to raise the threshold value of the memory cell at the time of writing is determined by the drain 103 and the gate electrode.
• Voltage applied to 107 In the above-described conventional configuration, although it is necessary to localize electrons in the region 109, the gate insulating film 1 in the center of the channel where electrons should not be injected originally should be used. A problem arises in that electrons are also captured during 04.
• the hot hole injected when the threshold value of the memory cell is lowered is different from the above-described hot electron in the generation mechanism. Because of the differences, the injection positions of both do not always match. Therefore, while writing and erasing are repeated, there is a case where one of the charges remains in the silicon nitride film 105, resulting in a problem that writing or erasing failure occurs.
• This problem can be mitigated by injecting too many electrons to raise the threshold and excessively injecting holes to lower the threshold, but excessively increasing the number of carriers Doing so causes another problem of slowing down the writing and erasing speeds and deteriorating the performance of the device.
• excessive injection of carriers applies excessive electrical stress to the insulating film, which causes dielectric breakdown with time and is not desirable from the viewpoint of device reliability.
• the hole generation efficiency is not always optimal, so that the device characteristics also deteriorate.
• the present invention has been made to solve such a problem.
• a semiconductor memory device that records two bits of information by changing the carrier injection position, the two bits of information can be reliably recorded. It is an object of the present invention to provide a semiconductor memory device capable of recording and holding data, suppressing occurrence of a writing defect or an erasing defect, and improving reliability, and a method of manufacturing the same. Disclosure of the invention
• a semiconductor memory device includes a pair of impurity diffusion layers formed in a surface region of a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the pair of impurity diffusion layers via a gate insulating film.
• a semiconductor memory device configured to capture a carrier in the gate insulating film by applying a predetermined voltage to the gate electrode.
• the gate insulating film is formed such that a carrier trap characteristic at a position close to each of the pair of impurity diffusion layers is higher than other regions.
• the method of manufacturing a semiconductor memory device includes a first step of sequentially forming first and second insulating films on a semiconductor substrate, and a method of selectively removing the first and second insulating films.
• the method includes a ninth step of forming a conductive film over the insulating film, and a tenth step of patterning the conductive film into a gate electrode shape.
• a step of forming a first insulating film on a semiconductor substrate a step of selectively removing the first insulating film to expose the underlying semiconductor substrate
• introducing an impurity into the exposed semiconductor substrate using the first insulating film as a mask to form a pair of independent impurity diffusion layers each in a surface region of the semiconductor substrate on both sides of the first insulating film.
• the fifth insulating film is removed so as to remain only on the semiconductor substrate, a sidewall made of the fifth insulating film is formed on a side wall of the second insulating film, and the semiconductor substrate in the element active region is formed. Exposing; forming a sixth insulating film on the exposed semiconductor substrate; removing the side wall to expose the fourth insulating film below the side wall; Using a fourth insulating film as a charge trapping film, forming a seventh insulating film on the charge trapping film, and forming a conductive film covering the sixth and seventh insulating films. Having.
• the present invention comprises the above technical means, when a high voltage is applied to the gate electrode to generate hot electrons at the time of data writing, the end portion having a higher carrier trap characteristic than the center portion of the channel width in the gate insulating film. Electrons are injected into the substrate. This makes it possible to collect electrons intensively at the edge of the gate insulating film below the gate electrode. Similarly, when data is erased, hot holes can be intensively injected into the edge of the gate insulating film, so that data can be erased stably.
• FIGS. 1A to 1G are schematic sectional views showing a method for manufacturing a nonvolatile semiconductor memory according to the first embodiment of the present invention in the order of steps.
• FIG. 2 is a schematic plan view showing a planar configuration of the nonvolatile semiconductor memory according to each embodiment of the present invention.
• FIG. 3 is a schematic plan view showing in detail the planar configuration of the nonvolatile semiconductor memory according to each embodiment of the present invention.
• 4A and 4B are schematic cross-sectional views showing the write and read operations of the nonvolatile semiconductor memory according to each embodiment of the present invention.
• FIGS. 5A to 5G show the fabrication of a nonvolatile semiconductor memory according to the second embodiment of the present invention. It is an outline sectional view showing a fabrication method in order of a process.
• 6A to 6G are schematic cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory according to the third embodiment of the present invention in the order of steps.
• FIG. 7A to 7F are schematic cross-sectional views showing a method for manufacturing a nonvolatile semiconductor memory according to the fourth embodiment of the present invention in the order of steps.
• FIG. 8 is a schematic sectional view showing a configuration of a conventional nonvolatile semiconductor memory.
• FIGS. 1A to 1G are schematic cross-sectional views illustrating a method for manufacturing the nonvolatile semiconductor memory according to the first embodiment in the order of steps.
• FIGS. 2 and 3 are schematic plan views showing a plan configuration of the nonvolatile semiconductor memory according to the first embodiment.
• FIG. 1 focuses on one memory cell of the nonvolatile semiconductor memory, and shows a cross-section of the memory cell in the order of the manufacturing process. The corresponding cross section is shown.
• a predetermined well is formed on the p-type silicon semiconductor substrate 1, and further, element isolation in the peripheral circuit area is performed (not shown).
• a silicon oxide film 2 is grown to a thickness of about 20 nm by a thermal oxidation method, and a silicon nitride film 3 is formed on the silicon oxide film 2 by a CVD method. Is deposited to a thickness of about 200 nm.
• the silicon nitride film 3 and the silicon oxide film 2 are left on the p-type silicon semiconductor substrate 1 in a portion to be the channel region of the memory cell, and the silicon nitride film 3 in other regions is left. Then, the silicon oxide film 2 is removed.
• an annealing treatment is performed in an ammonia (NH 3 ) gas atmosphere at a temperature of about 950 for about 20 minutes to about 120 minutes.
• a silicon nitride film 4 is formed over the P-type silicon semiconductor substrate 1 and a predetermined range below the pattern end of the silicon nitride film 3.
• a silicon nitride film 4 is formed by a direct reaction between silicon and ammonia gas.
• a silicon nitride film 4 is formed by a reaction with ammonia diffused in the silicon oxide film 2.
• the formation of the silicon nitride film 4 may be performed by an ion implantation method.
• ions containing nitrogen (N 2 ) and the like are implanted under the conditions of an acceleration energy of about 30 keV and a dose of about 1 ⁇ 10 16 (ions / cm 2 ), and annealing is performed.
• a film containing nitrogen is formed near the surface of the P-type silicon semiconductor substrate 1.
• the width of the silicon nitride film 4 formed below the pattern end of the silicon nitride film 3 can be controlled.
• ions are implanted into the surface region of the p-type silicon semiconductor substrate 1 using the silicon nitride film 3 as a mask.
• arsenic (As) which is an n-type impurity
• As arsenic
• the impurities implanted by this ion implantation become a pair of impurity diffusion layers 6 functioning as a source and a drain in the surface region of the p-type silicon semiconductor substrate 1 on both sides of the silicon nitride film 3.
• the impurity diffusion layer 6 functions as a bit line, a plurality of impurity diffusion layers 6 are formed so as to extend in a predetermined direction and connected to each memory cell as shown in FIG. Is done.
• the surface of the p-type silicon semiconductor substrate 1 is selectively oxidized by thermal oxidation.
• the oxidation resistance of the silicon nitride film 4 in the arsenic-implanted region has been lost due to the ion implantation in the process of FIG. 1C.
• the surface of the P-type silicon semiconductor substrate 1 other than the lower layer of the film 3 is oxidized, so-called LOCO S (Local ox i da ti on of silicon)
• a silicon oxide film 5 as element isolation grows. Then, an element active region is defined on the p-type silicon semiconductor substrate 1 by the silicon oxide film 5.
• the p-type silicon semiconductor substrate 1 is immersed in a phosphoric acid solution at a temperature of about 150 to dissolve and remove the silicon nitride film 3.
• the silicon nitride film 4 is not removed by phosphoric acid and is not removed. To remain.
• the silicon oxide film 2 on the p-type silicon semiconductor substrate 1 is immersed and removed in a hydrofluoric acid (HF) solution. Thereafter, thermal oxidation is performed to form a silicon oxide film 7 as a gate insulating film with a thickness of about 15 nm. At this time, in the portion where the silicon nitride film 4 is formed, the oxidation rate due to thermal oxidation is reduced by the action of the silicon nitride film 4, so that the silicon oxide film 7 at this position is formed thinner than other regions. Is done.
• HF hydrofluoric acid
• the silicon nitride film 4 is covered with the silicon oxide film 7, and on the p-type silicon semiconductor substrate 1 near each of the pair of impurity diffusion layers 6, a silicon nitride film is formed in the silicon oxide film 7.
• a gate insulating film having a structure including 4 is formed.
• the silicon oxide film 4 Since the silicon nitride film 4 has higher carrier trapping characteristics than the silicon oxide film 7, the silicon oxide film 4 functioning as a gate insulating film is partially included in the silicon The trap characteristics can be improved as compared with other regions of the silicon oxide film 7. That is, by forming the silicon nitride film 4 at the end of the silicon oxide film 7, it is possible to form a gate insulating film in which the equivalent capacitance at the end of the channel region is smaller than that near the center of the channel region. it can. In addition, since the silicon oxide film 7 is formed thicker in the region where the silicon nitride film 4 is not formed than in the region where the silicon nitride film 4 is formed, when a voltage is applied to the gate electrode formed above. Thus, carrier traps to gate oxide film 7 are suppressed. Therefore, the carrier trap characteristic at the end of the channel region can be improved as compared with the vicinity of the center of the channel region.
• a polycrystal doped with phosphorus (P) by CVD A silicon film 8 is formed on the entire surface of the p-type silicon semiconductor substrate 1, and a tungsten silicide film 9 is deposited on the polycrystalline silicon film 8 to a thickness of about 100 nm by a CVD method. After that, the polycrystalline silicon film 8 and the tungsten silicide film 9 are patterned into a gate electrode shape by photolithography and subsequent dry etching. Thus, a gate electrode having a polysilicon structure composed of the polycrystalline silicon film 8 and the tungsten silicide film 9 is formed.
• the source and drain diffusion layers (impurity diffusion layer 6), gate insulating film (silicon oxide film 7, silicon nitride film 4), and gate electrode (polysilicon film 8), which are the main parts of the transistor, are formed.
• the formation of the tungsten silicide film 9) is completed.
• a general wiring layer forming process is performed to complete the nonvolatile semiconductor memory according to the present embodiment. That is, an interlayer insulating film (silicon oxide film or the like) is deposited by the CVD method, and the gate electrode composed of the polycrystalline silicon film 8 and the tungsten silicide film 9 is covered, and then photolithography and subsequent dry etching are performed. A contact hole is formed in the interlayer insulating film. Then, for example, an aluminum film is deposited as a wiring layer on the interlayer insulating film by a sputtering method to fill contact holes, and the aluminum film is patterned into a predetermined shape by photolithography and subsequent dry etching. After that, a protective film is formed so as to cover the aluminum film.
• an interlayer insulating film silicon oxide film or the like
• FIG. 2 is a diagram showing the overall plan configuration of the completed nonvolatile semiconductor memory according to the present embodiment, and the illustration of the interlayer insulating film and the aluminum film on the gate electrode is omitted.
• a plurality of gate electrodes (polycrystalline silicon film 8, tungsten silicide film 9) are arranged side by side, and are orthogonal to the impurity diffusion layer 6, which is also formed side by side. Formed.
• FIG. 3 is an enlarged schematic view of a region A surrounded by a two-dot chain line in FIG. 2, and a silicon oxide film 5 as an element isolation film is not shown.
• a region surrounded by a two-dot chain line B is a region constituting one memory cell.
• the silicon nitride film 4 is formed along both sides of the impurity diffusion layer 6, and is arranged to face each other with the silicon oxide film 7 interposed therebetween.
• the gate electrode corresponding to the selected memory cell is set to a high potential, and both sides of the memory cell are set. This can be performed by giving a potential difference between the impurity diffusion layers 6.
• FIGS. 4A and 4B are schematic diagrams showing data write and read operations.
• writing data as shown in Fig. 4A, ground the source with the impurity diffusion layer 6a located on the right side, and apply a voltage of about 5 V using the impurity diffusion layer 6b located on the left side as the drain. I do.
• a high voltage about 10 V
• a hot electron is generated near the drain (impurity diffusion layer 6b), and electrons e are captured by the silicon nitride film 4b.
• the silicon nitride film 4b for capturing the electron e is formed only near the drain and not near the center of the channel width, the electron e is captured only in the region where the silicon nitride film 4b is formed. Will be. Therefore, capture of the electrons e in regions other than the region where the silicon nitride film 4b is formed can be suppressed, and the reliability of data writing can be improved.
• the impurity diffusion layer 6a When erasing data, the impurity diffusion layer 6a is opened, and a voltage of about 5 V is applied using the impurity diffusion layer 6b as a drain. Then, by applying a negative voltage (about 15 V) to the gate electrode, a hot hole is generated in the vicinity of the drain (impurity diffusion layer 6b) and holes are captured in the silicon nitride film 4b. At this time, since the silicon nitride film 4b for capturing holes is formed only near the drain and not near the center of the channel width, holes are captured only in the region where the silicon nitride film 4b is formed. And the trapped electron e can be reliably erased. Therefore, the reliability of data erasure can be improved.
• Data is written to and read from the silicon nitride film 4a by writing data to the above-described silicon nitride film 4b and applying a voltage in a direction opposite to that of reading. It can be carried out. This makes it possible to record 2-bit information on the silicon nitride films 4a and 4b.
• the silicon nitride film 4 having a high carrier trapping property is formed at both ends of the gate oxide film 7, the charge injection location is structurally reduced. As a result, the carriers can be reliably trapped only in the vicinity of the silicon nitride film 4.
• the gate electrode (polycrystalline silicon film 8, tungsten silicide film 9) is set to a high potential, and when a potential difference is applied between a pair of impurity diffusion layers 6, the gate electrode Electrons can be reliably trapped in the vicinity of the silicon nitride film 4 without being affected by variations in the potential of the electrodes or the potential difference between the pair of impurity diffusion layers 6, and the electrons are trapped in other regions. Can be suppressed. Also, at the time of erasing data, holes can be reliably trapped in the vicinity of the silicon nitride film 4, and the trapping of holes in other regions can be suppressed. This makes it possible to record and erase data stably and reliably by injecting the minimum amount of carriers.
• FIG. 5A to 5G are schematic sectional views showing a method for manufacturing a nonvolatile semiconductor memory according to the second embodiment in the order of steps.
• the planar configuration of the nonvolatile semiconductor memory according to the second embodiment is the same as the planar configuration of the nonvolatile semiconductor memory according to the first embodiment shown in FIGS.
• FIG. 5A to FIG. 5G are views showing a cross section of the memory cell in the order of the manufacturing process, focusing on one memory cell of the nonvolatile semiconductor memory.
• FIG. The cross section corresponding to the position along the alternate long and short dash line I_I 'of FIG. 5A to 5G, the same components as those in the first embodiment will be described with the same reference numerals as in FIG.
• a predetermined well is formed on the p-type silicon semiconductor substrate 1, and further, element isolation in the peripheral circuit area is performed (not shown).
• a silicon oxide film 2 is grown to a thickness of about 20 nm by a thermal oxidation method.
• a silicon nitride film 3 is deposited on the silicon oxide film 2 to a thickness of about 200 nm by a CVD method.
• the silicon nitride film 3 and the silicon oxide film 2 are left on the P-type silicon semiconductor substrate 1 in a portion to be the channel region of the memory cell, and the silicon nitride films 3 and The silicon oxide film 2 is removed.
• the p-type silicon semiconductor substrate 1 is immersed in a hydrofluoric acid (HF) solution, and the silicon oxide film 2 is etched by about 50 nm in the lateral width direction. By this etching, the width of the silicon oxide film 2 becomes smaller than the width of the silicon nitride film 3.
• annealing is performed in an ammonia (NH 3 ) gas atmosphere at a temperature of about 950 for a time of about 20 minutes to about 120 minutes, and silicon nitride is exposed on the exposed p-type silicon semiconductor substrate 1.
• the silicon nitride film 4 is formed over the lower layer of the pattern end of the film 3 and the pattern end of the silicon oxide film 2.
• the silicon oxide film 2 is etched in the lateral width direction, the silicon nitride film 4 is surely formed on the surface region of the P-type silicon semiconductor substrate 11 below the pattern end of the silicon nitride film 3. Can be formed.
• the lateral width of the silicon nitride film 4 under the silicon nitride film 3 can be adjusted with high accuracy.
• the formation of the silicon nitride film 4 may be performed by an ion implantation method.
• ions containing nitrogen (N 2 ) or the like are implanted under the conditions of an acceleration energy of about 30 keV and a dose of about l X 10 16 (ions Zcm 2 ).
• ions Zcm 2 ions containing nitrogen
• a film containing nitrogen is formed near the surface of the P-type silicon semiconductor substrate 1.
• the width of the silicon nitride film 4 formed below the pattern end of the silicon nitride film 3 can be controlled.
• ions are implanted into the surface region of the p-type silicon semiconductor substrate 1 using the silicon nitride film 3 as a mask.
• arsenic (As) which is an n-type impurity, is ion-implanted under the conditions of an acceleration energy of about 50 keV and a dose of about 1 ⁇ 10 16 (ions / cm 2 ).
• Impurities implanted by this ion implantation Becomes a pair of impurity diffusion layers 6 functioning as a source / drain in the surface region of the p-type silicon semiconductor substrate 1 on both sides of the silicon nitride film 3. Since the impurity diffusion layer 6 functions as a bit line, as shown in FIG. 2, a plurality of the impurity diffusion layers 6 are formed to extend in a predetermined direction, and are connected to each memory cell.
• the surface of the p-type silicon semiconductor substrate 1 is selectively oxidized by thermal oxidation.
• the oxidation resistance of the silicon nitride film 4 in the arsenic-implanted region is lost due to the ion implantation in the process of FIG. 5C, and thus the silicon nitride film is thermally oxidized in the process shown in FIG. 5D.
• the surface of the P-type silicon semiconductor substrate 1 other than the lower layer 3 is oxidized, and a silicon oxide film 5 as so-called LOCOS element isolation grows. Then, an element active region is defined on the P-type silicon semiconductor substrate 1 by the silicon oxide film 5.
• the p-type silicon semiconductor substrate 1 is immersed in a phosphoric acid solution at a temperature of about 150 to dissolve and remove the silicon nitride film 3.
• the silicon nitride film 4 is not removed by phosphoric acid and is not removed. To remain.
• the silicon oxide film 2 on the p-type silicon semiconductor substrate 1 is removed by immersing it in a hydrofluoric acid (HF) solution. Thereafter, thermal oxidation is performed to form a silicon oxide film 7 as a gate insulating film with a thickness of about 15 nm. At this time, in the portion where the silicon nitride film 4 is formed, the oxidation speed due to thermal oxidation is reduced by the silicon nitride film 4, so that the silicon oxide film 7 at this position is formed thinner than other regions. You.
• HF hydrofluoric acid
• the silicon nitride film 4 is covered with the silicon oxide film 7, and on the p-type silicon semiconductor substrate 1 near each of the pair of impurity diffusion layers 6, the silicon nitride film 4 is included in the silicon oxide film 7.
• a gate insulating film having a structure including is formed.
• the silicon nitride film 4 Since the silicon nitride film 4 has a higher carrier trap characteristic than the silicon oxide film 7, as in the first embodiment, the silicon nitride film 4 functions as a part of the silicon oxide film 7 functioning as a gate insulating film. By including it, the carrier trap characteristic at this portion can be improved as compared with other regions of the silicon oxide film 7. Moreover, since the silicon oxide film 7 is formed thicker in the region where the silicon nitride film 4 is not formed than in the region where the silicon nitride film 4 is formed, a voltage is applied to the gate electrode formed above. When the voltage is applied, the carrier trap to the gate oxide film 7 is suppressed. Therefore, the carrier trap characteristic at the end of the channel region can be improved as compared with the vicinity of the center of the channel region.
• a polycrystalline silicon film 8 doped with phosphorus (P) is formed on the entire surface of the p-type silicon semiconductor substrate 1 by a CVD method.
• a tungsten silicide film 9 is deposited to a thickness of about 100 nm.
• the polycrystalline silicon film 8 and the tungsten silicide film 9 are patterned into the shape of a gate electrode by photolithography and subsequent dry etching. As a result, a gate electrode having a polysilicon structure composed of the polycrystalline silicon film 8 and the tungsten silicide film 9 is formed.
• the source / drain diffusion layer impurity diffusion layer 6
• gate insulating film silicon oxide film 7, silicon nitride film 4
• gate electrode polycrystalline silicon film 8, tungsten
• a general wiring layer forming step is performed to complete the nonvolatile semiconductor memory according to the present embodiment. That is, an interlayer insulating film (silicon oxide film or the like) is deposited by a CVD method, and the gate electrode composed of the polycrystalline silicon film 8 and the tungsten silicide film 9 is covered. Then, by photolithography and subsequent dry etching, Contact holes are formed in the interlayer insulating film. Then, for example, an aluminum film is deposited as a wiring layer on the interlayer insulating film by a sputtering method to fill a contact hole, and the aluminum film is patterned into a predetermined shape by photolithography and subsequent dry etching. After that, a protective film is formed so as to cover the aluminum film.
• an interlayer insulating film silicon oxide film or the like
• the silicon nitride films 4 having high carrier trap characteristics are formed at both ends of the gate oxide film 7. Therefore, the location of charge injection is structurally limited, and the carrier can be reliably trapped only in the vicinity of the silicon nitride film 4.
• the silicon nitride film 4 when forming the silicon nitride film 4, the silicon nitride film 4 Since a predetermined amount of both ends of the silicon oxide film 2 has been removed in advance so as to be narrower than the width of 3, the silicon nitride film 4 can be surely formed in the removed region. By controlling the removal amount of the silicon oxide film 2, the width of the silicon nitride film 4 below the gate electrode can be adjusted with high accuracy.
• FIGS. 6A to 6G are schematic cross-sectional views illustrating a method for manufacturing a nonvolatile semiconductor memory according to the third embodiment in the order of steps.
• the planar configuration of the nonvolatile semiconductor memory according to the second embodiment is the same as the planar configuration of the nonvolatile semiconductor memory according to the first embodiment shown in FIGS.
• FIG. 6A to FIG. 6G are diagrams illustrating a cross section of the memory cell in the order of the manufacturing process, focusing on one memory cell of the nonvolatile semiconductor memory.
• FIG. The cross section corresponding to the position along the alternate long and short dash line I-I 'of FIG. 6A to 6G, the same components as those in the first embodiment will be described with the same reference numerals as in FIGS. 1A to 1G.
• a predetermined well is formed on the p-type silicon semiconductor substrate 1, and further, element isolation in the peripheral circuit area is performed (not shown).
• a silicon oxide film 2 is grown to a thickness of about 20 nm by a thermal oxidation method, and a silicon nitride film 3 is formed on the silicon oxide film 2 by a CVD method. Is deposited to a thickness of about 200 nm.
• the silicon nitride film 3 and the silicon oxide film 2 are left on the p-type silicon semiconductor substrate 1 in the region to be the channel region of the memory cell, and the silicon nitride film 3 in other regions is left. Then, the silicon oxide film 2 is removed.
• an annealing treatment was performed in an ammonia (NH 3 ) gas atmosphere at a temperature of about 950 for a time of about 20 minutes to about 120 minutes, and the exposed P was exposed.
• a silicon nitride film 4 is formed over a predetermined range of the lower portion of the pattern end portion of the silicon nitride film 3 from above the type silicon semiconductor substrate 1.
• silicon and ammonia gas directly react.
• a silicon nitride film 4 is formed.
• a silicon nitride film 4 is formed by a reaction with ammonia diffused in the silicon oxide film 2.
• the width of the silicon nitride film 4 formed at the pattern end of the silicon nitride film 3 can be controlled by adjusting the film formation conditions of the silicon nitride film 4.
• the formation of the silicon nitride film 4 may be performed by an ion implantation method.
• ions containing nitrogen (N 2 ) or the like are implanted under the conditions of an acceleration energy of about 30 keV and a dose of about 1 ⁇ 10 16 (ions / cm 2 ).
• a film containing nitrogen is formed near the surface of the P-type silicon semiconductor substrate 1.
• the angle of ion implantation with respect to the p-type silicon semiconductor substrate 1 the width of the silicon nitride film 4 formed below the pattern end of the silicon nitride film 3 can be controlled.
• ions are implanted into the surface region of the p-type silicon semiconductor substrate 1 using the silicon nitride film 3 as a mask.
• arsenic (As) which is an n-type impurity
• As arsenic
• the impurities implanted by this ion implantation become a pair of impurity diffusion layers 6 functioning as a source / drain in the surface region of the p-type silicon semiconductor substrate 1 on both sides of the silicon nitride film 3. Since the impurity diffusion layer 6 functions as a bit line, as shown in FIG. 2, a plurality of impurity diffusion layers 6 are formed so as to extend in a predetermined direction, and are connected to each memory cell.
• the surface of the P-type silicon semiconductor substrate 1 is selectively oxidized by thermal oxidation.
• the silicon nitride film is thermally oxidized in the step of FIG. 6D.
• the surface of the p-type silicon semiconductor substrate 1 other than the lower layer of the film 3 is oxidized, and a silicon oxide film 5 as so-called LO COS element separation grows. Then, an element active region is defined on the p-type silicon semiconductor substrate 1 by the silicon oxide film 5.
• the p-type silicon semiconductor substrate 1 is immersed in a phosphoric acid solution at a temperature of about 150 to dissolve and remove the silicon nitride film 3.
• silicon Since the upper surface of the silicon nitride film 4 formed under the nitride film 3 is covered with the silicon oxide film 2 and protected, it remains under the silicon oxide film 2 without being removed by phosphoric acid.
• the silicon oxide film 2 on the p-type silicon semiconductor substrate 1 is removed by immersion in a hydrofluoric acid (HF) solution. Thereafter, thermal oxidation is performed to form a silicon oxide film 7 as a gate insulating film with a thickness of about 15 nm. At this time, in the portion where the silicon nitride film 4 is formed, the oxidation speed due to thermal oxidation is reduced by the silicon nitride film 4, so that the silicon oxide film 7 at this position is formed thinner than other regions. You.
• HF hydrofluoric acid
• the silicon nitride film 4 is covered with the silicon oxide film 7, and on the p-type silicon semiconductor substrate 1 near each of the pair of impurity diffusion layers 6, the silicon nitride film 4 is included in the silicon oxide film 7.
• a gate insulating film having a structure including is formed.
• the silicon nitride film 4 Since the silicon nitride film 4 has a higher carrier trapping characteristic than the silicon oxide film 7, as in the first embodiment, the silicon nitride film 4 functions as a part of the silicon oxide film 7 functioning as a gate insulating film. By including it, the carrier trap characteristic at this portion can be improved as compared with other regions of silicon oxide film 7. Moreover, since the silicon oxide film 7 is formed thicker in the region where the silicon nitride film 4 is not formed than in the region where the silicon nitride film 4 is formed, a voltage is applied to the gate electrode formed above. In this case, carrier traps to gate oxide film 7 are suppressed. Therefore, the carrier trap characteristic at the end of the channel region can be improved as compared with the vicinity of the center of the channel region.
• a silicon nitride film 10 is formed on the silicon oxide film 7 and the silicon oxide film 5 to a thickness of about 6 nm by a CVD method.
• a trap film having a stacked structure of the silicon oxide film 7, the silicon nitride film 4, the silicon oxide film 7, and the silicon nitride film 10 is formed near the impurity diffusion layer 6.
• the polycrystalline silicon film 8 doped with phosphorus (P) is A tungsten silicide film 9 having a thickness of about 100 nm is formed on the polycrystalline silicon film 8 by a CVD method. Thereafter, the polycrystalline silicon film 8 and the tungsten silicide film 9 are patterned into a gate electrode shape by photolithography and subsequent dry etching. Thus, a gate electrode having a polyside structure including the polycrystalline silicon film 8 and the tungsten silicide film 9 is formed.
• the source / drain diffusion layers impurity diffusion layer 6
• gate insulating film silicon oxide film 7, silicon nitride film 4, silicon nitride film 10
• gate silicon oxide film 7, silicon nitride film 4, silicon nitride film 10
• the formation of the electrodes (polycrystalline silicon film 8, tungsten silicide film 9) is completed.
• a general wiring layer forming step is performed to complete the nonvolatile semiconductor memory according to the present embodiment. That is, an interlayer insulating film (silicon oxide film or the like) is deposited by the CVD method, and the gate electrode composed of the polycrystalline silicon film 8 and the tungsten silicide film 9 is covered, and then photolithography and subsequent dry etching are performed. Then, a contact hole is formed in the interlayer insulating film. Then, for example, an aluminum film is deposited as a wiring layer on the interlayer insulating film by a sputtering method to fill the contact holes, and the aluminum film is patterned into a predetermined shape by photolithography and subsequent dry etching. After that, a protective film is formed so as to cover the aluminum film.
• an interlayer insulating film silicon oxide film or the like
• the silicon nitride film 4 having high carrier trap characteristics is formed at both ends of the gate oxide film 7.
• the location where the charge is injected is limited structurally, and the carrier can be reliably trapped only in the vicinity of the silicon nitride film 4.
• the silicon nitride film 10 by forming the silicon nitride film 10 on the silicon nitride film 4 so as to overlap with the silicon nitride film 4, it is possible to further improve the carrier trap characteristic at the end of the gate oxide film 7. Data recording and erasing can be performed more reliably.
• FIG. 4 is a schematic cross-sectional view illustrating a method for manufacturing the nonvolatile semiconductor memory according to the embodiment in the order of steps.
• the planar configuration of the nonvolatile semiconductor memory according to the fourth embodiment is the same as the planar configuration of the nonvolatile semiconductor memory according to the first embodiment shown in FIGS.
• FIGS. 7A to 7F show two memory cells of the non-volatile semiconductor memory, and show the cross sections of the memory cells in the order of the manufacturing process. The cross section corresponding to the position along is shown.
• a silicon nitride film 12 is formed on a main surface of a p-type silicon semiconductor substrate 11 (specific resistance 1 to 12 ⁇ cm, containing boron (B)) by a CVD method. It is formed to a thickness of about 150 nm to 300 nm.
• the silicon nitride film 12 on the region where the bit line diffusion layer is to be formed is selectively removed by photolithography and subsequent dry etching. Then, ion implantation is performed using the silicon nitride film 12 as a mask. Specifically, arsenic (A s) of an acceleration energy of 6 0 ke V ⁇ l OO ke V about an n-type impurity, the dose 1 X 1 0 15 ⁇ : 1 X 1 0 16 (ions / cm 2) Ion implantation is performed under approximately the same conditions to form a high-concentration impurity diffusion layer 13 serving as a bit line diffusion layer.
• a s arsenic
• a silicon oxide film 14 is formed to a thickness of about 300 nm to 500 nm by the CVD method, and the bit line is diffused by the CMP (chemical mechanical polishing) method or dry etching.
• the silicon oxide film 14 is left only on the layer (impurity diffusion layer 13), and the silicon oxide film 14 in other regions is removed. Thereby, the surface of silicon oxide film 14 on impurity diffusion layer 13 is substantially flush with the surface of silicon nitride film 12.
• the impurity diffusion layer 13 and the silicon oxide film 14 can be formed in a self-alignment manner by one photolithography.
• the silicon nitride film 12 is removed by wet etching using phosphoric acid or the like, exposing the surface of the underlying p-type silicon semiconductor substrate 11.
• the P-type silicon semiconductor substrate 11 is subjected to thermal oxidation to remove the silicon nitride film 12, and the surface of the p-type silicon semiconductor substrate 11 exposed as a result of the silicon oxide film having a thickness of about 10 nm to 30 nm is exposed.
• a film 15 is formed.
• a silicon nitride film 16 serving as a carrier trap film is formed on the silicon oxide film 14 and the silicon oxide film 15 to a thickness of about 10 nm to 20 nm by the CVD method.
• a silicon oxide film 17 having a thickness of about 300 nm to 500 nm is formed by the CVD method, and only the side wall of the silicon oxide film 14 is formed by dry etching. Remove to remain. As a result, a sidewall composed of the silicon oxide film 17 and the silicon nitride film 16 is formed on the side wall of the silicon oxide film 14. Further, the silicon nitride film 16 and the silicon oxide film 15 between the side walls are removed by this dry etching, and the surface of the p-type silicon semiconductor substrate 11 is exposed.
• the surface of the P-type silicon semiconductor substrate 11 is subjected to thermal oxidation under the conditions of a temperature of about 800 to 900 and a time of about 30 to 90 minutes, A silicon oxide film 18 is formed on the exposed surface of the P-type silicon semiconductor substrate 11. Thereafter, the silicon oxide film 17 is removed by wet etching, and the surface of the silicon nitride film 16 is oxidized by thermal oxidation to form a silicon oxide film 19.
• impurities boron, phosphorus
• the etching rates of the silicon oxide film 17 and the silicon oxide film 14 can be made different.
• the silicon oxide film 17 It is possible to remove the silicon oxide film 17 while keeping the removal amount of the silicon oxide film 14 at a minimum.
• the silicon oxide film 18 is an oxide film formed by thermal oxidation, the etching rate is different from that of the silicon oxide film 17, and the removal amount is minimized.
• another insulating film having an etching rate different from that of the silicon oxide films 14 and 18 may be used.
• the silicon nitride film 16 has the lower layer covered with the silicon oxide film 15 and the upper layer covered with the silicon oxide film 19.
• a gate insulating film is formed.
• the silicon nitride film 16 is covered with the silicon oxide film 17, so that the thickness of the silicon oxide film 18 can be controlled independently. It is possible.
• thermal oxidation may be performed to form the silicon oxide film 18 and the silicon oxide film 19 at the same time.
• the oxidation rate due to thermal oxidation is reduced near the silicon nitride film 16, so that The silicon oxide film 19 is formed thinner than the silicon oxide film 18.
• the polycrystalline silicon film 20 containing about 2 ⁇ 10 2 ° to 6 ⁇ 10 20 (atms / cm 3 ) of phosphorus (P) is deposited by the CVD method. 1 0 0 ⁇ ⁇ ! It is formed to a thickness of about 200 nm, and is patterned into a word line shape by photolithography and subsequent dry etching.
• the silicon nitride films 15 having high carrier trap characteristics are formed on both ends of the gate oxide film 18.
• the location of charge injection is structurally limited, and the carrier can be reliably trapped only in the vicinity of the silicon nitride film 15.
• the impurity diffusion layer 13 and the silicon oxide film 14 on the impurity diffusion layer 13 can be formed in a single photolithographic manner in a self-aligned manner.
• a gate insulating film composed of the silicon oxide films 15, 18, 19 and the silicon nitride film 16 can be formed with high precision between two adjacent impurity diffusion layers 13.
• the silicon nitride film 16 is covered with the silicon oxide film 17 as a side wall, so that the thickness of the silicon oxide film 18 can be independently formed with high precision. It is possible to do.
• the present invention provides a pair of impurity diffusion layers formed in a surface region of a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the pair of impurity diffusion layers via a gate insulating film.
• a semiconductor memory device configured to capture a carrier in a gate insulating film by applying a predetermined voltage to a gate electrode, and to be close to each of a pair of impurity diffusion layers of the gate insulating film. Since the carrier trap characteristic at the position where the carrier is trapped is formed higher than in other regions, it is possible to record and hold the 2-bit information stably and reliably by changing the carrier injection position. Therefore, in a nonvolatile semiconductor memory in which 2-bit information can be recorded in one memory cell, occurrence of a writing or erasing failure can be suppressed, and a semiconductor memory device with improved reliability and a method of manufacturing the same can be suppressed. Can be provided.

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