Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
  • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/687—Floating-gate IGFETs having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels

Definitions

• the present invention relates to a novel nonvolatile memory capable of recording multi-bit information in one memory cell using a non-conductive charge trap gate.
• Non-volatile memories using semiconductors are widely used as information recording media because they can retain information even when the power is turned off and can read at high speed. In recent years, it has been used for portable information terminals and as a recording medium for digital cameras and digital music of MP3 data.
• Non-volatile memories such as flash memories, which are currently in widespread use, have a structure in which a conductive floating gate and a control gate are provided on a channel region between a source region and a drain region.
• a non-volatile memory is configured such that a floating gate is buried in a gate insulating film, and stores one bit of information by injecting a charge (charge) into the floating gate.
• charge charge
• Non-volatile memory In addition to the above-mentioned popular non-volatile memory, a non-conductive charge trap gate is provided instead of a floating gate, and charges are trapped on the source and drain sides to store 2-bit information.
• Non-volatile memories have been proposed. For example, a non-volatile memory according to PCT application, WO99 / 07000, "Two Bit Non-Volatile Electrically Erasable Ana Programmable Semiconductor Memory Cell Utilizing Asy Image Etrical Charge Trapping" is described. Is injected locally because the trap gate is non-conductive The probability of electron loss is low, and reliability can be increased.
• FIG. 1 is a diagram showing a configuration of the conventional 2-bit nonvolatile memory.
• FIG. 1 (1) is a cross-sectional view
• FIG. 1 (2) is an equivalent circuit diagram.
• Source and drain regions SD 1 and SD 2 are formed on the surface of the silicon substrate 1, and a trap gate TG formed of a silicon nitride film and the like and a conductive material control gate CG are formed on the channel region.
• the trap gate TG is embedded in an insulating film 2 such as a silicon oxide film, and has a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure as a whole.
• MONOS Metal-Oxide-Nitride-Oxide-Semiconductor
• the characteristic configuration of this non-volatile memory is made of a non-conductive material such as a dielectric material such as a trap gate TG.
• a non-conductive material such as a dielectric material such as a trap gate TG.
• the charge cannot move in the trap gate. Therefore, it is possible to distinguish between the case where the charge is injected near the first source-drain region SD1 and the case where the charge is injected near the second source / drain region SD2, Data can be recorded.
• FIG. 1 (2) is an equivalent circuit diagram of the above-mentioned 2-bit nonvolatile memory. Since the trap gate TG is non-conductive, the first trap gate region TSD 1 near the first source / drain region SD 1 and the second trap gate region TSD near the second source / drain region SD 2 This is equivalent to a configuration in which separate MOS transistors are formed in the trap gate region T SD 2 of FIG. In a read or program (write) operation described later, the first and second source / drain regions SD 1 and SD 2 are used as one of a source region and a drain region. These are referred to as a first source 'drain region SD 1 and a second source' drain region SD 2, respectively.
• FIG. 2 is a diagram for explaining programming, erasing, and reading of a conventional 2-bit nonvolatile memory.
• the voltage applied to the first source 'drain region SD1 is V (SD1)
• the voltage applied to the second source' drain region SD2 is V (SD2)
• the voltage applied to the gate is Vg.
• Vg —5V to the control gate CG and 5V to the first or second source drain region SD1 or SD2, or both, to cause FN tunneling (Fowler-Nordheim tunnel) phenomenon.
• the charge in the trap gate TG is neutralized by injecting hot holes generated near the source / drain regions SD1 and SD2 into the trap gate TG.
• Vg 3V
• V (SD1) 1.6V
• V (SD2) 0V
• Vg 3V
• V (SD1) 0V
• V (SD2) 1.6V
• the first and second source and drain regions are set. If the voltage applied state is reversed from that in Fig. 2 (3), even if electrons exist in the second trap gate region T SD2, the channel is pinched and the M ⁇ S transistor is turned off. In the same state, channel current flows. Therefore, in such a voltage applied state, whether or not electrons are accumulated in the first trap gate region T SD1 near the first source / drain region SD1 is determined by the second trap gate region T SD2. Can be detected regardless of the presence of electrons.
• FIG. 3 is a diagram showing a state in which 2-bit information of the above-mentioned nonvolatile memory is recorded.
• black circles indicate electrons.
• FIG. Data 10 when electrons are captured in the trap gate region T SD1 of 1.
• the two-bit nonvolatile memory described above can store two bits in one memory cell, which is advantageous for large capacity, but the demand for large capacity required for recent nonvolatile memory is , Even more severe. That is, when it is required to record from still image data to music data and further to moving image data, it is desired that more bits can be recorded in one memory cell.
• an object of the present invention is to provide a novel nonvolatile memory that can record 3-bit information in one memory cell.
• one aspect of the present invention is to provide a semiconductor device having a first and second source and drain regions, a non-conductive layer on a channel region therebetween, and an insulating film.
• a nonvolatile memory having a trap gate and a conductive floating gate.
• the nonvolatile memory according to the present invention includes a hot electron generated in the vicinity of the first or second source / drain region by applying a voltage between the first and second source / drain regions. The first or second state that is locally captured in the first or second trap gate region in the vicinity thereof, and a voltage is applied between the control gate and the channel region, and electrons are applied to the entire trap gate. (Or a charge).
• One-bit information is recorded depending on whether or not the third state is set, and two-bit information is recorded depending on whether or not the first and second states are set. Therefore, a total of three bits of information are recorded in one memory cell.
• another aspect of the present invention is a nonvolatile memory for recording multi-bit information
• First and second source / drain regions formed on the surface of a semiconductor substrate and a first insulating layer, a non-conductive trap gate, a second insulating layer, and a control formed on a channel region therebetween. Having a gate,
• It has a first state in which electric charges are locally trapped in the trap gate and a second state in which electric charges are injected into the entire trap gate.
• different data can be recorded between the case where electrons are injected into the entire non-conductive trap gate and the case where electrons are locally injected. More data can be recorded by setting multiple injection points locally.
• a predetermined voltage is applied between the first and second source and drain regions to generate a hot electric element generated in the channel region.
• the second state is written by applying a predetermined voltage between the semiconductor substrate and the control gate, and the charge is tunnel-injected.
• the semiconductor substrate and the control gate The erase operation is performed by applying a predetermined erase voltage to the substrate and extracting charges existing in the entire trap gate or in a local region of the trap gate.
• a preferred embodiment of the above invention has a first read voltage, a second read voltage, and a third read voltage, which are sequentially different in voltage, wherein the second read voltage is applied to the control gate.
• the first state or the third state is read, and the first or third read voltage is applied to the control gate to read the first state.
• still another aspect of the present invention relates to a nonvolatile memory for recording multi-bit information
• First and second source and drain regions formed on the surface of a semiconductor substrate, a first insulating layer formed on a channel region therebetween, a non-conductive trap gate, a second insulating layer, and a control. Having a gate,
• the second trap gate region near the drain region has a second state in which charges are trapped and a third state in which charges are injected into the entire trap gate.
• FIG. 1 is a diagram showing a configuration of a conventional 2-bit nonvolatile memory.
• FIG. 2 is a diagram for explaining programming, erasing, and reading of a conventional 2-bit nonvolatile memory.
• FIG. 3 is a diagram showing a state where 2-bit information of a conventional nonvolatile memory is recorded.
• FIG. 4 is a diagram showing a trap state of electrons corresponding to 3-bit information of the nonvolatile memory in the present embodiment.
• FIG. 5 shows a threshold value corresponding to 3-bit information of the nonvolatile memory in the present embodiment. It is a figure showing a state of a value voltage.
• FIG. 6 is a flowchart of a first read operation of the nonvolatile memory in the present embodiment.
• FIG. 7 is a circuit diagram showing an example of a memory cell array in the present embodiment.
• FIG. 8 is a flowchart of a second read operation of the nonvolatile memory according to the present embodiment.
• FIG. 9 is a circuit diagram of a sense amplifier circuit used in the second read operation.
• FIG. 10 is a flowchart for explaining the write (program) operation of the nonvolatile memory in the present embodiment.
• FIG. 11 is a flowchart illustrating a write (program) operation of the nonvolatile memory according to the present embodiment.
• FIG. 12 is a diagram showing an erasing operation of the nonvolatile memory in the present embodiment.
• the nonvolatile memory of the present embodiment includes N-type first and second source / drain regions SD 1 and SD 2 on the surface of a p-type semiconductor substrate 1. Having. On the channel region between them, a silicon oxide film 2, for example, a non-conductive trap gate TG made of a silicon nitride film, a silicon oxide film 2, and a conductive control gate CG are formed in this order. You. The trap gate T G is embedded in the silicon oxide film 2 and is in an electrically floating state.
• the trap gate TG is preferably made of a non-conductive material, and an insulating material such as a silicon nitride film is used.
• the nonvolatile memory of the present embodiment has a state of whether or not electrons are trapped locally in the trap gate TG in addition to a state of whether or not electrons are locally trapped in the trap gate TG. . That is, as shown in the conventional example, the region of the trap gate TG near the first and second source / drain regions SD 1 and SD 2 2-bit information is recorded by trapping a hot electron locally in the area. Further, in the present embodiment, by applying an electric field between the control gate CG and the semiconductor substrate 1 to the entire trap gate TG and tunnel-injecting electrons, the electrons are trapped in the entire trap gate. Record one more bit of information. FIG.
• FIG. 4 is a diagram showing a trap state of electrons corresponding to 3-bit information of the nonvolatile memory in the present embodiment.
• FIG. 5 is also a diagram showing a state of a threshold voltage corresponding to 3-bit information of the nonvolatile memory in the present embodiment.
• FIG. 4 shows a state in which electrons are trapped in the entire TAL L in the trap gate TG, and a local region near the first and second source / drain regions SD 1 and SD 2 of the trap gate TG. , And a state where electrons are trapped in the first and second trap gate regions TSD 1 and TSD 2.
• FIG. 5 shows that the channel region of the memory cell is divided into a portion corresponding to the first and second trap gate regions TSD 1 and TSD 2 and a portion corresponding to the central region TCN of the trap gate therebetween.
• the threshold voltage states are shown separately.
• the voltages V (0), V (1) and V (2) shown in FIG. 5 are the first, second and third read voltages applied to the control gate CG at the time of reading. Is shown.
• data 0 corresponds to a state in which a read voltage is applied and no current flows through the channel (non-conduction)
• data 1 corresponds to a state in which channel current flows (conduction).
• the non-volatile memory of the present embodiment stores 3-bit information.
• the information of the most significant bit is stored in the first trap gate depending on whether or not electrons are captured by the entire trap gate TG.
• the information of the second bit is determined by whether or not electrons are captured in the region TSD1
• the information of the third bit is determined by whether or not electrons are captured in the second trap gate region TSD2.
• the information of the least significant bit is stored.
• the threshold voltage of each of the three regions TSD1, TSD2, and TCN (the central region of the trap gate) is low. That is, the state is lower than the voltage V (0).
• the above three states can be read by using the second read voltage V (1) and the first read voltage V (0), as described later.
• the data 01 1, 0 10, 001, 000 are all states in which electrons are trapped in the entire trap gate TG, and the first and second trap gate regions T SD 1, T SD are respectively similar to the above.
• the first and second trap gate regions T SD 1, T SD are respectively similar to the above.
• the threshold voltage is higher than the second read voltage V (1) in all the regions TSD1, TSD2, and TCN. Then, the region TSDl, TSD2 force; is divided into higher and lower than the third read voltage V (2). That is, Fowler Nordheim. Tunnel phenomenon (hereinafter FN When electrons are injected into the entire trap gate TG due to the tunnel phenomenon, the threshold voltage of the memory cell trap gate alone becomes higher than the second read voltage V (1). Further, when electrons are locally tunnel-injected into the first or second trap gate regions TSD 1 and TSD 2, the threshold voltage of each corresponding region becomes higher than the third read voltage V (2). Become.
• the above four states can be read by the second read voltage V (1) and the third read voltage V (2).
• FIG. 6 is a flowchart of a first read operation of the nonvolatile memory in the present embodiment.
• the first, second, and third read voltages V (0), V (1), and V (2) are appropriately applied to the control gate CG, and the first and second source / drain regions are applied.
• the voltages V (SD1) and V (SD2) are appropriately applied so that a rightward or leftward electric field is applied between the two regions, and reading is performed.
• Vtttcenter the center threshold voltage
• Vt # sd2 the threshold voltage near the second trap gate region TSD2
• the stored data is found to be 101 ⁇ 111. If the cell trap gate is non-conductive (read data 0), the threshold voltage at the center is considered to be Vt # center> V (0) or Vt # sd2> V (0), and other data is stored. Is detected.
• step S2 the applied voltage to the control gate remains at Vg2V (0), and the applied voltages V (SD1) and V (SD2) of the first and second source / drain regions are maintained.
• conduction is performed in step S1 and data 1 is read, and conduction is also performed in step S2.
• the threshold voltages are Vt # center ⁇ V (0) and Vt # sd2 ⁇ 0, and the threshold voltage near the first trap gate region TSD1 (hereinafter abbreviated as Vtlisdl) Since it is smaller than the first read voltage V (0), the data is specified as 1 1 1.
• the threshold voltage is Vtttcenter ⁇ V (0), Vt # sd2 ⁇ V (0) And since Vt # sdl> V (0), the data is identified as 101.
• step S1 if the data is read out in step S1 because of non-conduction and the data is read out in step S2, the threshold voltage is Vt # center ⁇ V (0), Vt # sd2 > V (0) N Vt # sdl ⁇ V (0), so the data is identified as 110. If data is read out in step S1 because of non-conduction, and data 0 is read out in step S2,
• Vg V (2)
• V (SD1) 1.6V
• V (SD2) 0V.
• the threshold voltage is Vt # sd2> V (2), so that the stored data is 010 or 000. If the cell transistor conducts and the read data is 1, the threshold voltage is Vt # sd2 and V (2), so the stored data can be determined to be 00 1, 100, or 01 1. .
• the threshold voltage is Vt # sd2> V (2) and Vtilsdl ⁇ V (2), so the data is specified as 000.
• step S3 when data is read out in step S3 and data 0 is read out and in step S4 data is read out and data 1 is read, the threshold voltage is Vt # sd2> V (2) and Vt # sdl ⁇ Since it is V (2), the data is identified as 010.
• Vt # sd2 V (2) and Vt # sdl> V (2) The data is identified as 001. If data is read by conducting in step S3, and data 1 is read in step S4, Vt # center ⁇ V (0), Vtttsd2> V (0) and Vt # There are two states: sdl> V (0), Vt # center> V (0), Vt # sd2 ⁇ V (2) and Vt # sdl ⁇ V (2). That is, the data is 100 or 0 1 1.
• the voltages V (SD1) and V (SD2) applied to the first and second source / drain regions may have an opposite relationship.
• the threshold voltage is Vt # center ⁇ V (l). Specified as 100.
• the data is specified as 01 1 because the threshold voltage is Vt # center> V (l).
• step S5 the voltage Vg to the control gate CG is set to the second read voltage V (l), and it is checked whether or not conduction occurs, so that the most significant bit is 0 or 1 Can be separated. Then, by executing the above-mentioned steps S l and S 2, data 11 1 to 100 can be detected. Alternatively, by executing the above steps S3 and S4, data 011 to 000 can be detected.
• FIG. 7 is a circuit diagram showing an example of a memory cell array according to the present embodiment.
• FIG. 7 shows four bit lines BL0 to BL3 and two word lines WL0 and WL1, and memory cells MC00 to MC13 are arranged at their intersections.
• the first and second source / drain regions of each memory cell are connected to a bit line, and the control gate is connected to a gate line.
• the read line is selected by the read decoder WDEC, and the bit line is passed through the transistors selected by the column select signals CL0 to CL3 selected by the column decoder. Connected to.
• the data read by the circuits 10 A and 10 B is supplied to the read circuit 12, and as a result of the above read sequence, 3-bit data is output to the output terminal DQ. Output to 0 to DQ2.
• a read voltage can be applied to the first and second source and drain regions of the memory cell by appropriately combining the conduction of the column gate transistors QC L0 to QC L3 provided above and below.
• data 1 and 0 corresponding to the conduction and non-conduction of the memory cell can be read.
• FIG. 8 is a flowchart of a first read operation of the nonvolatile memory according to the present embodiment.
• FIG. 9 is a circuit diagram of the sense amplifier circuit in that case. Steps S1 to S5 in FIG. 8 correspond to steps S1 to S5 in FIG.
• the most significant digit (whether or not electrons are trapped in the entire trap gate) and the second digit (the first digit) Whether or not electrons are trapped in the trap gate region) and the third digit (whether or not electrons are trapped in the second trap gate region) are 3 * n, 3 * n + l, 3 *
• a read operation is performed by assigning an address at address n + 2 (where n is an integer greater than or equal to 0.) Therefore, in Fig. 8, A indicates the above address.
• a pre-sense circuit composed of transistors P ll and N 10 is connected to a bit line BL via a column gate QC L, and is connected to the main amplifier via an inverter 15.
• the latch circuit 17 latches the most significant digit data indicating whether or not electrons are trapped in the entire trap gate, and outputs the data through the output inverters P13, P14, N15, and N16. Output to terminal OUT.
• the data of the second and third digits indicating whether or not electrons are trapped in the first or second trap gate region is latched by the latch circuit 26, and the output converters P17, P18 , N19, N20 to the output terminal OUT.
• Control signal SNS2 High Therefore, the trap gates PI 8 and N 19 become conductive, the CM ⁇ S inverter is activated, and depending on whether node M is high or low, the output OUT is high (data 1) or low (data 1). 0) is output.
• V (SD2) is set to 1.6V (S4).
• the data obtained in the above steps S1 and S4 is the data of the second digit.
• the data read in the above steps S2 and S4 is the 13th digit data.
• data corresponding to three addresses for one memory cell could be serially read. After that, it proceeds to the next memory cell and repeats the same operation until it reaches the final address.
• the read operation may be stopped in the middle, or sequential read from an arbitrary address instead of address 0 is possible.
• FIGS. 10 and 11 are flow charts for explaining the write (program) operation of the nonvolatile memory in the present embodiment.
• FIGS. 10 and 11 show that the writing steps S 1, S 2, and S 3 are sequentially performed from the erased state P 0 in which no electrons are trapped in the trap gate TG, so that the eight written states P 30 of the 3-bit information can be obtained.
• 9 shows a flowchart leading to P37. Therefore, by combining FIGS. 10 and 11 in the horizontal direction, the entire writing (program) process is shown.
• FIGS. 10 and 11 show a writing step for enabling writing to such a plurality of memory cells.
• the memory for writing data 000, 00 1, 010, 01 1 Electrons are injected into the cell.
• Vg 10V
• V (SD1) 6V
• V (SD2) 0V
• a channel 'hot' electron generated by avalanche breakdown is locally injected into the trap gate region T SD1 near the first source / drain region SD1.
• Vg as shown in the state P21.
• step S2 If the verification fails, the process S1 is repeated until the verification passes. If the above verification passes, the threshold voltage becomes higher than the second read voltage V (1).
• step S3 If the verification fails, the process S2 is repeated until the verification passes. If the above verification passes, the threshold voltage of the channel region corresponding to the first trap gate region TSD1 becomes higher than the third read voltage V (2).
• the channel hot electron generated by avalanche breakdown is injected into the second trap gate region TSD2.
• V g V (2)
• V (SD1) 1.6V
• V (SD2) performs writing base Rifai as 0V. If the verify passes, the write operation is completed. If the verify fails, step S3 is repeated until the verify passes. If the above verification passes, the threshold voltage corresponding to the second trap gate region T SD2 becomes higher than the third read voltage V (2).
• the erasing operation of the nonvolatile memory in the present embodiment is performed by extracting electrons in the trap gate TG to the channel region side by utilizing the FN tunnel phenomenon. Either when electrons are injected into the entire trap gate TG or when electrons are trapped in the first and second trap gate regions, all can be similarly erased.
• FIG. 12 is a diagram showing an erasing operation of the nonvolatile memory in the present embodiment.
• FIG. 12 shows four types of erase operations.
• the electrons trapped in the trap gate TG pass through the gate oxide film below the trap gate TG by a tunnel phenomenon and are extracted to the channel region.
• Vg 0 V for the control gate CG
• V (BULK) 15 V for the channel region
• 15 V for the first and second source / drain regions 15 V for the first and second source / drain regions.
• a state in which a non-conductive trap gate is buried in a gate insulating film to inject a charge into the entire trap gate and a state in which a charge is locally injected into a part of the trap gate.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Non-Volatile Memory (AREA)
• Read Only Memory (AREA)
• Semiconductor Memories (AREA)

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• 1999
  • 1999-08-10 JP JP22691399A patent/JP3912937B2/ja not_active Expired - Fee Related
• 2000
  • 2000-02-28 KR KR1020027001620A patent/KR100633752B1/ko not_active Expired - Fee Related
  • 2000-02-28 US US10/030,117 patent/US6670669B1/en not_active Expired - Lifetime
  • 2000-02-28 WO PCT/JP2000/001158 patent/WO2001013378A1/ja not_active Ceased

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