Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
  • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/63—Vertical IGFETs
  • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/8303—Diamond
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Definitions

• This invention relates to the field of high power semiconductor switches.
• Semiconductor devices are increasingly required to accommodate high currents and/or high voltages without failing.
• Many high power applications call for the use of a semiconductor switch which is required to conduct a large current when turned on, and to block a high voltage when off.
• MOSFET power metal- oxide-semiconductor field-effect transistor
• SiC silicon carbide
• One such device is described in "High-Voltage Accumulation-Layer UMOSFET's in 4H-SiC", IEEE Electron Device Letters, Vol. 19, No. 12 (December 1998), pp. 487-489.
• This SiC-based device employs a UMOS structure, with an accumulation channel formed on the sidewalls of the trench by epitaxial growth to attain enhancement mode operation. It requires an additional epitaxial layer under the p-base to promote current spreading and achieve low on-resistance.
• the doping levels and the thicknesses of the sidewall epilayer and the epilayer under the p-base must be tightly controlled to achieve an enhancement mode device with low on-resistance.
• a high power unipolar field-effect transistor (FET) switch is presented which overcomes the problems noted above.
• the switch is particularly well-suited to high power switching applications, providing a very low on-resistance, a high blocking voltage, and negligible switching loss.
• An N- drift layer is on an N+ layer which provides an ohmic contact to the drift layer (X+ denotes a carrier concentration of at least 1 x 10 18 /cm 3 , X- denotes a carrier concentration of less than 5 x 10 16 /cm 3 ) .
• a layer of metal on the N+ layer provides a drain connection for the FET.
• a pair of trenches are recessed into the drift layer opposite the N+ layer; the trenches are separated by a mesa region comprised of that portion of the N- drift layer found between the trenches.
• Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material.
• a second layer of metal connects the conductive material in each of the trenches together to provide a gate connection for the FET.
• a shallow P region extends from the bottom of each trench into the drift layer and around the corners formed at the intersections of its respective trench's oxide side- walls and its oxide bottom.
• a second N+ layer is on the N- drift layer within the mesa region which provides an ohmic contact to the mesa region, and a third layer of metal contacts the second N+ layer to provide a source connection for the FET.
• the structure is preferably arranged so that the switch operates as a "normally-off" device; i.e., current is prohibited from flowing between drain and source when the voltage applied to the gate connection is zero. This is accomplished by making the width and doping concentration of the mesa region such that, with no voltage applied to the gate, the mesa region is completely depleted by the potentials created by the work function difference between the conductive material and the N- material in the mesa region.
• the structure can also be arranged to operate as a "normally-on” device by making the mesa region so wide or its doping concentration so high that a negative gate voltage is required to completely deplete the mesa region.
• the mesa region When a positive gate voltage is applied, the mesa region is undepleted and accumulation channels are created adjacent to the oxide side-walls of the trenches.
• the gate voltage modulates the N- drift layer within the mesa region, thereby turning the switch on and allowing current to flow between the drain and the source connections via the mesa region and the accumulation channels.
• the creation of the accumulation channels in combination with the modulation of the mesa region and the use of ohmic contacts, enables the unipolar FET switch to have a low on- resistance. Since the device is unipolar, there are no minority carriers to recombine during turn-off, and thus the device's switching speed can be very fast.
• the shallow P regions surrounding the lower corners of the trench structures protect the corners from high electric fields and thereby increase the switch's breakdown voltage and enhance the reliability of the trench oxide .
• the switch' s N- drift and N+ layers may be conventional silicon (Si) , but are preferably made from semiconductor materials having a bandgap voltage higher than that of silicon, such as silicon carbide (SiC) , gallium nitride (GaN) , gallium arsenide (GaAs), or diamond.
• SiC silicon carbide
• GaN gallium nitride
• GaAs gallium arsenide
• a material's critical field is proportional to its bandgap voltage.
• the use of a wide bandgap material enables the use of a drift layer that, for the same blocking voltage, is much thinner than would be necessary with an Si implementation - an order of magnitude thinner for an SiC implementation.
• the doping concentration a material is capable of attaining is proportional to its critical field.
• these higher- critical-field materials also permit the drift region's doping density to be much higher than an Si version capable of providing the same blocking voltage (an order of magnitude higher for an SiC implementation) , which further reduces the device's on-resistance to very low level.
• Use of a wide bandgap material also enables the device's reverse leakage current to be several orders of magnitude less than a comparable Si device, which serves to increase the temperature at which the switch can be operated.
• the doping concentration m the mesa region is preferably less than it is in the portion of the N- drift layer below the mesa region. This makes it easier to completely deplete the mesa region, which in turn enables the use of a wider and easier to fabricate mesa region. However, due to the presence of the accumulation channels across the mesa region when the switch is on, the lower doping concentration has only a minor effect on the device's on-resistance .
• a number of structures are fabricated in parallel to provide a desired current carrying capacity.
• Devices per the present invention can carry currents of 50 A with a reverse blocking voltage in excess of 1200 volts, on a die size of only 0.1 cm 2 . These characteristics make the novel FET switch well-suited for high power applications.
• FIG. 1 is a sectional view of one embodiment of a FET switch per the present invention.
• FIG. 2 is a sectional view of the switch of FIG. 1, illustrating its operation when off.
• FIG. 3 is a sectional view of the switch of FIG. 1, illustrating its operation when on.
• FIG. 4 is a graph plotting dram current density vs. drain bias for a FET switch per the present invention.
• FIG. 5 is a sectional view of an opposite polarity version of the switch of FIG. 1.
• FIG. 6a is a sectional view of alternative embodiment of a switch per the present invention.
• FIG. 6b is a sectional view of another alternative embodiment of a switch per the present invention.
• FIG. 7 is a cross-sectional view of a multiple-cell implementation of a switch per the present invention, cut along section lines 7-7 in FIGs . 8, 9a, and 9b.
• FIG. 8 is a plan view of one embodiment of a multiple-cell implementation of a switch per the present invention.
• FIG. 9a is a plan view of another embodiment of a multiple-cell implementation of a switch per the present invention.
• FIG. 9b is a plan view of yet another possible embodiment of a multiple-cell implementation of a switch per the present invention.
• FIG. 10 is a schematic diagram of pulse-width modulated motor control circuit employing FET switches per the present invention.
• FIG. 11 is a schematic diagram of switching voltage regulator employing FET switches per the present invention.
• FIG. 1 An exemplary embodiment of a unipolar FET switch m accordance with the present invention is shown in FIG. 1.
• a N- drift layer 100 of a desired thickness is on a first N+ layer 102.
• Recessed into drift layer 100 opposite the N+ layer are a pair of trenches 104, 106, which are separated by a mesa region 108 comprised of that portion of the N- drift layer found between the trenches.
• Each of the trenches has oxide side-walls 110, 112, 114, 116 and oxide bottoms 118, 120, and is filled with a conductive material 121.
• At the bottom of each trench is a shallow P region 122, 124, which extends around the corners formed at the intersections of its respective trench's oxide side-walls and its oxide bottom.
• a second N+ layer 128 is on N- drift layer 100 within mesa region 108.
• the first N+ layer 102 provides an ohmic contact to drift layer 100, and a first layer of metal 130 on N+ layer 102 provides a drain connection for the FET switch.
• the second N+ layer 128 provides an ohmic contact to mesa region 108, and a second layer of metal 132 on N+ layer 128 provides a source connection for the switch.
• a third layer of metal 134 contacts the conductive material 121 in each of the trenches, providing a gate connection for the FET switch.
• the structure of the novel switch is preferably arranged so that it is normally off. This is illustrated in FIG. 2 for the switch of FIG. 1.
• the width and doping concentration of the mesa region 108 are established such that, with no voltage applied to the gate connection 134, the mesa region is completely depleted by the potentials created by the work function difference between the conductive material 121 and the N- material in the mesa region.
• the depletion regions 140 formed around each P region 122, 124 and adjacent to the oxide sidewalls 110, 112, 114, 116 merge in mesa region 108 to form a potential barrier for electrons, preventing the flow of current between drain 130 and source 132.
• the switch can be arranged so that it is normally on.
• FIG. 3 illustrates how the switch of FIG. 1, when configured to be normally off, is turned on. A positive voltage is applied to the gate connection 134.
• the positive gate voltage undepletes the mesa region 108, creates accumulation channels 150 adjacent to the oxide side-walls 110, 112, 114, 116, and modulates the N- drift layer 100 within the mesa region, thereby turning the switch on and enabling current 152 to flow between the drain and source via the mesa region and the accumulation channels.
• FIG. 4 plots drain current density versus drain bias for a gate voltage of 5 volts.
• a normally-on version of the switch conducts current when the gate voltage is zero.
• the application of a positive gate voltage creates accumulation channels and modulates the mesa region, which signif cantly lowers on-resistance and enables the conduction of a much higher current.
• the novel switch is unipolar, there is no recombination of carriers needed to turn-off the device. This makes the switch' s reverse recovery time negligible, and enables it to switch from an on-state to an off-state very quickly.
• voltage overshoot and reverse current virtually eliminated by the unipolar structure, very little power is dissipated when transitioning from an on-state to an off-state. As a result, the switch's switching losses are very low.
• the trenches are preferably recessed vertically into the N- drift region; i.e., with their side-walls approximately perpendicular to the top surface of the drift layer 100.
• each trench may be wider at the top than it is at the bottom, or vice versa. Trenches that are wider at the top than at the bottom make the mesa region wider between the trench bottoms, which tends to lower the switch's on- resistance but may degrade its blocking voltage. Trenches that are wider at the bottom constrict the mesa region, which may increase on-resistance but improve blocking voltage. Vertically-recessed trenches provide a good balance between on-resistance and blocking voltage, and are preferred.
• Conductive material 121 in trenches 104 and 106 is required to, by virtue of its work function difference with the N- mate ⁇ al in the mesa region, create the potentials needed to completely deplete mesa region 108.
• Conductive material 121 is preferably polysilicon which has been heavily-doped with acceptors. Polysilicon is preferred because it easily fills the trenches, but other materials that can fill the trenches and provide good conductivity could also be used, as long as the work function difference between the material and the N- material in the mesa region is sufficient to completely deplete the mesa region.
• a metal could also be used for conductive material 121, as long as it has a higher work function than the N- material in the mesa region; metals are generally not preferred, however, as it is difficult to completely fill a trench with a metal.
• the switch When the switch is required to have a high blocking voltage (i.e., greater than about 300 volts), its N+ and N- d ⁇ ft layers are preferably made from a semiconductor material having a bandgap voltage that is higher than that of silicon (Si) , such as silicon carbide (SiC) , gallium nitride (GaN) , gallium arsenide (GaAs) , or diamond.
• Si silicon carbide
• GaN gallium nitride
• GaAs gallium arsenide
• the peak electric field that a material can withstand without breaking down, i.e., its "critical field" is proportional to its bandgap voltage.
• an SiC layer for example, is able to sustain a peak field that is about 10 times greater than that supportable by an Si layer of comparable thickness.
• the doping concentration a material is capable of attaining is proportional to its critical field.
• SiC's higher critical field enables the switch's material layers to have a doping concentration that is an order of magnitude higher than is possible with Si ( ⁇ 5 x 10 15 vs. ⁇ 8 x 10 13 carriers/cm 3 ) .
• a switch with a 1200 volt blocking voltage could be provided with a drift layer made from Si having a doping density of about 8 x 10 13 carriers/cm 3 which is about 120 ⁇ m thick, or with an SiC drift layer having a doping density of about 5 x 10 15 carriers/cm 3 which is about 12 ⁇ m thick.
• the higher doping concentration achievable with a wide- bandgap material also lowers the device' s on-resistance when compared with an Si implementation.
• a specific on-resistance of about 6 m ⁇ -cm 2 at a gate voltage of 5 volts is attainable with an SiC-based switch structure as described herein.
• a wide-bandgap material also reduces reverse leakage current.
• SiC's wide bandgap enables a device's reverse leakage current to be several orders of magnitude less than an Si-based device of comparable thickness. This factor also serves to increase the temperature at which the switch can be operated. Because reverse leakage current increases exponentially with temperature, conventional devices must be operated at lower temperatures to achieve leakage currents as low as that provided by an SiC implementation. Conversely, a switch fabricated from a wide-bandgap material such as SiC can be operated at higher temperatures while still meeting a given reverse leakage current specification.
• the doping concentration in the mesa region 108 is preferably less than that in the portion of the N- drift layer below the mesa region.
• a zero gate voltage can completely deplete a wider mesa region than would be possible if it had a higher doping concentration. This is desirable because a structure with a wider mesa region is easier to fabricate than one with a narrow mesa. Reducing the doping concentration has only a minor effect on the device's on-resistance, however, due to the accumulation channels 150 created across mesa region 108 when the switch is turned on.
• the shallow P regions 122 and 124 protect the trench oxide from high electric fields.
• the doping of the shallow P regions should be sufficient to prevent them from becoming completely depleted when subjected to the switch's rated breakdown voltage.
• the activated charge needed to accomplish this varies with a material's critical field: for example, an activated charge of about 2 x 10 12 carriers/cm 2 is typically adequate for an Si switch, and a charge of about and 2 x 10 13 carriers/cm 2 should suffice for an SiC-based switch.
• the shallow P regions 122, 124 extend around the trench corners, to protect the corners from premature breakdown caused by high electric fields; this improves the reliability of the trench oxide and enhances the robustness of the switch' s breakdown voltage characteristic.
• the P regions can be floating or connected to the source connection.
• the P regions are preferably made shallow to limit lateral diffusion. To further limit lateral diffusion, it is preferred that the P regions comprise a slow-diffusing material.
• the preferred material for the shallow P regions is aluminum.
• the width of the mesa region Careful consideration must be given to the width of the mesa region, and the widths and depths of the trenches. For example, if a mesa is too narrow, lateral diffusion around the P regions 122, 124 may act to pinch off the conductive path and block current flow. If too wide, the reverse blocking voltage may be adversely affected (as might the operation of a normally-off version of the device) .
• an SiC-based switch having a mesa width of about l-2 ⁇ m, separating trenches that are each about l-2 ⁇ m wide and 3-5 ⁇ m deep, and with an N- drift layer doped to about 1 x 10 16 carriers/cm 3 , provides a low on-resistance while providing a blocking voltage of about 1200 volts.
• a more lightly-doped mesa region would typically be doped to a density of between about 1 x 10" to 1 x 10 15 carriers/cm 3 .
• the present FET switch is not limited to the structure shown in FIG. 1. An opposite polarity embodiment is shown in FIG. 5, in which each of the materials has been swapped with its opposite polarity counterpart.
• a P- drift layer 200 is on a first P+ layer 202.
• a pair of trenches 204, 206 are recessed into drift layer 200 opposite P+ layer 202, and are separated by a mesa region 208.
• Each of the trenches has oxide side-walls 210, 212, 214, 216 and oxide bottoms 218, 220, and is filled with a conductive material 221.
• a shallow N region 222, 224 is at the bottom of each trench.
• a second P+ layer 228 is on P- drift layer 200 within mesa region 208.
• First P+ layer 202 provides an ohmic contact to drift layer 200, and a first layer of metal 230 on P+ layer 202 provides a drain connection for the FET switch.
• the second P+ layer 228 provides an ohmic contact to mesa region 208, and a second layer of metal 232 on P+ layer 228 provides a source connection for the switch.
• a third layer of metal 234 contacts conductive material 221 in each of the trenches, providing a gate connection for the switch.
• the switch functions as before, except that the switch is turned on by applying a negative gate voltage to gate connection 234, which allows current to flow from source 232 to drain 230.
• the conductive material is preferably polysilicon which has been heavily-doped with donors, though other materials can also be used as long as the work function difference between the material and the P- material in the mesa region is sufficient to completely deplete the mesa region (for a normally-off switch) .
• the switch can be fabricated on punch-through wafers (EPI) , in which the drift layer is an epitaxial layer grown to a desired thickness on a bulk substrate material (as in FIG. 1, with epitaxial drift layer 100 on N+ bulk substrate 102), or on non-punch-through (NPT) wafers.
• EPI punch-through wafers
• NPT non-punch-through
• FIG. 6a An exemplary embodiment using an NPT wafer is shown in FIG. 6a.
• the N- drift region 300 is a bulk substrate material
• the N+ region 302 is a very thin layer (0.5 ⁇ m or less) of a material having a large supply of donors, such as phosphorus or nitrogen, which has been implanted or diffused into the backside to provide a low resistance ohmic contact; the rest of the structure is similar to that shown in FIG.
• FIG. 6b Another possible embodiment of the switch is shown in FIG. 6b. This structure is similar to that of the device in FIG. 1, except for the addition of an N type layer 310 which completely envelops P regions 122 and 124.
• N type layer 310 is more heavily doped than N- drift layer 100, it reduces the out-diffusion of P material from P regions 122 and 124, thereby reducing the switch's on-resistance.
• the portion of mesa region 108 found between N type layer 310 and N+ layer 128 may be doped to the same level as the N- drift layer 100; for this embodiment, however, it is preferred that this portion of mesa region 108 be more lightly doped than N-drift layer 100 (as discussed above) .
• the reduction in on-resistance a more lightly-doped mesa might otherwise cause is compensated for by the improved on- resistance brought about by N layer 310.
• a die 400 has an N- drift layer 402 on an N+ layer 404, with a metal layer 406 on layer 404 providing a drain connection; each of these layers runs approximately the full length and width of the die.
• a number of trench structures 408 are spaced periodically across the die, each of which has the same structure as the trenches shown in FIG.
• a normally-on version of the switch has the same basic structure as that shown in FIG. 7, except for the use of wider mesa regions as discussed above.
• the switch operates as described above, with the mesa regions 420 being completely depleted when the gate voltage is zero (for a normally-off embodiment), making the switch normally-off.
• the mesa regions become undepleted and accumulation channels form adjacent to the oxide side-walls 412, allowing current to flow between drain and source via the mesa regions.
• Simulation results indicate that a multiple-cell switch such as that shown in FIG. 7 can accommodate current densities in excess of 500 A/cm 2 .
• the trench structures may be arrayed across the die in a wide variety of ways.
• FIG. 8 is a plan view that corresponds with the cross- sectional view of FIG. 7 (metal layers 406, 418, and 424 not shown for clarity) .
• the trench structures 408 form channels that run the length of the die 400, and are spaced periodically across its width.
• FIG. 9a Another possible trench structure arrangement is shown in FIG. 9a, which also corresponds with the cross-sectional view of FIG. 7.
• the N+ layers 422 and the mesa regions 420 below them are cylindrical in shape and surrounded with oxide side-walls 412, and are spaced periodically within the die 400.
• the trench structures' conductive material 410 and the buried P regions 416 occupy the area between the cylindrical mesa regions.
• FIG. 9a An alternative arrangement to that shown in FIG. 9a is also possible, in which the mesa regions 420 and the trench structures 408 are reversed.
• the trench structures could be circular in shape and surrounded by cylindrical oxide side-walls, and spaced periodically within the die 400, with the trench structures 408 recessed in the area between the mesa regions 420.
• the perimeter of each of the mesa regions or trenches may also describe a polygon.
• FIG. 9b which also corresponds with the cross-sectional view of FIG. 7.
• the N+ layers 422, the mesa regions 420 below them, and the oxide side-walls 412 surrounding them are hexagonal in shape, and are spaced periodically within the die 400.
• trench structure arrays shown in FIGs. 7-9b are merely exemplary; many other possible trench and mesa geometries and arrangements are possible which will result in switches that adhere to the principles of the invention. It is recommended that square-shaped trenches be avoided, because the high peak fields that appear at the trench corners can result in the premature breakdown of the device.
• a “termination” typically surrounds an array of cells as described above, to protect the cells on the outer edges of the array.
• the termination depth extend well into the drift layer. This serves to better protect the outlying trench structures, and reduces the sharpness of the termination's corners, which enhances the termination's ability to protect the trenches from high electric fields.
• the termination is typically P type.
• the termination may be formed with the same P type material as is used for the buried P regions below each trench. This is not recommended for an SiC implementation, however: aluminum is the preferred material for the P regions, because it is slow-diffusing in SiC and can thus limit lateral diffusion.
• the termination is preferably fast-diffusing. As such, a fast- diffusing material such as boron is preferred for the termination around an SiC device.
• a high power switch is provided by employing an array of switch cells across a die.
• a switch as described herein can carry a current of at least 50 A with a die having a surface area of about 0.1 cm 9 .
• a PWM motor control circuit 580 provides variable frequency AC power to a 3-phase AC motor 582 using six switching transistors and six flyback diodes.
• Each switch is made from two transistors connected in a totem-pole configuration: one switch (typical of all the switches), is made from a pair of transistors 584, 586 per the present invention, connected in series between a high voltage DC bus and ground, with a flyback diode 588 connected across each transistor.
• the switching transistors are driven by a gate drive circuit 590, which regulates power to the motor by adjusting the time duration for the on and off states of each switch.
• the switching transistors used in a motor control circuit application have a high blocking voltage, a low on- resistance, fast switching speed and low switching losses.
• the FET switch described herein offers all of these characteristics, making it well-suited for use in a motor control circuit.
• FIG. 11 depicts a basic switching voltage regulator 600.
• Two rectifiers 602 are employed on the primary side of the regulator, connected in series with respective switching transistors 604 and 606; both transistor/rectifier branches are connected across an input voltage V ⁇ n .
• the switching transistors 604, 606 conduct a current through the primary side of a transformer 608 when switched on, and the rectifiers 602 conduct the transformer current when the transistors are switched off.
• Rectifiers 610 are connected to the secondary side of transformer 608 and, with output inductor 612, produce a rectified output voltage V out from the regulator.
• the switching transistors' fast switching speed and low switching losses make it well-suited for use in switching regulator applications.
• the high power unipolar FET switch is fabricated using conventional means well-known to those in the art of semiconductor fabrication. Though the device's trench structures require processing steps that are not necessary when fabricating other switch types, such as planar MOSFETs, the additional fabrication complexity is offset by the greatly improved performance of the device when used in high power applications . While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.

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