WO1999054935A1 - Dispositif portable de telecommunications - Google Patents

Dispositif portable de telecommunications Download PDF

Info

Publication number
WO1999054935A1
WO1999054935A1 PCT/JP1998/001744 JP9801744W WO9954935A1 WO 1999054935 A1 WO1999054935 A1 WO 1999054935A1 JP 9801744 W JP9801744 W JP 9801744W WO 9954935 A1 WO9954935 A1 WO 9954935A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
semiconductor chip
communication device
portable communication
electrode
Prior art date
Application number
PCT/JP1998/001744
Other languages
English (en)
Japanese (ja)
Inventor
Toshinori Hirashima
Tsuneo Endo
Masatoshi Morikawa
Mitsuaki Hibino
Tomio Yamada
Sakae Kikuchi
Shinji Moriyama
Original Assignee
Hitachi, Ltd.
Hitachi Tohbu Semiconductor, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/001744 priority Critical patent/WO1999054935A1/fr
Priority to AU68524/98A priority patent/AU6852498A/en
Publication of WO1999054935A1 publication Critical patent/WO1999054935A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/03—Constructional details, e.g. casings, housings
    • H04B1/036—Cooling arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Definitions

  • the present invention relates to a mobile communication device, and particularly to a technology effective when applied to a mobile communication device such as a mobile phone or a mobile phone equipped with an antenna and a power amplifier circuit module.
  • mobile communication devices such as a PDC (Persona1Digitala1C1E1lullar) type mobile phone and a mobile phone such as a PHS (Persona1 1Handy phponesyms) type mobile phone have rapidly spread.
  • these portable communication devices emit an electric wave and receive an electric wave, an antenna for supplying a transmitting high-frequency signal to the antenna, a radio unit for converting a received high-frequency signal received by the antenna to an intermediate frequency, and a voice unit. It consists of a baseband unit that performs signal processing and input / output control.
  • the configuration of these portable communication devices is disclosed in, for example, “Hitachi Review”, vol. 78, No. 11 (1996-1-11), and pp. 21-26. .
  • One of the components of the upper device is a power amplifier circuit module provided in the wireless section of a portable communication device.
  • this power amplifier circuit module it is necessary to reduce the size of the semiconductor chip that constitutes the amplifier. Is essential.
  • the size of the semiconductor chip is reduced, the ability to radiate heat generated inside the semiconductor chip to the outside decreases. As a result, the heat generated inside the semiconductor chip adversely affects the amplification characteristics of the amplifying element, and may cause deterioration of the characteristics of the mobile communication device. For this reason, there is a problem that it is difficult to further reduce the size of the power amplification circuit module.
  • the present invention has been made to solve the problems of the prior art, and an object of the present invention is to further reduce the size of a power amplifier circuit module in a portable communication device, and to further reduce the size.
  • the aim is to provide technologies that can be achieved.
  • a portable communication device including an antenna and a power amplification circuit module for amplifying a high-frequency signal radiated from the antenna, wherein the power amplification circuit module is mounted on a wiring board, and on the wiring board, Multiple ba
  • the wiring board is connected to a part of the plurality of bump electrodes by a bump electrode. It has a conductor that is electrically and mechanically connected and serves as a heat dissipation path.
  • the wiring board is a multilayer wiring board in which wiring layers are formed over multiple layers, and the conductor serving as the heat dissipation path is formed to penetrate each wiring layer of the multilayer wiring board.
  • the conductor serving as the heat dissipation path is characterized in that a cross-sectional shape of a wiring layer in contact with the bump electrode of the multilayer wiring board is an ellipse or an ellipse.
  • the cross-sectional area of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is larger than the cross-sectional area of the wiring layer in contact with the bump electrode of the multilayer wiring board. Is also large.
  • the cross-sectional shape of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is circular.
  • the semiconductor chip is a field-effect transistor formed on one main surface of a semiconductor substrate.
  • the conductor serving as the heat dissipation path is electrically and mechanically connected to a bump electrode formed on a source electrode of the field effect transistor.
  • the power amplification circuit module includes a plurality of wiring layers and a plurality of through holes whose inside is filled with a metal layer. Having a gate electrode, a source electrode, and a drain electrode on its main surface A semiconductor chip having a field-effect transistor formed thereon, the semiconductor chip being mounted on the multilayer wiring such that the main surface faces the multilayer wiring board; and the gate electrode, the source electrode, and the drain of the semiconductor chip. And a plurality of bump electrodes for electrically and mechanically connecting the plurality of wiring layers of the multilayer wiring board to each other, and at a position facing the source electrode of the semiconductor chip. At least one of the plurality of through holes is arranged, and each of the through holes arranged at a position facing the source electrode and the source electrode are electrically and mechanically connected via the plurality of bump electrodes. Is connected to the terminal.
  • the semiconductor chip has a rectangular shape, and the source electrode has a first portion extending planarly along a long side direction of the semiconductor chip; and a short portion of the semiconductor chip extending from the first portion. A second portion extending along a side direction, wherein the plurality of bump electrodes connected to the source electrode are connected to the second portion along a short side direction of the semiconductor chip. It is characterized by that.
  • the multilayer wiring board is a ceramic board, and a minimum pitch at which the plurality of bump electrodes can be arranged is smaller than a minimum pitch at which the plurality of through holes can be arranged.
  • a semiconductor chip is mounted on a wiring board by a flip-chip method, and a conductor serving as a heat dissipation path is provided on the wiring board, and the heat dissipation path is provided.
  • a conductor serving as a heat dissipation path is provided on the wiring board, and the heat dissipation path is provided.
  • FIG. 1 is a block diagram showing a schematic configuration of a mobile phone according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an example of a circuit configuration of the power amplifier shown in FIG.
  • FIG. 3 is a top plan view of a power amplifier circuit module in which the circuit configuration shown in FIG. 2 is modularized.
  • FIG. 4 is a diagram for explaining a method of mounting a semiconductor chip (CHT 2) on a multilayer wiring board in the present embodiment.
  • FIG. 5 is a diagram showing a state in which a semiconductor chip (CHT 2) is mounted on a multilayer wiring board in the present embodiment.
  • FIG. 6 is a cross-sectional view of a main part of a multilayer wiring board on which a semiconductor chip (CHT 2) is mounted in the present embodiment.
  • FIG. 7 is a top plan view of a conventional power amplifier circuit module.
  • FIG. 8 is a diagram for explaining a method of manufacturing the power amplification circuit module of the present embodiment.
  • FIG. 9 is a diagram showing a specific example of the power amplification circuit module of the present embodiment.
  • FIG. 10 is a circuit diagram showing another example of the circuit configuration of the power amplifier shown in FIG.
  • FIG. 11 is a circuit diagram showing another example of the circuit configuration of the power amplifier shown in FIG.
  • FIG. 12 is a diagram showing a modification of the thermal via (through hole) of the present embodiment.
  • the mobile phone emits radio waves, supplies an antenna 10 for receiving radio waves, a high-frequency signal to the antenna 10, and a reception signal received by the antenna 10. It comprises a radio section 20 for converting a high-frequency signal to an intermediate frequency and a baseband section 30.
  • the radio section 20 includes a high frequency section 120 and a low frequency section 130.
  • the high-frequency section 120 is composed of a power mixer (high-frequency power amplifier circuit module) 122 that amplifies the power of the transmission high-frequency signal output from the transmission mixer 123 and the transmission mixer 123, and an antenna 110 on the transmission side. And a receiving side, an antenna switch 122, a low noise amplifier 124 for amplifying a high frequency signal received by the antenna 10, and a receiving mixer 125. Further, the low frequency section 130 is composed of a quadrature modulator 131, a frequency synthesizer 132, and an intermediate frequency amplifier 133.
  • the baseband unit 30 performs audio signal processing and input / output control.
  • the power amplifier 122 shown in FIG. 1 uses field-effect transistors (FET1, FET2) as the amplification elements.
  • the second circuit is a power amplifier having a two-stage configuration in which an FET amplification circuit having a source ground circuit configuration is cascaded in two stages.
  • the power amplifier shown in FIG. 1 includes a chip component CH such as a resistor and a capacitor and a semiconductor chip (CHT 1 and CHT 2) on a multilayer wiring board 1 composed of a ceramic substrate. ) are implemented and modularized.
  • This semiconductor chip (CHT1, CHT2) is composed of a single crystal semiconductor substrate such as silicon (Si) or a compound semiconductor substrate such as gallium arsenide (GaAs).
  • Field-effect transistors (FET1, FET2) are formed on the surface.
  • the surface of the semiconductor chip (CHT 2) in contact with the multilayer wiring board 1 is provided on both sides of the element forming region 6 with the gate electrode 7g, the source electrode 7s, and the drain, respectively.
  • An electrode 7d is provided.
  • the source electrode 7 s is formed in a comb tooth shape
  • the gate electrode 7 g is arranged between the comb teeth of the source electrode 7 s. Note that the region that substantially operates as an FET is shown as an active region AE in FIG. As shown in FIG.
  • the electrodes (gate electrode 7g, source electrode 7s, Corresponding to the drain electrode 7d), a gate wiring electrode 2g, a source wiring electrode 2s, and a drain wiring electrode 2d are formed, respectively.
  • the gate electrode 7 g, the source electrode 7 s and the drain electrode 7 d of the semiconductor chip (C HT 2) are connected to the gate wiring electrode 2 g of the multilayer wiring board 1 and the source wiring electrode via the bump electrode 3. 2s and drain wiring electrode 2d are electrically and mechanically connected.
  • the semiconductor chip (CHT 2) is mounted on the multilayer wiring board 1 as shown in FIG.
  • a plurality of bump electrodes 3 are provided on the source electrode 7 s and the drain electrode 7 d of the semiconductor chip (C HT 2).
  • the source wiring electrode 2 s and the gate wiring electrode 2 g on the multilayer wiring board 1 are formed in a comb-teeth shape, and a thermal via (therma 1 viahole) ( 4, 5) are formed.
  • the thermal via is also referred to as a through hole.
  • the thermal vias (4, 5) penetrate through the inside of the multilayer wiring board 1 and are provided up to the back surface layer of the multilayer wiring board 1, as shown in FIG. 6 (a).
  • the cross-sectional shape of the thermal via 4 in the first wiring layer (or the surface layer) of the multilayer wiring board 1 has an oval (or elliptical) shape.
  • the cross-sectional shape of the thermal via 5 in the second and subsequent wiring layers (or the inner layer and the back surface layer) of the multilayer wiring board 1 is formed in a circular shape.
  • the size of the cross-sectional shape of the thermal via 5 of the second and subsequent wiring layers is such that the elliptical shape (or elliptical shape) of the thermal via 4 of the first wiring layer is included in the circular shape.
  • a large drain current (IDS) flows between the source and drain of the field-effect transistor (FET 2).
  • IDS drain current
  • FET 2 field-effect transistor
  • Heat generation becomes a problem. That is, the characteristics of Si—FETs that use Si (silicon) as a semiconductor substrate deteriorate because the transconductance (gm) decreases as the temperature rises, and G a A as a semiconductor substrate. In G a A s — FETs that use s (gallium arsenide), thermal runaway occurs at elevated temperatures, and in the worst case, the FETs burst.
  • the thermal vias (4, 5) described above are used for the semiconductor chip (CHT2). It is provided to make it easier to dissipate the heat generated inside and to prevent the problems described above.
  • the thermal vias (4, 5) are formed in an elliptical (or elliptical) cross section in the first wiring layer of the multilayer wiring board 1. In the second and subsequent wiring layers, the cross-sectional shape is formed in a circular shape, whereby the heat radiation effect can be improved.
  • thermal vias (4, 5) are arranged immediately below the bump electrodes 3.
  • a thermal resistance corresponding to the shift is added, and efficient heat dissipation is difficult.
  • the heat generated inside the semiconductor chip (C HT 2) can be efficiently dissipated, so that the field effect transistor (TFT 2) Deterioration of characteristics or destruction of the field effect transistor (TFT 2) can be prevented, and the current value of the drain current (IDS) that can flow between the source and the drain of the field effect transistor (TFT 2) can be prevented. Since the width (difference between the maximum current value and the minimum current value) can be increased, the design margin can be improved.
  • each electrode (source electrode, gate electrode and drain electrode) of the semiconductor chip (CHT 2) and the multi-layer wiring board 1 are connected by wire bonding.
  • the formed wiring electrodes (source wiring electrode, gate wiring electrode, and drain wiring electrode) were electrically connected.
  • a predetermined distance is required between each electrode of the semiconductor chip (CHT 2) and the wiring electrode formed on the multilayer wiring board 1. Therefore, in the conventional power amplifier circuit module, when mounting the semiconductor chip (CHT2) on the multilayer wiring board 1, a large area (or area) is required, and there is a limit to the miniaturization of the power amplifier circuit module. there were.
  • the size can be 7 mm X 7 mm.
  • the present embodiment is suitable for a high-frequency circuit because the wiring length is shorter than that of wire bonding.
  • the thermal vias (4, 5) are formed on the teeth of the comb of the source wiring electrode 2s. This is because when a thermal via (4, 5) is formed at the connection of the comb teeth of the gate wiring electrode 2 g, the drain wiring electrode 2 d or the source wiring electrode 2 s, the field effect transistor (FET 2 This is because parasitic capacitance is added to the gate electrode or drain electrode of), which affects the amplification characteristics of the field-effect transistor (FET 2).
  • the source electrode of the field-effect transistor (FET 2) is at the ground potential (G ND), so that the thermal via (4, 5) Is formed on the teeth of the comb of the source wiring electrode 2 s without adversely affecting the amplification characteristics of the field-effect transistor (FET 2). If the amplification characteristics of the field-effect transistor (FET 2) are not affected, the thermal vias (4, 5) are connected to the gate wiring electrode 2g, the drain wiring electrode 2d, or the source wiring electrode 2d. It may be formed at the connecting portion of the teeth of the s comb.
  • the power amplification circuit module of the present embodiment is manufactured by the following method.
  • the green sheets (9a to 9e) are aligned and superimposed, and then each green sheet is heated and pressurized to thereby obtain a respective dust sheet.
  • (9a-9e) is sintered to form a multilayer wiring board 1 made of ceramic.
  • the ceramic substrate has a lower coefficient of linear expansion than silicon and GaAs and a lower stress than glass-epoxy substrates. Also, the dielectric constant is low.
  • the semiconductor chip C HT 2 on which the bump electrode 3 is formed is mounted on the multilayer wiring board 1, and is mounted by soldering.
  • the bump electrode 3 is formed, for example, by forming an Au wire on a semiconductor chip electrode by a ball bonding method and leaving only the ball portion of the Au wire.
  • the minimum pitch between bumps can be about 20 ⁇ m.
  • a chip such as a resistor or a capacitor is provided on the multilayer wiring board 1. Parts are also mounted by soldering.
  • FIG. 9 shows a specific example of the power amplifier circuit module of the present embodiment manufactured by the method shown in FIG.
  • the thermal via 4 in the first wiring layer of the multilayer wiring board 1 has an elliptical shape having a width of 0.1 mm and a length of 0.25 mm.
  • the thermal vias 5 in the wiring layers other than the first layer of the multilayer wiring board 1 were circular with a diameter of 0.25 mm, and the interval between the thermal vias 5 was 0.50 mm.
  • the bump electrode 3 was a circle having a diameter of 0.09 mm, and the interval between the bump electrodes 3 was 0.12 mm. Note that the thickness of the multilayer wiring board 1 is 0.5 mm.
  • the size of the thermal via (4, 5) is limited by the manufacturing process of the multilayer wiring board 1 (if the thermal via (4, 5) becomes large, the green sheet It is determined from the fact that the conductor paste comes off from the ground or the gap between the thermal vials (4, 5) becomes narrow, so that the green sheet cracks).
  • the formation of the through-holes in the multilayer ceramic substrate requires a margin for the alignment of the through-holes between the respective layers, so that it is difficult to match the pitch of the bump electrodes 3. Therefore, in the present invention, the diameter of the through hole is widened so that a plurality of bump electrodes 3 can be connected.
  • the size of the thermal vias (4, 5) can be made larger than that shown in FIG.
  • the size of Malvia (4, 5) is made larger than that shown in Fig. 9, the heat radiation effect can be further improved.
  • the pitch on the bump electrode side is widened, the area of the semiconductor chip itself becomes large, and miniaturization becomes difficult, which is not practical.
  • the circuit configuration shown in FIG. 10 or FIG. 11 is adopted as the circuit configuration of the power amplifier shown in FIG. Is also good.
  • a field effect transistor (FET 3) constitutes an active filter circuit.
  • the thermal via 4 may be the one shown in FIG.
  • the thermal via 4 shown in FIG. 12 has a half cross section of the thermal via (4a) formed on the source wiring electrodes 2 s at both ends in the first wiring layer of the multilayer wiring board 1. It has a circular shape. According to the thermal via (4 a) shown in FIG. 12, the area of the thermal via (4, 4 a) in the first wiring layer of the multilayer wiring board 1 is increased, so that the heat dissipation effect is further improved. Can be enhanced.
  • the mounting method of the semiconductor chip (C HT 2) and the multilayer wiring board 1 has been described as an example.
  • the present invention is not limited to this, and the present invention is shown in FIG. It goes without saying that the present invention is also applicable to a method of mounting the semiconductor chip (CHT 1) and the multilayer wiring board 1.
  • the present invention is not limited to this.
  • the invention as has been described can be applied in which c above semiconductor chip bipolar transistor is formed on a principal surface, the following advantages are provided according to the present embodiment.
  • a multilayer wiring board A thermal via (4, 5) penetrating to the lowermost wiring layer is formed in 1 and the source electrode 2s of the semiconductor chip (CHT1, CHT2) and the thermal via (4, 5) are bump electrodes. Since the connection is made electrically and mechanically via 3, heat generated inside the semiconductor chips (CHT 1 and CHT 2) can be efficiently dissipated.
  • the size of the power amplification circuit module of the mobile communication device can be further reduced, so that the size of the mobile communication device can be further reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention porte sur un dispositif portable de télécommunications muni d'une antenne et d'un circuit d'amplification de signaux à haute fréquence émis par l'antenne. Ledit circuit d'amplification comporte une plaquette (1) de CI sur laquelle est monté un élément à semi-conducteur (CHT) (2) relié mécaniquement et électriquement à la plaquette (1) par une série de plots de contact (3). Le substrat (1) comporte des conducteurs (4 et 5) relié mécaniquement et électriquement à certaines parties des plots de contact (3) et servant de canaux de dissipation de chaleur. La plaquette (1) du dispositif portable est faite de plusieurs couches de circuits dont chacune comporte des conducteurs (4 et 5) servant de canaux de dissipation de chaleur. Il en résulte une réduction de la taille du circuit d'amplification, et par là, de celle du dispositif de télécommunications.
PCT/JP1998/001744 1998-04-16 1998-04-16 Dispositif portable de telecommunications WO1999054935A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP1998/001744 WO1999054935A1 (fr) 1998-04-16 1998-04-16 Dispositif portable de telecommunications
AU68524/98A AU6852498A (en) 1998-04-16 1998-04-16 Portable communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/001744 WO1999054935A1 (fr) 1998-04-16 1998-04-16 Dispositif portable de telecommunications

Publications (1)

Publication Number Publication Date
WO1999054935A1 true WO1999054935A1 (fr) 1999-10-28

Family

ID=14208052

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/001744 WO1999054935A1 (fr) 1998-04-16 1998-04-16 Dispositif portable de telecommunications

Country Status (2)

Country Link
AU (1) AU6852498A (fr)
WO (1) WO1999054935A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6860006B2 (en) 2000-03-17 2005-03-01 Murata Manufacturing Co, Ltd. Method for manufacturing a monolithic ceramic electronic component
JP2012256631A (ja) * 2011-06-07 2012-12-27 Toshiba Corp 半導体装置及びその製造方法
US20210313293A1 (en) * 2020-04-03 2021-10-07 Cree, Inc. Rf amplifier devices and methods of manufacturing
US11362011B2 (en) 2019-04-01 2022-06-14 Nuvoton Technology Corporation Japan Power amplification device
US11670605B2 (en) 2020-04-03 2023-06-06 Wolfspeed, Inc. RF amplifier devices including interconnect structures and methods of manufacturing
US11837457B2 (en) 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers
US12034419B2 (en) 2022-05-05 2024-07-09 Macom Technology Solutions Holdings, Inc. RF amplifiers having shielded transmission line structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521959A (ja) * 1991-07-16 1993-01-29 Nec Corp 高放熱形複合基板
JPH0590437A (ja) * 1991-09-25 1993-04-09 Nippon Cement Co Ltd 放熱用複合基板
JPH09181642A (ja) * 1995-12-22 1997-07-11 Sony Corp 通信端末装置
JP2719067B2 (ja) * 1991-03-29 1998-02-25 松下電器産業株式会社 電力用モジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2719067B2 (ja) * 1991-03-29 1998-02-25 松下電器産業株式会社 電力用モジュール
JPH0521959A (ja) * 1991-07-16 1993-01-29 Nec Corp 高放熱形複合基板
JPH0590437A (ja) * 1991-09-25 1993-04-09 Nippon Cement Co Ltd 放熱用複合基板
JPH09181642A (ja) * 1995-12-22 1997-07-11 Sony Corp 通信端末装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6860006B2 (en) 2000-03-17 2005-03-01 Murata Manufacturing Co, Ltd. Method for manufacturing a monolithic ceramic electronic component
JP2012256631A (ja) * 2011-06-07 2012-12-27 Toshiba Corp 半導体装置及びその製造方法
US8786077B2 (en) 2011-06-07 2014-07-22 Kabushiki Kaisha Toshiba Semiconductor device having a first substrate containing circuit element connected to radiation plate on a cover plate with metal vias
US11362011B2 (en) 2019-04-01 2022-06-14 Nuvoton Technology Corporation Japan Power amplification device
US20210313293A1 (en) * 2020-04-03 2021-10-07 Cree, Inc. Rf amplifier devices and methods of manufacturing
US11670605B2 (en) 2020-04-03 2023-06-06 Wolfspeed, Inc. RF amplifier devices including interconnect structures and methods of manufacturing
US11837457B2 (en) 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers
US12034419B2 (en) 2022-05-05 2024-07-09 Macom Technology Solutions Holdings, Inc. RF amplifiers having shielded transmission line structures

Also Published As

Publication number Publication date
AU6852498A (en) 1999-11-08

Similar Documents

Publication Publication Date Title
US8339204B2 (en) Semiconductor device
KR100993277B1 (ko) 반도체장치 및 전자 장치
KR100634947B1 (ko) 고주파 디바이스
US7995984B2 (en) Semiconductor device
US10950569B2 (en) High frequency module and communication device
JP2000124358A (ja) 高周波集積回路
JP2004282752A (ja) 能動型スマートアンテナシステム及びその製造方法
JP5577694B2 (ja) 部品内蔵モジュール
KR100993579B1 (ko) 반도체장치 및 전자 장치
KR20240005847A (ko) 집적 수동 디바이스(ipd) 컴포넌트 및 이를 구현하기 위한 패키지 및 프로세스
JPH10242377A (ja) 高周波電力増幅器モジュール
JP2018085613A (ja) 半導体装置
JP3515854B2 (ja) 高周波電力増幅回路装置
WO1999054935A1 (fr) Dispositif portable de telecommunications
WO2011104774A1 (fr) Dispositif semi-conducteur
JP3744828B2 (ja) 半導体装置
JP2002009193A (ja) 半導体装置
JPH09148373A (ja) 無線通信モジュール
JP2000106386A (ja) 高周波増幅器
JP2005340713A (ja) マルチチップモジュール
JP2003229521A (ja) 半導体モジュール及びその製造方法
JP2006332096A (ja) 半導体装置
JP2001068615A (ja) 電力増幅モジュール
JPH0714877A (ja) 半導体装置
JP2005236685A (ja) マイクロ波電力増幅モジュール

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM GW HU ID IL IS JP KE KG KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA