WO1999054935A1 - Portable communication equipment - Google Patents

Portable communication equipment Download PDF

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Publication number
WO1999054935A1
WO1999054935A1 PCT/JP1998/001744 JP9801744W WO9954935A1 WO 1999054935 A1 WO1999054935 A1 WO 1999054935A1 JP 9801744 W JP9801744 W JP 9801744W WO 9954935 A1 WO9954935 A1 WO 9954935A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
semiconductor chip
communication device
portable communication
electrode
Prior art date
Application number
PCT/JP1998/001744
Other languages
French (fr)
Japanese (ja)
Inventor
Toshinori Hirashima
Tsuneo Endo
Masatoshi Morikawa
Mitsuaki Hibino
Tomio Yamada
Sakae Kikuchi
Shinji Moriyama
Original Assignee
Hitachi, Ltd.
Hitachi Tohbu Semiconductor, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/001744 priority Critical patent/WO1999054935A1/en
Priority to AU68524/98A priority patent/AU6852498A/en
Publication of WO1999054935A1 publication Critical patent/WO1999054935A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0204Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02Transmitters
    • H04B1/03Constructional details, e.g. casings, housings
    • H04B1/036Cooling arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/096Vertically aligned vias, holes or stacked vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Definitions

  • the present invention relates to a mobile communication device, and particularly to a technology effective when applied to a mobile communication device such as a mobile phone or a mobile phone equipped with an antenna and a power amplifier circuit module.
  • mobile communication devices such as a PDC (Persona1Digitala1C1E1lullar) type mobile phone and a mobile phone such as a PHS (Persona1 1Handy phponesyms) type mobile phone have rapidly spread.
  • these portable communication devices emit an electric wave and receive an electric wave, an antenna for supplying a transmitting high-frequency signal to the antenna, a radio unit for converting a received high-frequency signal received by the antenna to an intermediate frequency, and a voice unit. It consists of a baseband unit that performs signal processing and input / output control.
  • the configuration of these portable communication devices is disclosed in, for example, “Hitachi Review”, vol. 78, No. 11 (1996-1-11), and pp. 21-26. .
  • One of the components of the upper device is a power amplifier circuit module provided in the wireless section of a portable communication device.
  • this power amplifier circuit module it is necessary to reduce the size of the semiconductor chip that constitutes the amplifier. Is essential.
  • the size of the semiconductor chip is reduced, the ability to radiate heat generated inside the semiconductor chip to the outside decreases. As a result, the heat generated inside the semiconductor chip adversely affects the amplification characteristics of the amplifying element, and may cause deterioration of the characteristics of the mobile communication device. For this reason, there is a problem that it is difficult to further reduce the size of the power amplification circuit module.
  • the present invention has been made to solve the problems of the prior art, and an object of the present invention is to further reduce the size of a power amplifier circuit module in a portable communication device, and to further reduce the size.
  • the aim is to provide technologies that can be achieved.
  • a portable communication device including an antenna and a power amplification circuit module for amplifying a high-frequency signal radiated from the antenna, wherein the power amplification circuit module is mounted on a wiring board, and on the wiring board, Multiple ba
  • the wiring board is connected to a part of the plurality of bump electrodes by a bump electrode. It has a conductor that is electrically and mechanically connected and serves as a heat dissipation path.
  • the wiring board is a multilayer wiring board in which wiring layers are formed over multiple layers, and the conductor serving as the heat dissipation path is formed to penetrate each wiring layer of the multilayer wiring board.
  • the conductor serving as the heat dissipation path is characterized in that a cross-sectional shape of a wiring layer in contact with the bump electrode of the multilayer wiring board is an ellipse or an ellipse.
  • the cross-sectional area of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is larger than the cross-sectional area of the wiring layer in contact with the bump electrode of the multilayer wiring board. Is also large.
  • the cross-sectional shape of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is circular.
  • the semiconductor chip is a field-effect transistor formed on one main surface of a semiconductor substrate.
  • the conductor serving as the heat dissipation path is electrically and mechanically connected to a bump electrode formed on a source electrode of the field effect transistor.
  • the power amplification circuit module includes a plurality of wiring layers and a plurality of through holes whose inside is filled with a metal layer. Having a gate electrode, a source electrode, and a drain electrode on its main surface A semiconductor chip having a field-effect transistor formed thereon, the semiconductor chip being mounted on the multilayer wiring such that the main surface faces the multilayer wiring board; and the gate electrode, the source electrode, and the drain of the semiconductor chip. And a plurality of bump electrodes for electrically and mechanically connecting the plurality of wiring layers of the multilayer wiring board to each other, and at a position facing the source electrode of the semiconductor chip. At least one of the plurality of through holes is arranged, and each of the through holes arranged at a position facing the source electrode and the source electrode are electrically and mechanically connected via the plurality of bump electrodes. Is connected to the terminal.
  • the semiconductor chip has a rectangular shape, and the source electrode has a first portion extending planarly along a long side direction of the semiconductor chip; and a short portion of the semiconductor chip extending from the first portion. A second portion extending along a side direction, wherein the plurality of bump electrodes connected to the source electrode are connected to the second portion along a short side direction of the semiconductor chip. It is characterized by that.
  • the multilayer wiring board is a ceramic board, and a minimum pitch at which the plurality of bump electrodes can be arranged is smaller than a minimum pitch at which the plurality of through holes can be arranged.
  • a semiconductor chip is mounted on a wiring board by a flip-chip method, and a conductor serving as a heat dissipation path is provided on the wiring board, and the heat dissipation path is provided.
  • a conductor serving as a heat dissipation path is provided on the wiring board, and the heat dissipation path is provided.
  • FIG. 1 is a block diagram showing a schematic configuration of a mobile phone according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an example of a circuit configuration of the power amplifier shown in FIG.
  • FIG. 3 is a top plan view of a power amplifier circuit module in which the circuit configuration shown in FIG. 2 is modularized.
  • FIG. 4 is a diagram for explaining a method of mounting a semiconductor chip (CHT 2) on a multilayer wiring board in the present embodiment.
  • FIG. 5 is a diagram showing a state in which a semiconductor chip (CHT 2) is mounted on a multilayer wiring board in the present embodiment.
  • FIG. 6 is a cross-sectional view of a main part of a multilayer wiring board on which a semiconductor chip (CHT 2) is mounted in the present embodiment.
  • FIG. 7 is a top plan view of a conventional power amplifier circuit module.
  • FIG. 8 is a diagram for explaining a method of manufacturing the power amplification circuit module of the present embodiment.
  • FIG. 9 is a diagram showing a specific example of the power amplification circuit module of the present embodiment.
  • FIG. 10 is a circuit diagram showing another example of the circuit configuration of the power amplifier shown in FIG.
  • FIG. 11 is a circuit diagram showing another example of the circuit configuration of the power amplifier shown in FIG.
  • FIG. 12 is a diagram showing a modification of the thermal via (through hole) of the present embodiment.
  • the mobile phone emits radio waves, supplies an antenna 10 for receiving radio waves, a high-frequency signal to the antenna 10, and a reception signal received by the antenna 10. It comprises a radio section 20 for converting a high-frequency signal to an intermediate frequency and a baseband section 30.
  • the radio section 20 includes a high frequency section 120 and a low frequency section 130.
  • the high-frequency section 120 is composed of a power mixer (high-frequency power amplifier circuit module) 122 that amplifies the power of the transmission high-frequency signal output from the transmission mixer 123 and the transmission mixer 123, and an antenna 110 on the transmission side. And a receiving side, an antenna switch 122, a low noise amplifier 124 for amplifying a high frequency signal received by the antenna 10, and a receiving mixer 125. Further, the low frequency section 130 is composed of a quadrature modulator 131, a frequency synthesizer 132, and an intermediate frequency amplifier 133.
  • the baseband unit 30 performs audio signal processing and input / output control.
  • the power amplifier 122 shown in FIG. 1 uses field-effect transistors (FET1, FET2) as the amplification elements.
  • the second circuit is a power amplifier having a two-stage configuration in which an FET amplification circuit having a source ground circuit configuration is cascaded in two stages.
  • the power amplifier shown in FIG. 1 includes a chip component CH such as a resistor and a capacitor and a semiconductor chip (CHT 1 and CHT 2) on a multilayer wiring board 1 composed of a ceramic substrate. ) are implemented and modularized.
  • This semiconductor chip (CHT1, CHT2) is composed of a single crystal semiconductor substrate such as silicon (Si) or a compound semiconductor substrate such as gallium arsenide (GaAs).
  • Field-effect transistors (FET1, FET2) are formed on the surface.
  • the surface of the semiconductor chip (CHT 2) in contact with the multilayer wiring board 1 is provided on both sides of the element forming region 6 with the gate electrode 7g, the source electrode 7s, and the drain, respectively.
  • An electrode 7d is provided.
  • the source electrode 7 s is formed in a comb tooth shape
  • the gate electrode 7 g is arranged between the comb teeth of the source electrode 7 s. Note that the region that substantially operates as an FET is shown as an active region AE in FIG. As shown in FIG.
  • the electrodes (gate electrode 7g, source electrode 7s, Corresponding to the drain electrode 7d), a gate wiring electrode 2g, a source wiring electrode 2s, and a drain wiring electrode 2d are formed, respectively.
  • the gate electrode 7 g, the source electrode 7 s and the drain electrode 7 d of the semiconductor chip (C HT 2) are connected to the gate wiring electrode 2 g of the multilayer wiring board 1 and the source wiring electrode via the bump electrode 3. 2s and drain wiring electrode 2d are electrically and mechanically connected.
  • the semiconductor chip (CHT 2) is mounted on the multilayer wiring board 1 as shown in FIG.
  • a plurality of bump electrodes 3 are provided on the source electrode 7 s and the drain electrode 7 d of the semiconductor chip (C HT 2).
  • the source wiring electrode 2 s and the gate wiring electrode 2 g on the multilayer wiring board 1 are formed in a comb-teeth shape, and a thermal via (therma 1 viahole) ( 4, 5) are formed.
  • the thermal via is also referred to as a through hole.
  • the thermal vias (4, 5) penetrate through the inside of the multilayer wiring board 1 and are provided up to the back surface layer of the multilayer wiring board 1, as shown in FIG. 6 (a).
  • the cross-sectional shape of the thermal via 4 in the first wiring layer (or the surface layer) of the multilayer wiring board 1 has an oval (or elliptical) shape.
  • the cross-sectional shape of the thermal via 5 in the second and subsequent wiring layers (or the inner layer and the back surface layer) of the multilayer wiring board 1 is formed in a circular shape.
  • the size of the cross-sectional shape of the thermal via 5 of the second and subsequent wiring layers is such that the elliptical shape (or elliptical shape) of the thermal via 4 of the first wiring layer is included in the circular shape.
  • a large drain current (IDS) flows between the source and drain of the field-effect transistor (FET 2).
  • IDS drain current
  • FET 2 field-effect transistor
  • Heat generation becomes a problem. That is, the characteristics of Si—FETs that use Si (silicon) as a semiconductor substrate deteriorate because the transconductance (gm) decreases as the temperature rises, and G a A as a semiconductor substrate. In G a A s — FETs that use s (gallium arsenide), thermal runaway occurs at elevated temperatures, and in the worst case, the FETs burst.
  • the thermal vias (4, 5) described above are used for the semiconductor chip (CHT2). It is provided to make it easier to dissipate the heat generated inside and to prevent the problems described above.
  • the thermal vias (4, 5) are formed in an elliptical (or elliptical) cross section in the first wiring layer of the multilayer wiring board 1. In the second and subsequent wiring layers, the cross-sectional shape is formed in a circular shape, whereby the heat radiation effect can be improved.
  • thermal vias (4, 5) are arranged immediately below the bump electrodes 3.
  • a thermal resistance corresponding to the shift is added, and efficient heat dissipation is difficult.
  • the heat generated inside the semiconductor chip (C HT 2) can be efficiently dissipated, so that the field effect transistor (TFT 2) Deterioration of characteristics or destruction of the field effect transistor (TFT 2) can be prevented, and the current value of the drain current (IDS) that can flow between the source and the drain of the field effect transistor (TFT 2) can be prevented. Since the width (difference between the maximum current value and the minimum current value) can be increased, the design margin can be improved.
  • each electrode (source electrode, gate electrode and drain electrode) of the semiconductor chip (CHT 2) and the multi-layer wiring board 1 are connected by wire bonding.
  • the formed wiring electrodes (source wiring electrode, gate wiring electrode, and drain wiring electrode) were electrically connected.
  • a predetermined distance is required between each electrode of the semiconductor chip (CHT 2) and the wiring electrode formed on the multilayer wiring board 1. Therefore, in the conventional power amplifier circuit module, when mounting the semiconductor chip (CHT2) on the multilayer wiring board 1, a large area (or area) is required, and there is a limit to the miniaturization of the power amplifier circuit module. there were.
  • the size can be 7 mm X 7 mm.
  • the present embodiment is suitable for a high-frequency circuit because the wiring length is shorter than that of wire bonding.
  • the thermal vias (4, 5) are formed on the teeth of the comb of the source wiring electrode 2s. This is because when a thermal via (4, 5) is formed at the connection of the comb teeth of the gate wiring electrode 2 g, the drain wiring electrode 2 d or the source wiring electrode 2 s, the field effect transistor (FET 2 This is because parasitic capacitance is added to the gate electrode or drain electrode of), which affects the amplification characteristics of the field-effect transistor (FET 2).
  • the source electrode of the field-effect transistor (FET 2) is at the ground potential (G ND), so that the thermal via (4, 5) Is formed on the teeth of the comb of the source wiring electrode 2 s without adversely affecting the amplification characteristics of the field-effect transistor (FET 2). If the amplification characteristics of the field-effect transistor (FET 2) are not affected, the thermal vias (4, 5) are connected to the gate wiring electrode 2g, the drain wiring electrode 2d, or the source wiring electrode 2d. It may be formed at the connecting portion of the teeth of the s comb.
  • the power amplification circuit module of the present embodiment is manufactured by the following method.
  • the green sheets (9a to 9e) are aligned and superimposed, and then each green sheet is heated and pressurized to thereby obtain a respective dust sheet.
  • (9a-9e) is sintered to form a multilayer wiring board 1 made of ceramic.
  • the ceramic substrate has a lower coefficient of linear expansion than silicon and GaAs and a lower stress than glass-epoxy substrates. Also, the dielectric constant is low.
  • the semiconductor chip C HT 2 on which the bump electrode 3 is formed is mounted on the multilayer wiring board 1, and is mounted by soldering.
  • the bump electrode 3 is formed, for example, by forming an Au wire on a semiconductor chip electrode by a ball bonding method and leaving only the ball portion of the Au wire.
  • the minimum pitch between bumps can be about 20 ⁇ m.
  • a chip such as a resistor or a capacitor is provided on the multilayer wiring board 1. Parts are also mounted by soldering.
  • FIG. 9 shows a specific example of the power amplifier circuit module of the present embodiment manufactured by the method shown in FIG.
  • the thermal via 4 in the first wiring layer of the multilayer wiring board 1 has an elliptical shape having a width of 0.1 mm and a length of 0.25 mm.
  • the thermal vias 5 in the wiring layers other than the first layer of the multilayer wiring board 1 were circular with a diameter of 0.25 mm, and the interval between the thermal vias 5 was 0.50 mm.
  • the bump electrode 3 was a circle having a diameter of 0.09 mm, and the interval between the bump electrodes 3 was 0.12 mm. Note that the thickness of the multilayer wiring board 1 is 0.5 mm.
  • the size of the thermal via (4, 5) is limited by the manufacturing process of the multilayer wiring board 1 (if the thermal via (4, 5) becomes large, the green sheet It is determined from the fact that the conductor paste comes off from the ground or the gap between the thermal vials (4, 5) becomes narrow, so that the green sheet cracks).
  • the formation of the through-holes in the multilayer ceramic substrate requires a margin for the alignment of the through-holes between the respective layers, so that it is difficult to match the pitch of the bump electrodes 3. Therefore, in the present invention, the diameter of the through hole is widened so that a plurality of bump electrodes 3 can be connected.
  • the size of the thermal vias (4, 5) can be made larger than that shown in FIG.
  • the size of Malvia (4, 5) is made larger than that shown in Fig. 9, the heat radiation effect can be further improved.
  • the pitch on the bump electrode side is widened, the area of the semiconductor chip itself becomes large, and miniaturization becomes difficult, which is not practical.
  • the circuit configuration shown in FIG. 10 or FIG. 11 is adopted as the circuit configuration of the power amplifier shown in FIG. Is also good.
  • a field effect transistor (FET 3) constitutes an active filter circuit.
  • the thermal via 4 may be the one shown in FIG.
  • the thermal via 4 shown in FIG. 12 has a half cross section of the thermal via (4a) formed on the source wiring electrodes 2 s at both ends in the first wiring layer of the multilayer wiring board 1. It has a circular shape. According to the thermal via (4 a) shown in FIG. 12, the area of the thermal via (4, 4 a) in the first wiring layer of the multilayer wiring board 1 is increased, so that the heat dissipation effect is further improved. Can be enhanced.
  • the mounting method of the semiconductor chip (C HT 2) and the multilayer wiring board 1 has been described as an example.
  • the present invention is not limited to this, and the present invention is shown in FIG. It goes without saying that the present invention is also applicable to a method of mounting the semiconductor chip (CHT 1) and the multilayer wiring board 1.
  • the present invention is not limited to this.
  • the invention as has been described can be applied in which c above semiconductor chip bipolar transistor is formed on a principal surface, the following advantages are provided according to the present embodiment.
  • a multilayer wiring board A thermal via (4, 5) penetrating to the lowermost wiring layer is formed in 1 and the source electrode 2s of the semiconductor chip (CHT1, CHT2) and the thermal via (4, 5) are bump electrodes. Since the connection is made electrically and mechanically via 3, heat generated inside the semiconductor chips (CHT 1 and CHT 2) can be efficiently dissipated.
  • the size of the power amplification circuit module of the mobile communication device can be further reduced, so that the size of the mobile communication device can be further reduced.

Abstract

Portable communication equipment provided with an antenna and a power amplifier circuit module for amplifying high-frequency signals emitted from the antenna, wherein the power amplifier circuit module is provided with a wiring board (1) and a semiconductor element (CHT) (2) which is mounted on the wiring board (1) and electrically and mechanically connected to the board (1) through a plurality of bump electrodes (3), characterized in that the substrate (1) has conductors (4 and 5) which are electrically and mechanically connected to part of the bump electrodes (3) and work as heat dissipating paths. The portable communication equipment is further characterized in that the wiring board (1) is constituted in a multilayered wiring board composed of multiple wiring layers and the conductors (4 and 5) used as the above heat dissipating paths are formed through each wiring layer of the multilayered wiring board, thereby further reducing the size of the power amplifier circuit module and, accordingly, the portable communication equipment.

Description

W /54  W / 54
明 細 書 携帯通信機器 技術分野 Description Mobile communication device Technical field
本発明は、 携帯通信機器に係わり、 特に、 アンテナと電力増幅回路モ ジュールとを搭載する自動車電話、 携帯電話等の携帯通信機器に適用し て有効な技術に関する。 背景技術  The present invention relates to a mobile communication device, and particularly to a technology effective when applied to a mobile communication device such as a mobile phone or a mobile phone equipped with an antenna and a power amplifier circuit module. Background art
近年、 P D C ( P e r s o n a l D i g i t a l C e l l u l a r ) 方式の自動車電話および携帯電話、 あるいは、 P H S ( P e r s o n a 1 H a n d y p h o n e S y s t e m) 方式の携帯電話等の携 帯通信機器が急速に普及している。 これら携帯通信機器は、 一般に、 電 波を放射し、 電波を受信するアンテナと、 アンテナに送信高周波信号を 供給し、 また、 アンテナで受信した受信高周波信号を中間周波数に変換 する無線部と、 音声信号処理および入出力制御を行うベースバン ド部で 構成される。 なお、 これら携帯通信機器の構成については、 例えば、 「日 立評論」 , v o l . 7 8, N o . 1 1 ( 1 9 9 6— 1 1 ) , p p 2 1 - 2 6に開示されている。  2. Description of the Related Art In recent years, mobile communication devices such as a PDC (Persona1Digitala1C1E1lullar) type mobile phone and a mobile phone such as a PHS (Persona1 1Handy phponesyms) type mobile phone have rapidly spread. In general, these portable communication devices emit an electric wave and receive an electric wave, an antenna for supplying a transmitting high-frequency signal to the antenna, a radio unit for converting a received high-frequency signal received by the antenna to an intermediate frequency, and a voice unit. It consists of a baseband unit that performs signal processing and input / output control. The configuration of these portable communication devices is disclosed in, for example, “Hitachi Review”, vol. 78, No. 11 (1996-1-11), and pp. 21-26. .
自動車電話、 携帯電話等の携帯通信機器の普及した原因は、 その小型、 軽量という特徴を活かし、 「何時でも、 何処でも、 誰とでも」 情報の交 換が可能になったことにある。 しかし、 この携帯通信機器のより一層の 普及を図るために、 携帯通信機器のさらなる小型化が要望されている。 この要望に応えるためには、 携帯通信機器の各構成部品のより一層の 小型化を実現する必要がある。 The widespread use of mobile communication devices such as mobile phones and mobile phones is due to their ability to exchange information "anytime, anywhere, with anyone" by taking advantage of their small size and light weight. However, there is a demand for further downsizing of the mobile communication device in order to further spread the use of the mobile communication device. In order to meet this demand, it is necessary to further reduce the size of each component of the mobile communication device.
上器構成部品の一つと して、 携帯通信機器の無線部内に設けられる電 力増幅回路モジュールがあるが、 この電力増幅回路モジュールを小型化 するためには、 増幅素子を構成する半導体チップの小型化が必須である。 しかしながら、 半導体チップを小さくすると、 半導体チップ内部で発生 する熱を外部へ放熱する能力が小さくなる。 この結果、 半導体チップ内 部で発生した熱により、 上記増幅素子の増幅特性に悪影響を与え、 携帯 通信機器の特性劣化を招く恐れがある。 そのため、 当該電力増幅回路モ ジュールのより一層の小型化を図ることが困難であるという問題点があ つた。  One of the components of the upper device is a power amplifier circuit module provided in the wireless section of a portable communication device. To reduce the size of this power amplifier circuit module, it is necessary to reduce the size of the semiconductor chip that constitutes the amplifier. Is essential. However, when the size of the semiconductor chip is reduced, the ability to radiate heat generated inside the semiconductor chip to the outside decreases. As a result, the heat generated inside the semiconductor chip adversely affects the amplification characteristics of the amplifying element, and may cause deterioration of the characteristics of the mobile communication device. For this reason, there is a problem that it is difficult to further reduce the size of the power amplification circuit module.
本発明は前記従来技術の問題点を解決するためになされたものであり、 本発明の目的は、 携帯通信機器において、 電力増幅回路モジュールのよ り一層の小型化を図り、 更なる小型化を図ることが可能となる技術を提 供することにある。  SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to further reduce the size of a power amplifier circuit module in a portable communication device, and to further reduce the size. The aim is to provide technologies that can be achieved.
本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述 及び添付図面によって明らかにする。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention
本願において開示される発明のうち、 代表的なものの概要を簡単に説 明すれば、 下記の通りである。  The following is a brief description of an outline of typical inventions disclosed in the present application.
( 1 ) アンテナと、 前記アンテナから放射する高周波信号を増幅する電 力増幅回路モジュールとを備える携帯通信機器であって、 前記電力増幅 回路モジュールは、 配線基板と、 前記配線基板上に搭載され、 複数のバ ンブ電極を介して前記配線基板に電気的、 機械的に接続される半導体チ ップとを有する携帯通信機器において、 前記配線基板は、 前記複数のバ ンプ電極の中の一部のバンプ電極と、 電気的および機械的に接続され、 放熱経路となる導体を有することを特徴とする。 (1) A portable communication device including an antenna and a power amplification circuit module for amplifying a high-frequency signal radiated from the antenna, wherein the power amplification circuit module is mounted on a wiring board, and on the wiring board, Multiple ba In a portable communication device having a semiconductor chip electrically and mechanically connected to the wiring board via a bump electrode, the wiring board is connected to a part of the plurality of bump electrodes by a bump electrode. It has a conductor that is electrically and mechanically connected and serves as a heat dissipation path.
( 2 ) 前記配線基板は、 配線層が多層に亘つて形成される多層配線基板 であって、 前記放熱経路となる導体は、 前記多層配線基板の各配線層を 貫通して形成されることを特徴とする。  (2) The wiring board is a multilayer wiring board in which wiring layers are formed over multiple layers, and the conductor serving as the heat dissipation path is formed to penetrate each wiring layer of the multilayer wiring board. Features.
( 3 ) 前記放熱経路となる導体は、 前記多層配線基板の前記バンプ電極 と接する配線層の断面形状が長円形あるいは楕円形であることを特徴と する。  (3) The conductor serving as the heat dissipation path is characterized in that a cross-sectional shape of a wiring layer in contact with the bump electrode of the multilayer wiring board is an ellipse or an ellipse.
( 4 ) 前記放熱経路となる導体は、 前記多層配線基板のバンプ電極と接 する配線層以外の配線層の断面積が、 前記多層配線基板の前記バンプ電 極と接する配線層の断面積よ り も大きいことを特徴とする。  (4) The cross-sectional area of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is larger than the cross-sectional area of the wiring layer in contact with the bump electrode of the multilayer wiring board. Is also large.
( 5 ) 前記多層配線基板のバンプ電極と接する配線層以外の配線層の断 面形状は、 円形であることを特徴とする。  (5) The cross-sectional shape of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is circular.
( 6 ) 前記半導体チップは、 半導体基板の一主面上に形成される電界効 果型 トランジスタであることを特徴とする。  (6) The semiconductor chip is a field-effect transistor formed on one main surface of a semiconductor substrate.
( 7 ) 前記放熱経路となる導体は、 電界効果型トランジスタのソース電 極に形成されるバンプ電極と電気的および機械的に接続されることを特 徴とする。  (7) The conductor serving as the heat dissipation path is electrically and mechanically connected to a bump electrode formed on a source electrode of the field effect transistor.
( 8 ) また、 アンテナと、 電力増幅回路モジュールとを有する携帯通信 機器であって、 前記電力增幅回路モジュールは、 複数の配線層と、 その 内部が金属層で充填された複数のスルーホールとを有する多層配線基板 と、 その主面に、 ゲー ト電極、 ソース電極およびドレイ ン電極を有する 電界効果トランジスタが形成された半導体チップであって、 前記主面が 前記多層配線基板と対向するように前記多層配線上に搭載された半導体 チップと、 前記半導体チップの前記ゲート電極、 ソース電極およびドレ イ ン電極の各々と、 前記多層配線基板の前記複数の配線層を電気的およ び機械的に接続する複数のバンプ電極とを有し、 前記半導体チップの前 記ソース電極に対向する位置に前記複数のスルーホールの少なく とも一 つが配置され、 前記ソース電極に対向する位置に配置されたスル一ホー ルの各々と前記ソース電極とは、 前記複数のバンプ電極を介して電気的 および機械的に接続されていることを特徴とする。 (8) Further, in a portable communication device having an antenna and a power amplification circuit module, the power amplification circuit module includes a plurality of wiring layers and a plurality of through holes whose inside is filled with a metal layer. Having a gate electrode, a source electrode, and a drain electrode on its main surface A semiconductor chip having a field-effect transistor formed thereon, the semiconductor chip being mounted on the multilayer wiring such that the main surface faces the multilayer wiring board; and the gate electrode, the source electrode, and the drain of the semiconductor chip. And a plurality of bump electrodes for electrically and mechanically connecting the plurality of wiring layers of the multilayer wiring board to each other, and at a position facing the source electrode of the semiconductor chip. At least one of the plurality of through holes is arranged, and each of the through holes arranged at a position facing the source electrode and the source electrode are electrically and mechanically connected via the plurality of bump electrodes. Is connected to the terminal.
( 9 ) 前記半導体チップは長方形形状を有し、 前記ソース電極は平面的 に前記半導体チップの長辺方向に沿って延在する第 1の部分と、 前記第 1 の部分から前記半導体チップの短辺方向に沿って延在する第 2の部分 とを有し、 前記ソース電極に接続された複数のバンプ電極は、 前記半導 体チップの短辺方向に沿って前記第 2の部分に接続されていることを特 徴とする。  (9) The semiconductor chip has a rectangular shape, and the source electrode has a first portion extending planarly along a long side direction of the semiconductor chip; and a short portion of the semiconductor chip extending from the first portion. A second portion extending along a side direction, wherein the plurality of bump electrodes connected to the source electrode are connected to the second portion along a short side direction of the semiconductor chip. It is characterized by that.
( 1 0 ) 前記多層配線基板はセラミ ックス基板であり、 前記複数のバン プ電極の配列可能な最小ピツチは、 前記複数のスルーホールの配列可能 な最小ピッチより小さいことを特徴とする。  (10) The multilayer wiring board is a ceramic board, and a minimum pitch at which the plurality of bump electrodes can be arranged is smaller than a minimum pitch at which the plurality of through holes can be arranged.
前記した手段によれば、 携帯通信機器の電力増幅回路モジュールにお いて、 配線基板上にフリ ップチップ方式で半導体チップを実装し、 また、 配線基板に放熱経路となる導体を設け、 当該放熱経路となる導体をバン プ電極に電気的、 機械的に接続し、 前記半導体チップの内部で発生する 熱を効率良く放熱することができるので、 高周波電力増幅回路モジユー ルをより一層の小型化を図ることができ、 それにより、 携帯通信機器の より一層の小型化を図ることが可能となる。 図面の簡単な説明 According to the above-described means, in a power amplification circuit module of a portable communication device, a semiconductor chip is mounted on a wiring board by a flip-chip method, and a conductor serving as a heat dissipation path is provided on the wiring board, and the heat dissipation path is provided. Can be electrically and mechanically connected to the bump electrode, and the heat generated inside the semiconductor chip can be efficiently radiated, so that the high-frequency power amplifier module can be further miniaturized. And thereby the mobile communication device It is possible to further reduce the size. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の一実施形態である携帯電話の概略構成を示すプロ ック図である。  FIG. 1 is a block diagram showing a schematic configuration of a mobile phone according to an embodiment of the present invention.
第 2図は、 第 1図に示す電力増幅器の回路構成の一例を示す回路図で ある。  FIG. 2 is a circuit diagram showing an example of a circuit configuration of the power amplifier shown in FIG.
第 3図は、 第 2図に示す回路構成をモジュール化した電力増幅回路モ ジュールの上平面図である。  FIG. 3 is a top plan view of a power amplifier circuit module in which the circuit configuration shown in FIG. 2 is modularized.
第 4図は、 本実施の形態において、 半導体チップ (CHT 2 ) の多層 配線基板への実装方法を説明するための図である。  FIG. 4 is a diagram for explaining a method of mounting a semiconductor chip (CHT 2) on a multilayer wiring board in the present embodiment.
第 5図は、 本実施形態において、 半導体チップ (C HT 2 ) を多層配 線基板に実装した状態を示す図である。  FIG. 5 is a diagram showing a state in which a semiconductor chip (CHT 2) is mounted on a multilayer wiring board in the present embodiment.
第 6図は、 本実施の形態において、 半導体チップ (CHT 2 ) を実装 した多層配線基板の要部断面図である。  FIG. 6 is a cross-sectional view of a main part of a multilayer wiring board on which a semiconductor chip (CHT 2) is mounted in the present embodiment.
第 7図は、 従来の電力増幅回路モジュールの上平面図である。  FIG. 7 is a top plan view of a conventional power amplifier circuit module.
第 8図は、 本実施形態の電力増幅回路モジュールの製造方法を説明す るための図である。  FIG. 8 is a diagram for explaining a method of manufacturing the power amplification circuit module of the present embodiment.
第 9図は、 本実施形態の電力増幅回路モジュールの一具体例を示す図 である。  FIG. 9 is a diagram showing a specific example of the power amplification circuit module of the present embodiment.
第 1 0図は、 第 1図に示す電力増幅器の回路構成の他の例を示す回路 図である。  FIG. 10 is a circuit diagram showing another example of the circuit configuration of the power amplifier shown in FIG.
第 1 1図は、 第 1図に示す電力増幅器の回路構成の他の例を示す回路 図である。 第 1 2図は、 本実施形態のサーマルヴィァ (スルーホール) の変形例 を示す図である。 発明を実施するための最良の形態 FIG. 11 is a circuit diagram showing another example of the circuit configuration of the power amplifier shown in FIG. FIG. 12 is a diagram showing a modification of the thermal via (through hole) of the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 図面を参照して本発明の実施形態を詳細に説明する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
なお、 実施形態を説明するための全図において、 同一機能を有するも のは同一符号を付け、 その繰り返しの説明は省略する。  In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.
第 1図に示すように、 本実施形態の携帯電話は、 電波を放射し、 電波 を受信するアンテナ 1 0 と、 アンテナ 1 0に送信高周波信号を供給し、 また、 アンテナ 1 0で受信した受信高周波信号を中間周波数に変換する 無線部 2 0 と、 ベースバン ド部 3 0 とで構成される。 ここで、 無線部 2 0は、 高周波部 1 2 0 と、 低周波部 1 3 0 とから構成される。  As shown in FIG. 1, the mobile phone according to the present embodiment emits radio waves, supplies an antenna 10 for receiving radio waves, a high-frequency signal to the antenna 10, and a reception signal received by the antenna 10. It comprises a radio section 20 for converting a high-frequency signal to an intermediate frequency and a baseband section 30. Here, the radio section 20 includes a high frequency section 120 and a low frequency section 130.
高周波部 1 2 0は、 送信ミキサ 1 2 3、 送信ミキサ 1 2 3から出力さ れる送信高周波信号の電力を増幅する電力増幅器 (高周波電力増幅回路 モジュール) 1 2 2 と、 アンテナ 1 0を送信側と受信側とに切り替える アンテナスィ ッチ 1 2 1 と、 アンテナ 1 0で受信した受信高周波信号を 増幅する低雑音増幅器 1 2 4 と、 受信ミキサ 1 2 5 とで構成される。 ま た、 低周波部 1 3 0は、 直交変調器 1 3 1 と、 周波数シンセサイザ 1 3 2 と、 中間周波増幅器 1 3 3 とで構成される。 ベースバンド部 3 0は、 音声信号処理および入出力制御を行う。  The high-frequency section 120 is composed of a power mixer (high-frequency power amplifier circuit module) 122 that amplifies the power of the transmission high-frequency signal output from the transmission mixer 123 and the transmission mixer 123, and an antenna 110 on the transmission side. And a receiving side, an antenna switch 122, a low noise amplifier 124 for amplifying a high frequency signal received by the antenna 10, and a receiving mixer 125. Further, the low frequency section 130 is composed of a quadrature modulator 131, a frequency synthesizer 132, and an intermediate frequency amplifier 133. The baseband unit 30 performs audio signal processing and input / output control.
第 2図の回路図に示すように、 第 1図に示す電力増幅器 1 2 2は、 増 幅素子と して電界効果型トランジスタ (F E T 1, F E T 2 ) を使用す る。 なお、 この第 2に示す回路は、 ソ一ス接地回路構成の F E T増幅回 路を 2段に縦続接続した 2段構成の電力増幅器である。 また、 第 3図に示すように、 第 1図に示す電力増幅器は、 セラミ ック 基板から成る多層配線基板上 1に、 抵抗、 コンデンサ等のチップ部品 C Hと、 半導体チップ (CHT 1, CHT 2 ) とが実装され、 モジュール ィ匕されてレヽる。 この半導体チップ (CHT 1, C HT 2 ) は、 シリ コ ン ( S i ) 等の単結晶半導体基板、 あるいはひ化ガリ ウム (G a A s ) 等 の化合物半導体基板で構成され、 その一主面上に電界効果型トランジス タ (F E T 1, F E T 2 ) が形成される。 As shown in the circuit diagram of FIG. 2, the power amplifier 122 shown in FIG. 1 uses field-effect transistors (FET1, FET2) as the amplification elements. The second circuit is a power amplifier having a two-stage configuration in which an FET amplification circuit having a source ground circuit configuration is cascaded in two stages. As shown in FIG. 3, the power amplifier shown in FIG. 1 includes a chip component CH such as a resistor and a capacitor and a semiconductor chip (CHT 1 and CHT 2) on a multilayer wiring board 1 composed of a ceramic substrate. ) Are implemented and modularized. This semiconductor chip (CHT1, CHT2) is composed of a single crystal semiconductor substrate such as silicon (Si) or a compound semiconductor substrate such as gallium arsenide (GaAs). Field-effect transistors (FET1, FET2) are formed on the surface.
次に、 第 4図を参照して、 半導体チップ (C HT 2 ) と多層配線基板 1 との実装方法について説明する。 第 4図 ( a ) に示すように、 半導体 チップ (CHT 2 ) の、 多層配線基板 1 と接する面には、 素子形成領域 6の両側に、 それぞれゲー ト電極 7 g、 ソース電極 7 sおよびドレイ ン 電極 7 dが設けられる。 ここで、 ソース電極 7 sは櫛の歯状に形成され、 ソース電極 7 sの櫛の歯の間に、 ゲート電極 7 gが配置される。 なお、 実質的に F E Tと して動作する領域を同図中に活性領域 A Eと して示す。 第 4図 ( b ) に示すように、 セラミ ック基板から成る多層配線基板 1 の最上層の面には、 半導体チップ (C HT 2 ) の各電極 (ゲート電極 7 g、 ソース電極 7 sおよびドレイ ン電極 7 d ) と対応して、 それぞれ、 ゲ一 ト配線電極 2 g、 ソース配線電極 2 sおよびドレイ ン配線電極 2 d が形成される。 そして、 半導体チップ (C HT 2 ) のゲー ト電極 7 g、 ソース電極 7 sおよびドレイ ン電極 7 dは、 バンプ電極 3を介して、 多 層配線基板 1 のゲート配線電極 2 g、 ソース配線電極 2 sおよびドレイ ン配線電極 2 dに電気的、 機械的に接続される。 これにより、 第 5図に 示すように、 多層配線基板 1上に半導体チップ (C HT 2 ) が実装され る。 ここで、 半導体チップ (C HT 2 ) のソース電極 7 sおよびドレイ ン 電極 7 dには、 複数のバンプ電極 3が設けられる。 また、 多層配線基板 1上のソース配線電極 2 s とゲート配線電極 2 g とは、 櫛の歯状に形成 され、 ソース配線電極 2 sの櫛の歯部分には、 サーマルヴィァ ( t h e r m a 1 v i a h o l e ) ( 4, 5 ) が形成される。 以下、 サ一マ ルヴィァをスルーホールとも称する。 Next, a method of mounting the semiconductor chip (C HT 2) and the multilayer wiring board 1 will be described with reference to FIG. As shown in FIG. 4 (a), the surface of the semiconductor chip (CHT 2) in contact with the multilayer wiring board 1 is provided on both sides of the element forming region 6 with the gate electrode 7g, the source electrode 7s, and the drain, respectively. An electrode 7d is provided. Here, the source electrode 7 s is formed in a comb tooth shape, and the gate electrode 7 g is arranged between the comb teeth of the source electrode 7 s. Note that the region that substantially operates as an FET is shown as an active region AE in FIG. As shown in FIG. 4 (b), on the uppermost surface of the multilayer wiring board 1 composed of a ceramic substrate, the electrodes (gate electrode 7g, source electrode 7s, Corresponding to the drain electrode 7d), a gate wiring electrode 2g, a source wiring electrode 2s, and a drain wiring electrode 2d are formed, respectively. The gate electrode 7 g, the source electrode 7 s and the drain electrode 7 d of the semiconductor chip (C HT 2) are connected to the gate wiring electrode 2 g of the multilayer wiring board 1 and the source wiring electrode via the bump electrode 3. 2s and drain wiring electrode 2d are electrically and mechanically connected. Thereby, the semiconductor chip (CHT 2) is mounted on the multilayer wiring board 1 as shown in FIG. Here, a plurality of bump electrodes 3 are provided on the source electrode 7 s and the drain electrode 7 d of the semiconductor chip (C HT 2). The source wiring electrode 2 s and the gate wiring electrode 2 g on the multilayer wiring board 1 are formed in a comb-teeth shape, and a thermal via (therma 1 viahole) ( 4, 5) are formed. Hereinafter, the thermal via is also referred to as a through hole.
このサ一マルヴィァ (4, 5 ) は、 第 6図 ( a ) に示すように、 多層 配線基板 1の内部を貫通して多層配線基板 1 の裏面層まで設けられる。 この場合に、 第 6図 ( b ) に示すように、 多層配線基板 1の第 1層 (ま たは表面層) 目の配線層におけるサーマルヴィァ 4の断面形状は長円形 状 (あるいは楕円形状) に形成されるが、 多層配線基板 1の第 2層目 (ま たは内層 +裏面層) 以降の配線層におけるサーマルヴィァ 5の断面形状 は円形状に形成される。 この第 2層目以降の配線層のサーマルヴィァ 5 の断面形状の大きさは、 当該円形状内に、 第 1層目の配線層のサーマル ヴィァ 4の長円形状 (あるいは楕円形状) が含まれるようにされる。 電力増幅器では、大信号を取り扱うため、電界効果型トランジスタ ( F E T 2 ) のソース ' ドレイ ン間には、 大電流の ドレイ ン電流 ( I D S ) が流れるので、 半導体チップ (C HT 2 ) 内部での発熱が問題となる。 即ち、 半導体基板と して S i (シリ コン) を使用する S i — F E Tでは、 温度が上昇すると相互コンダクタンス ( g m) が低下するので特性が劣 化し、 また、 半導体基板と して G a A s (ひ化ガリ ウム) を使用する G a A s — F E Tでは、 温度が上昇すると熱暴走が起こり、 最悪の場合に は F E Tが破壌される。  The thermal vias (4, 5) penetrate through the inside of the multilayer wiring board 1 and are provided up to the back surface layer of the multilayer wiring board 1, as shown in FIG. 6 (a). In this case, as shown in FIG. 6 (b), the cross-sectional shape of the thermal via 4 in the first wiring layer (or the surface layer) of the multilayer wiring board 1 has an oval (or elliptical) shape. However, the cross-sectional shape of the thermal via 5 in the second and subsequent wiring layers (or the inner layer and the back surface layer) of the multilayer wiring board 1 is formed in a circular shape. The size of the cross-sectional shape of the thermal via 5 of the second and subsequent wiring layers is such that the elliptical shape (or elliptical shape) of the thermal via 4 of the first wiring layer is included in the circular shape. To be. Since power amplifiers handle large signals, a large drain current (IDS) flows between the source and drain of the field-effect transistor (FET 2). Heat generation becomes a problem. That is, the characteristics of Si—FETs that use Si (silicon) as a semiconductor substrate deteriorate because the transconductance (gm) decreases as the temperature rises, and G a A as a semiconductor substrate. In G a A s — FETs that use s (gallium arsenide), thermal runaway occurs at elevated temperatures, and in the worst case, the FETs burst.
前記したサーマルヴィァ (4, 5 ) は、 半導体チップ (C HT 2 ) の 内部で発生する熱を放熱し易く して、 前記したような問題を防止するた めに設けられる。 そして、 このサーマルヴィァ (4, 5 ) は、 多層配線 基板 1の第 1層目の配線層においては、 その断面形状は長円形状 (ある いは楕円形状) に形成され、 また、 多層配線基板 1の第 2層目以降の配 線層においては、 その断面形状は円形状に形成され、 これにより、 放熱 効果を向上させることができる。 The thermal vias (4, 5) described above are used for the semiconductor chip (CHT2). It is provided to make it easier to dissipate the heat generated inside and to prevent the problems described above. The thermal vias (4, 5) are formed in an elliptical (or elliptical) cross section in the first wiring layer of the multilayer wiring board 1. In the second and subsequent wiring layers, the cross-sectional shape is formed in a circular shape, whereby the heat radiation effect can be improved.
ここで、 重要なことは、 サ一マルヴィァ (4, 5 ) がバンプ電極 3の 直下に配置されることである。 サーマルヴィァ (4, 5 ) とバンプ電極 3の位置がずれる場合には、 そのずれ分に相当する熱抵抗が付加される ことになり、 効率的な放熱が困難である。  What is important here is that the thermal vias (4, 5) are arranged immediately below the bump electrodes 3. When the positions of the thermal vias (4, 5) and the bump electrode 3 are shifted, a thermal resistance corresponding to the shift is added, and efficient heat dissipation is difficult.
このよ うに、 本実施形態の電力増幅回路モジュールでは、 半導体チッ プ (C HT 2 ) の内部で発生する熱を効率良く放熱することが可能とな るので、 電界効果型トランジスタ (T F T 2 ) の特性劣化、 あるいは、 電界効果型トランジスタ (T F T 2 ) の破壊等を防止でき、 さらに、 電 界効果型トランジスタ (T F T 2 ) のソース . ドレイ ン間に流せる ド レ イン電流 ( I D S ) の電流値の幅 (最大電流値と最小電流値との差) を 大きくできるので、 設計マージンを向上させることが可能となる。  As described above, in the power amplifier circuit module of the present embodiment, the heat generated inside the semiconductor chip (C HT 2) can be efficiently dissipated, so that the field effect transistor (TFT 2) Deterioration of characteristics or destruction of the field effect transistor (TFT 2) can be prevented, and the current value of the drain current (IDS) that can flow between the source and the drain of the field effect transistor (TFT 2) can be prevented. Since the width (difference between the maximum current value and the minimum current value) can be increased, the design margin can be improved.
比較のために、 従来の電力増幅回路モジュールにおける、 半導体チッ プ (C HT 2 ) と多層多層配線基板 1 との実装方法を、 第 7図を用いて 説明する。 第 7図に示すように、 従来の電力増幅回路モジュールでは、 ワイヤボンディングにより、 半導体チップ (C HT 2 ) の各電極 (ソー ス電極、 ゲート電極およびドレイ ン電極) と、 多層配線基板 1上に形成 される配線電極 (ソース配線電極、 ゲート配線電極およびドレイ ン配線 電極) とを電気的に接続していた。 このワイヤボンディングでは、 半導体チップ (C HT 2 ) の各電極と 多層配線基板 1上に形成される配線電極との間に所定の距離が必要とな る。 そのため、 従来の電力増幅回路モジュールでは、 半導体チップ (C HT 2 ) を多層配線基板 1上に実装する場合に、 大きな領域 (または面 積) が必要となり、 電力増幅回路モジュールの小型化に限界があった。 For comparison, a method of mounting the semiconductor chip (C HT 2) and the multilayer wiring board 1 in a conventional power amplifier circuit module will be described with reference to FIG. As shown in FIG. 7, in the conventional power amplifier circuit module, each electrode (source electrode, gate electrode and drain electrode) of the semiconductor chip (CHT 2) and the multi-layer wiring board 1 are connected by wire bonding. The formed wiring electrodes (source wiring electrode, gate wiring electrode, and drain wiring electrode) were electrically connected. In this wire bonding, a predetermined distance is required between each electrode of the semiconductor chip (CHT 2) and the wiring electrode formed on the multilayer wiring board 1. Therefore, in the conventional power amplifier circuit module, when mounting the semiconductor chip (CHT2) on the multilayer wiring board 1, a large area (or area) is required, and there is a limit to the miniaturization of the power amplifier circuit module. there were.
第 7図に示すように、 例えば、 従来の電力増幅回路モジュールが、 1 0 mm X 1 O mmの大きさである場合、 本実施形態の電力増幅回路モジ ユールによれば、 第 3図に示すように、 例えば、 7 m m X 7 m mの大き さにすることができる。 このように、 本実施形態の電力増幅回路モジュ ールによれば、 より小型化を図ることが可能である。 さらに、 本実施形 態は、 ワイヤボンデンイングに比して配線長が短いので、 高周波回路に 適している。  As shown in FIG. 7, for example, when a conventional power amplifier circuit module has a size of 10 mm × 10 mm, according to the power amplifier circuit module of the present embodiment, as shown in FIG. Thus, for example, the size can be 7 mm X 7 mm. Thus, according to the power amplification circuit module of the present embodiment, it is possible to further reduce the size. Further, the present embodiment is suitable for a high-frequency circuit because the wiring length is shorter than that of wire bonding.
また、 本実施形態では、 サ一マルヴィァ (4, 5 ) を、 ソース配線電 極 2 sの櫛の歯部分に形成する。 これは、 サ一マルヴィァ (4, 5 ) を、 ゲー ト配線電極 2 g、 ドレイ ン配線電極 2 dあるいはソース配線電極 2 sの櫛の歯の連結部分に形成すると、 電界効果型トランジスタ ( F E T 2 ) のゲート電極、 あるいはドレイ ン電極に、 寄生容量が付加されるこ とになり、 電界効果型トランジスタ ( F E T 2 ) の増幅特性に影響を与 えるためである。  In this embodiment, the thermal vias (4, 5) are formed on the teeth of the comb of the source wiring electrode 2s. This is because when a thermal via (4, 5) is formed at the connection of the comb teeth of the gate wiring electrode 2 g, the drain wiring electrode 2 d or the source wiring electrode 2 s, the field effect transistor (FET 2 This is because parasitic capacitance is added to the gate electrode or drain electrode of), which affects the amplification characteristics of the field-effect transistor (FET 2).
しかしながら、 第 2図の回路図から分かるように、 電界効果型トラン ジスタ (F E T 2 ) のソース電極は接地電位 (G ND) とされるので、 本実施形態のように、 サーマルヴィァ (4, 5 ) を、 ソース配線電極 2 sの櫛の歯部分に形成しても、 電界効果型トランジスタ (F E T 2 ) の 増幅特性に好ましくない影響を与えることはない。 なお、 電界効果型トランジスタ (F E T 2 ) の増幅特性に影響がでな い場合であれば、 サーマルヴィァ ( 4, 5 ) を、 ゲー ト配線電極 2 g、 ドレイ ン配線電極 2 dあるいはソース配線電極 2 sの櫛の歯の連結部分 に形成してもよい。 However, as can be seen from the circuit diagram of FIG. 2, the source electrode of the field-effect transistor (FET 2) is at the ground potential (G ND), so that the thermal via (4, 5) Is formed on the teeth of the comb of the source wiring electrode 2 s without adversely affecting the amplification characteristics of the field-effect transistor (FET 2). If the amplification characteristics of the field-effect transistor (FET 2) are not affected, the thermal vias (4, 5) are connected to the gate wiring electrode 2g, the drain wiring electrode 2d, or the source wiring electrode 2d. It may be formed at the connecting portion of the teeth of the s comb.
本実施形態の電力増幅回路モジュールは、 以下の方法により製造され る。  The power amplification circuit module of the present embodiment is manufactured by the following method.
始めに、 第 8図 ( a ) に示すように、 銀ペース トあるいは銅ペース ト 用いて、 配線パターン ( 2 g, 2 s, 2 d ) およびサーマルヴィァ ( 4, 5 ) を形成した各層毎のグリーンシー ト ( 9 a〜 9 e ) を用意する。 な お、 第 8図では、 第 1層目の配線層のみ図示し、 それ以外の層の配線層 は図示を省略している。  First, as shown in Fig. 8 (a), using a silver paste or a copper paste, the green for each layer on which the wiring patterns (2g, 2s, 2d) and thermal vias (4, 5) are formed Prepare sheets (9a to 9e). In FIG. 8, only the first wiring layer is shown, and other wiring layers are not shown.
次に、 第 8図 ( b ) に示すよ うに、 各グリーンシー ト ( 9 a〜 9 e ) を位置合わせして重ね合わせた後、 加圧 · 加熱することによ り、 各ダリ —ンシー ト ( 9 a〜 9 e ) を焼結してセラ ミ ックからなる多層配線基板 1 を形成する。 セラ ミ ック基板は、 ガラス · エポキシ基板に比べ、 線膨 張係数がシリ コン、 G a A s に近く 、 応力が少なく レ、。 また、 誘電率も 低い。  Next, as shown in Fig. 8 (b), the green sheets (9a to 9e) are aligned and superimposed, and then each green sheet is heated and pressurized to thereby obtain a respective dust sheet. (9a-9e) is sintered to form a multilayer wiring board 1 made of ceramic. The ceramic substrate has a lower coefficient of linear expansion than silicon and GaAs and a lower stress than glass-epoxy substrates. Also, the dielectric constant is low.
最後に、 第 8図 ( c ) に示すよ うに、 前記多層配線基板 1 上に、 バン プ電極 3 を形成した半導体チップ C HT 2 とを搭載し、 半田付けして実 装する。 バンプ電極 3は、 例えば、 A uワイヤを半導体チップの電極上 にボールボンディ ング法で形成した後、 前記 A uワイャのボール部分の みを残すことによって形成する。 この場合、 バンプ間の最小ピッチは、 2 0 μ m程度にすることが可能である。 なお、 第 8図 ( c ) には図示し ていないが、 この多層配線基板 1 上には、 抵抗、 コンデンサ等のチップ 部品も半田付けして実装される。 Finally, as shown in FIG. 8 (c), the semiconductor chip C HT 2 on which the bump electrode 3 is formed is mounted on the multilayer wiring board 1, and is mounted by soldering. The bump electrode 3 is formed, for example, by forming an Au wire on a semiconductor chip electrode by a ball bonding method and leaving only the ball portion of the Au wire. In this case, the minimum pitch between bumps can be about 20 μm. Although not shown in FIG. 8 (c), a chip such as a resistor or a capacitor is provided on the multilayer wiring board 1. Parts are also mounted by soldering.
第 8図に示す方法により製造された本実施形態の電力増幅回路モジュ 一ルのー具体例を第 9図に示す。 この第 9図に示す具体例では、 多層配 線基板 1 の第 1層目の配線層におけるサーマルヴィァ 4は、 幅が 0. 1 mm、 長さが 0. 2 5 mmの長円形とし、 また、 多層配線基板 1の第 1 層目以外の配線層におけるサ一マルヴィァ 5は、 直径が 0. 2 5 mmの 円形と し、 サーマルヴィァ 5の間隔は 0. 5 0 m mと した。 また、 バン プ電極 3は、 直径が 0. 0 9 mmの円形と し、 このバンプ電極 3の間隔 は 0. 1 2 mmと した。 なお、 多層配線基板 1の厚さは、 0. 5 mmで ある。  FIG. 9 shows a specific example of the power amplifier circuit module of the present embodiment manufactured by the method shown in FIG. In the specific example shown in FIG. 9, the thermal via 4 in the first wiring layer of the multilayer wiring board 1 has an elliptical shape having a width of 0.1 mm and a length of 0.25 mm. The thermal vias 5 in the wiring layers other than the first layer of the multilayer wiring board 1 were circular with a diameter of 0.25 mm, and the interval between the thermal vias 5 was 0.50 mm. The bump electrode 3 was a circle having a diameter of 0.09 mm, and the interval between the bump electrodes 3 was 0.12 mm. Note that the thickness of the multilayer wiring board 1 is 0.5 mm.
なお、 この第 9図に示す具体例において、 サ一マルヴィァ (4, 5 ) の大きさは、 多層配線基板 1の製造工程上の制限 (サ一マルヴィァ ( 4, 5 ) が大きくなると、 グリーンシートから導体ペース トが抜け落ちる、 あるいは、 サ一マルヴィァ (4, 5 ) の間隔が狭く なると、 グリーンシ —トにひび割れが生じる等) から決定されたものである。  In the specific example shown in FIG. 9, the size of the thermal via (4, 5) is limited by the manufacturing process of the multilayer wiring board 1 (if the thermal via (4, 5) becomes large, the green sheet It is determined from the fact that the conductor paste comes off from the ground or the gap between the thermal vials (4, 5) becomes narrow, so that the green sheet cracks).
また、 多層セラミ ック基板におけるスルーホールの形成は、 各層間に おいて、 スルーホールの位置合わせのマージンが必要となるので、 バン プ電極 3のピッチに合わせることが困難である。 そこで、 本発明におい ては、 スルーホール径を複数のバンプ電極 3が接続できるように広く し てある。  Also, the formation of the through-holes in the multilayer ceramic substrate requires a margin for the alignment of the through-holes between the respective layers, so that it is difficult to match the pitch of the bump electrodes 3. Therefore, in the present invention, the diameter of the through hole is widened so that a plurality of bump electrodes 3 can be connected.
多層配線基板 1 の製造工程上の制限がない、 あるいは緩和される場合 には、 サ一マルヴィァ (4, 5 ) の大きさは第 9図に示すものよ り大き くすることができ、 サ一マルヴィァ (4, 5 ) の大きさを第 9図に示す ものより大きく した場合は、 より放熱効果を向上させることができる。 逆に、 バンプ電極側のピッチを広く してしまう と、 半導体チップ自体の 面積が大きくなり小型化が困難になってしまうので現実的でない。 If there are no or less restrictions on the manufacturing process of the multilayer wiring board 1, the size of the thermal vias (4, 5) can be made larger than that shown in FIG. When the size of Malvia (4, 5) is made larger than that shown in Fig. 9, the heat radiation effect can be further improved. Conversely, if the pitch on the bump electrode side is widened, the area of the semiconductor chip itself becomes large, and miniaturization becomes difficult, which is not practical.
なお、 本実施形態において、 第 1図に示す電力増幅器の回路構成と し ては、 第 2図に示す回路構成以外に、 第 1 0図または第 1 1図に示す回 路構成を採用してもよい。  In this embodiment, in addition to the circuit configuration shown in FIG. 2, the circuit configuration shown in FIG. 10 or FIG. 11 is adopted as the circuit configuration of the power amplifier shown in FIG. Is also good.
この第 1 1図において、 電界効果型トランジスタ (F E T 3 ) は、 ァ クティブフィルタ回路を構成するものである。  In FIG. 11, a field effect transistor (FET 3) constitutes an active filter circuit.
また、 本実施形態において、 サーマルヴィァ 4 として、 第 1 2図に示 すものを使用してもよい。 この第 1 2図に示すサ一マルヴィァ 4は、 多 層配線基板 1 の第 1層目の配線層における両端のソース配線電極 2 s に 形成されるサ一マルヴィァ (4 a ) の断面形状を半円形状にしたもので ある。 第 1 2図に示すサーマルヴィァ (4 a ) によれば、 多層配線基板 1の第 1層目の配線層におけるサ一マルヴィァ (4, 4 a ) の面積が大 きくなるので、 より一層放熱効果を高めることができる。  In this embodiment, the thermal via 4 may be the one shown in FIG. The thermal via 4 shown in FIG. 12 has a half cross section of the thermal via (4a) formed on the source wiring electrodes 2 s at both ends in the first wiring layer of the multilayer wiring board 1. It has a circular shape. According to the thermal via (4 a) shown in FIG. 12, the area of the thermal via (4, 4 a) in the first wiring layer of the multilayer wiring board 1 is increased, so that the heat dissipation effect is further improved. Can be enhanced.
また、 本実施形態では、 半導体チップ (C HT 2 ) と多層配線基板 1 との実装方法を例に挙げて説明したが、 本発明はこれに限定されず、 本 発明は、 第 2図に示す半導体チップ (C HT 1 ) と多層配線基板 1 との 実装方法にも適用可能であることは言うまでもない。  Further, in the present embodiment, the mounting method of the semiconductor chip (C HT 2) and the multilayer wiring board 1 has been described as an example. However, the present invention is not limited to this, and the present invention is shown in FIG. It goes without saying that the present invention is also applicable to a method of mounting the semiconductor chip (CHT 1) and the multilayer wiring board 1.
さらに、 本実施形態では、 一主面上に電界効果型トランジスタ ( F E T 1 , F E T 2 ) が形成される半導体チップ (C HT 2 ) の場合につい て説明したが、 これに限定されるものではなく、 本発明は、 一主面上に バイポーラ トランジスタが形成される半導体チップにも適用可能である c 以上説明したように、 本実施形態によれば以下の効果が得られる。 ( 1 ) 携帯通信機器の電力増幅回路モジュールにおいて、 多層配線基板 1 内に最下層の配線層まで貫通するサーマルヴィァ (4, 5 ) を形成し、 半導体チップ (CHT 1, C HT 2 ) のソース電極 2 s と、 サーマルヴ ィァ (4 , 5 ) とをバンプ電極 3 を介して電気的、 機械的に接続するよ うにしたので、 半導体チップ (CHT 1, C H T 2 ) の内部で発生する 熱を効率良く放熱することが可能となる。 Further, in the present embodiment, the case of the semiconductor chip (C HT 2) in which the field effect transistors (FET 1, FET 2) are formed on one main surface has been described, but the present invention is not limited to this. the invention, as has been described can be applied in which c above semiconductor chip bipolar transistor is formed on a principal surface, the following advantages are provided according to the present embodiment. (1) In a power amplifier circuit module for portable communication equipment, a multilayer wiring board A thermal via (4, 5) penetrating to the lowermost wiring layer is formed in 1 and the source electrode 2s of the semiconductor chip (CHT1, CHT2) and the thermal via (4, 5) are bump electrodes. Since the connection is made electrically and mechanically via 3, heat generated inside the semiconductor chips (CHT 1 and CHT 2) can be efficiently dissipated.
これによ り、 携帯通信機器の電力増幅回路モジュールのよ り一層の小 型化を図ることができるので、 携帯通信機器のよ り一層の小型化を図る ことが可能となる。  As a result, the size of the power amplification circuit module of the mobile communication device can be further reduced, so that the size of the mobile communication device can be further reduced.
( 2 ) 携帯通信機器の電力増幅回路モジュールにおいて、 半導体チップ (C HT 1, C HT 2 ) の内部で発生する熱を効率良く放熱することが 可能となるので、 電力増幅回路の設計マ一ジンを向上させることが可能 となる。  (2) In a power amplifier circuit module of a portable communication device, heat generated inside the semiconductor chip (CHT1, CHT2) can be efficiently dissipated. Can be improved.
以上、 本発明者によってなされた発明を、 前記実施形態に基づき具体 的に説明したが、 本発明は、 前記実施形態に限定されるものではなく 、 その要旨を逸脱しない範囲において種々変更可能であることは勿論であ る。 産業上の利用可能性  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Of course. Industrial applicability
本願において開示される発明のうち代表的なものによって得られる効 果を簡単に説明すれば、 下記の通りである。  The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
本発明によれば、 携帯通信機器のより一層の小型化を図ることが可能 となる。  According to the present invention, it is possible to further reduce the size of a portable communication device.

Claims

請 求 の 範 囲 The scope of the claims
1 . アンテナと、 前記アンテナから放射する高周波信号を増幅する電 力増幅回路モジュールとを備える携帯通信機器であって、  1. A portable communication device comprising: an antenna; and a power amplification circuit module for amplifying a high-frequency signal radiated from the antenna,
前記電力増幅回路モジュールは、  The power amplification circuit module,
配線基板と、  A wiring board,
前記配線基板上に搭載され、 複数のバンプ電極を介して前記配線基板 に電気的、 機械的に接続される半導体チップとを有する携帯通信機器に おいて、  A portable communication device having a semiconductor chip mounted on the wiring board and electrically and mechanically connected to the wiring board via a plurality of bump electrodes;
前記配線基板は、 前記複数のバンプ電極の中の一部のバンプ電極と、 電気的、 機械的に接続され、 放熱経路となる導体を有することを特徴と する携帯通信機器。  The portable communication device, wherein the wiring board has a conductor that is electrically and mechanically connected to a part of the plurality of bump electrodes and serves as a heat radiation path.
2 . 前記配線基板は、 配線層が多層に亘つて形成される多層配線基板 であって、  2. The wiring board is a multilayer wiring board in which wiring layers are formed over multiple layers,
前記放熱経路となる導体は、 前記多層配線基板の各配線層を貫通して 形成されることを特徴とする請求の範囲第 1項に記載の携帯通信機器。  2. The portable communication device according to claim 1, wherein the conductor serving as the heat radiation path is formed so as to penetrate each wiring layer of the multilayer wiring board.
3 . 前記放熱経路となる導体は、 前記多層配線基板の前記バンプ電極 と接する配線層の断面形状が長円形あるいは楕円形であることを特徴と する請求の範囲第 2項に記載の携帯通信機器。  3. The portable communication device according to claim 2, wherein the conductor serving as the heat dissipation path has a cross-sectional shape of a wiring layer in contact with the bump electrode of the multilayer wiring board, which is oval or elliptical. .
4 . 前記放熱経路となる導体は、 前記多層配線基板のバンプ電極と接 する配線層以外の配線層の断面積が、 前記多層配線基板の前記バンプ電 極と接する配線層の断面積より も大きいことを特徴とする請求の範囲第 2項または請求の範囲第 3項に記載の携帯通信機器。  4. The conductor serving as the heat dissipation path has a cross-sectional area of a wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board larger than a cross-sectional area of the wiring layer in contact with the bump electrode of the multilayer wiring board. The portable communication device according to claim 2 or claim 3, characterized in that:
5 . 前記多層配線基板のバンプ電極と接する配線層以外の配線層の断 面形状は、 円形であることを特徴とする請求の範囲第 4項に記載の携帯 通信機器。 5. The mobile phone according to claim 4, wherein the cross-sectional shape of the wiring layer other than the wiring layer in contact with the bump electrode of the multilayer wiring board is circular. Communication equipment.
6 . 前記配線基板は、 セラミ ックで構成されていることを特徴とする 請求の範囲第 1項ないし請求の範囲第 5項のいずれか 1項に記載の携帯 通信機器。  6. The portable communication device according to any one of claims 1 to 5, wherein the wiring board is made of a ceramic.
7 . 前記半導体チップは、 半導体基板の一主面上に形成される電界効 果型トランジスタであることを特徴とする請求の範囲第 1項ないし請求 の範囲第 6項のいずれか 1項に記載の携帯通信機器。  7. The semiconductor device according to claim 1, wherein the semiconductor chip is a field effect transistor formed on one main surface of a semiconductor substrate. Mobile communication devices.
8 . 前記半導体基板は、 化合物半導体基板であることを特徴とする請 求項第 7項の携帯通信機器。  8. The portable communication device according to claim 7, wherein said semiconductor substrate is a compound semiconductor substrate.
9 . 前記放熱経路となる導体は、 電界効果型ト ランジスタのソース電 極に形成されるバンプ電極と電気的、 機械的に接続されることを特徴と する請求の範囲第 7項または請求の範囲第 8項に記載の携帯通信機器。  9. The conductor as the heat dissipation path is electrically and mechanically connected to a bump electrode formed on a source electrode of a field-effect transistor. A mobile communication device according to paragraph 8.
1 0 . 前記放熱経路となる導体は、 第 1の基準電位が印加されること を特徴とする請求の範囲第 1項ないし請求の範囲第 9項のいずれか 1項 に記載の携帯通信  10. The portable communication according to any one of claims 1 to 9, wherein a first reference potential is applied to the conductor serving as the heat radiation path.
機器。 machine.
1 1 . アンテナと、 電力増幅回路モジュールとを有する携帯通信機器 であって、  1 1. A portable communication device having an antenna and a power amplification circuit module,
前記電力増幅回路モジュールは、  The power amplification circuit module,
複数の配線層と、 その内部が金属層で充填された複数のスルーホール とを有する多層配線基板と、  A multilayer wiring board having a plurality of wiring layers and a plurality of through holes whose inside is filled with a metal layer;
その主面に、 ゲート電極、 ソース電極およびドレイ ン電極を有する電 界効果トランジスタが形成された半導体チップであって、 前記主面が前 記多層配線基板と対向するように前記多層配線上に搭載された半導体チ ップと、 A semiconductor chip having a field effect transistor having a gate electrode, a source electrode, and a drain electrode formed on a main surface thereof, mounted on the multilayer wiring so that the main surface faces the multilayer wiring board. Semiconductor chip And
前記半導体チップの前記ゲー ト電極、 ソース電極およびドレイン電極 の各々 と前記多層配線基板の前記複数の配線層を電気的および機械的に 接続する複数のバンプ電極とを有し、  A plurality of bump electrodes for electrically and mechanically connecting each of the gate electrode, the source electrode, and the drain electrode of the semiconductor chip to the plurality of wiring layers of the multilayer wiring board;
前記半導体チップの前記ソース電極に対向する位置に前記複数のスル 一ホールの少なく とも一つが配置され、  At least one of the plurality of through holes is arranged at a position facing the source electrode of the semiconductor chip,
前記ソース電極に対向する位置に配置されたスルーホールの各々 と前 記ソース電極とは、 前記複数のバンプ電極を介して電気的および機械的 に接続されていることを特徴とする携帯通信機器。  A portable communication device, wherein each of the through holes arranged at a position facing the source electrode and the source electrode are electrically and mechanically connected via the plurality of bump electrodes.
1 2 . 前記半導体チップは長方形形状を有し、 前記ソース電極は平面 的に前記半導体チップの長辺方向に沿って延在する第 1 の部分と、 前記 第 1 の部分から前記半導体チップの短辺方向に沿って延在する第 2の部 分とを有し、  12. The semiconductor chip has a rectangular shape, and the source electrode has a first portion extending planarly along a long side direction of the semiconductor chip, and a short portion of the semiconductor chip extending from the first portion. A second portion extending along the side direction,
前記ソース電極に接続された複数のバンプ電極は、 前記半導体チップ の短辺方向に沿って前記第 2の部分に接続されていることを特徴とする 請求の範囲第 1 1項に記載の携帯通信機器。  The mobile communication according to claim 11, wherein the plurality of bump electrodes connected to the source electrode are connected to the second portion along a short side direction of the semiconductor chip. machine.
1 3 . 前記多層配線基板はセラミ ックス基板であり、 前記複数のバン プ電極の配列可能な最小ピツチは、 前記複数のスルーホールの配列可能 な最小ピツチよ り小さいことを特徴とする請求の範囲第 1 1項または請 求の範囲第 1 2項に記載の携帯通信機器。  13. The multilayer wiring board is a ceramic board, and a minimum pitch at which the plurality of bump electrodes can be arranged is smaller than a minimum pitch at which the plurality of through holes can be arranged. The mobile communication device according to paragraph 11 or the scope of the request, paragraph 12.
PCT/JP1998/001744 1998-04-16 1998-04-16 Portable communication equipment WO1999054935A1 (en)

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US6860006B2 (en) 2000-03-17 2005-03-01 Murata Manufacturing Co, Ltd. Method for manufacturing a monolithic ceramic electronic component
JP2012256631A (en) * 2011-06-07 2012-12-27 Toshiba Corp Semiconductor device and manufacturing method of the same
US20210313293A1 (en) * 2020-04-03 2021-10-07 Cree, Inc. Rf amplifier devices and methods of manufacturing
US11362011B2 (en) 2019-04-01 2022-06-14 Nuvoton Technology Corporation Japan Power amplification device
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US11837457B2 (en) 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers

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JPH0521959A (en) * 1991-07-16 1993-01-29 Nec Corp Composite substrate of high heat radiation efficiency
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6860006B2 (en) 2000-03-17 2005-03-01 Murata Manufacturing Co, Ltd. Method for manufacturing a monolithic ceramic electronic component
JP2012256631A (en) * 2011-06-07 2012-12-27 Toshiba Corp Semiconductor device and manufacturing method of the same
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US20210313293A1 (en) * 2020-04-03 2021-10-07 Cree, Inc. Rf amplifier devices and methods of manufacturing
US11670605B2 (en) 2020-04-03 2023-06-06 Wolfspeed, Inc. RF amplifier devices including interconnect structures and methods of manufacturing
US11837457B2 (en) 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers

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