JP2003229521A - Semiconductor module and manufacturing method therefor - Google Patents

Semiconductor module and manufacturing method therefor

Info

Publication number
JP2003229521A
JP2003229521A JP2002025752A JP2002025752A JP2003229521A JP 2003229521 A JP2003229521 A JP 2003229521A JP 2002025752 A JP2002025752 A JP 2002025752A JP 2002025752 A JP2002025752 A JP 2002025752A JP 2003229521 A JP2003229521 A JP 2003229521A
Authority
JP
Japan
Prior art keywords
circuit board
board
substrate
wiring
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002025752A
Other languages
Japanese (ja)
Inventor
Toshiaki Morita
俊章 守田
Yasutoshi Kurihara
保敏 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2002025752A priority Critical patent/JP2003229521A/en
Publication of JP2003229521A publication Critical patent/JP2003229521A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin high frequency power module whose mounting area is reduced. <P>SOLUTION: A recess 102 is disposed on one face side of a multilayer wiring board 1, and a bump is formed at the base of the recess. The module is constituted of the multilayer wiring board 1 connected to the terminal on one face side of a semiconductor element 101 through the bump 104, and a circuit board which has a radiating wiring board 105 and in which the radiating wiring board 105 is connected to a terminal on the other face side of the semiconductor element 101 through the wax material of Sn. The bump 104 is formed of Al or Al alloy or Au or Au alloy. The multilayer wiring board 1 has a circuit part including at least a passive part. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は半導体モジュール及
びその製造方法に係り、特に小型の半導体モジュール及
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module and a manufacturing method thereof, and more particularly to a small semiconductor module and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】半導体装置として、ＰＤＣ(Personal Di
gital Cellular)方式の自動車電話、及び携帯電話、或
いはＰＨＳ(Personal Handyphone System)方式の携帯電
話等の携帯通信機器に組み込まれる高周波電力増幅器
（半導体モジュール）が知られている。この高周波電力
増幅器は、複数の増幅手段を多段に接続した多段式増幅
回路構成になっている。2. Description of the Related Art As a semiconductor device, a PDC (Personal Dielectric
2. Description of the Related Art A high frequency power amplifier (semiconductor module) incorporated in a mobile communication device such as a car phone of a digital cellular system and a mobile phone or a mobile phone of a PHS (Personal Handyphone System) system is known. This high frequency power amplifier has a multi-stage amplification circuit configuration in which a plurality of amplification means are connected in multiple stages.

【０００３】前記高周波電力増幅器は、主面に増幅手段
が形成された半導体チップを配線基板の主面側に塔載
し、半導体チップの前記主面に形成された電極と配線基
板の前記主面に形成された電極とを導電性のワイヤで電
気的に接続している。増幅手段は、例えば複数の電界効
果トランジスタの夫々を電気的に並列に接続した構成に
なっており、増幅手段のゲート端子（入力部）は半導体
チップの一主面に形成されたチップ側入力用電極と電気
的に接続され、増幅手段のドレイン端子（出力部）は半
導体チップの前記主面に形成されたチップ側出力用電極
と電気的に接続されている。チップ側入力用電極は半導
体チップの一辺側に配置され、チップ側出力用電極は半
導体チップの一辺と対向する他の辺側に配置されてい
る。増幅手段のソース端子は半導体チップの前記主面と
対向する他の面（裏面）に形成された裏面電極と電気的
に接続され、この裏面電極は基準電位に電位固定され
る。チップ側入力用電極は、半導体チップの一辺と向か
い合うようにして配線基板の前記主面に形成された基板
側入力用電極と入力用ワイヤを介して電気的に接続さ
れ、チップ側出力用電極は、半導体チップの他の辺と向
かい合うにようにして配線基板の前記主面に形成された
基板側出力用電極と出力用ワイヤを介して電気的に接続
されている。In the high-frequency power amplifier, a semiconductor chip having an amplifying means formed on the main surface is mounted on the main surface side of a wiring board, and electrodes formed on the main surface of the semiconductor chip and the main surface of the wiring board. The electrodes formed on the substrate are electrically connected by a conductive wire. The amplifying means has, for example, a structure in which a plurality of field effect transistors are electrically connected in parallel, and the gate terminal (input section) of the amplifying means is for chip side input formed on one main surface of the semiconductor chip. The drain terminal (output section) of the amplification means is electrically connected to the electrode, and is electrically connected to the chip-side output electrode formed on the main surface of the semiconductor chip. The chip-side input electrode is arranged on one side of the semiconductor chip, and the chip-side output electrode is arranged on the other side opposite to one side of the semiconductor chip. The source terminal of the amplifying means is electrically connected to a back surface electrode formed on the other surface (back surface) facing the main surface of the semiconductor chip, and the back surface electrode is fixed at a reference potential. The chip-side input electrode is electrically connected to the board-side input electrode formed on the main surface of the wiring board so as to face one side of the semiconductor chip via the input wire, and the chip-side output electrode is The substrate-side output electrode formed on the main surface of the wiring substrate is electrically connected to the other side of the semiconductor chip via an output wire.

【０００４】具体的な半導体モジュールの構造について
は、日立評論社発行「日立評論」１９９３年第４号、同
年４月２５日発行、Ｐ１２ないしＰ２６に記載されてい
る。この半導体モジュール（高周波電力増幅器用ＭＯＳ
・パワーモジュール）は、パワーＭＯＳＦＥＴを三段に
組み込み、出力の向上を図っている。The specific structure of the semiconductor module is described in "Hitachi Kenron", No. 4, 1993, issued by Hitachi Hyoron Co., Ltd., issued April 25, P12 to P26. This semiconductor module (MOS for high frequency power amplifier
・ The power module) incorporates power MOSFETs in three stages to improve output.

【０００５】また、前記文献には、各種のパッケージ
（封止）形態の半導体モジュールが紹介されている。携
帯用電話に組み込まれる半導体モジュールは、小型化の
ために金属カバーと表面実装型が採用されている。Further, the above-mentioned documents introduce semiconductor modules of various package (sealing) forms. For a semiconductor module incorporated in a mobile phone, a metal cover and a surface mount type are adopted for miniaturization.

【０００６】このような、金属カバー（以下、本明細書
ではキャップと称する）と表面実装型が採用される従来
の半導体モジュールの構造を図１８に示す。すなわち、
矩形板状の放熱フランジ２０１の主面（上面）には、図
示しないはんだによってガラス−セラミックス基板２０
２が固定されている。この基板２０２の主面（上面）に
は、パワーＭＯＳＦＥＴ（図示せず）等の能動部品や抵
抗、コンデンサ（図示せず）等の受動部品が搭載されて
いる。ＭＯＳＦＥＴ等の能動部品と外部端子はワイヤボ
ンディング法により接続される。FIG. 18 shows a structure of such a conventional semiconductor module in which a metal cover (hereinafter referred to as a cap in this specification) and a surface mount type are adopted. That is,
The glass-ceramic substrate 20 is formed on the main surface (upper surface) of the rectangular plate-shaped heat dissipation flange 201 with solder (not shown).
2 is fixed. On the main surface (upper surface) of the substrate 202, active components such as power MOSFETs (not shown) and passive components such as resistors and capacitors (not shown) are mounted. Active parts such as MOSFETs and external terminals are connected by a wire bonding method.

【０００７】また、前記ガラス−セラミックス基板２０
２の主面側を覆うように、放熱フランジ２０１にはキャ
ップ２０３が取り付けられている。また、前記キャップ
２０３の一側面には開口部分が設けられ、この開口部分
を通して内端が前記ガラス−セラミックス基板２０２に
固定されたリード２０４が取り付けられている。また、
前記放熱フランジ２０１の側縁からは、面付用フィン２
０５が階段状に一段だけ外方に突出するように配設され
ている。この面付用フィン２０５は、高周波パワーモジ
ュール２０６が実装される図示しないシャーシに熱を伝
達する役割を果たすとともにグランドピンともなってい
る。また、放熱フランジ２０１は前記ガラス−セラミッ
ク基板２０２に設けられたスルーホールに充填された導
体を介してガラス−セラミックス基板２０２の主面のグ
ランド配線に電気的に接続されている。Further, the glass-ceramic substrate 20
A cap 203 is attached to the heat radiating flange 201 so as to cover the main surface side of 2. An opening portion is provided on one side surface of the cap 203, and a lead 204 having an inner end fixed to the glass-ceramic substrate 202 is attached through the opening portion. Also,
From the side edge of the heat dissipation flange 201, the fin 2 for surface attachment
05 are arranged so as to project outward one step at a step. The surface mounting fins 205 play a role of transferring heat to a chassis (not shown) in which the high frequency power module 206 is mounted and also serve as ground pins. Further, the heat radiation flange 201 is electrically connected to the ground wiring on the main surface of the glass-ceramic substrate 202 through the conductor filled in the through hole provided in the glass-ceramic substrate 202.

【０００８】また、特開平１０−５０９２６号公報に
は、回路基板の凹部に発熱性を有する回路部品を収納
し、該回路部品のはんだバンプを回路基板のランド電極
にはんだ付けすること、及びこのようにして得た回路基
板を親回路基板上に熱伝導部材を介して搭載し、更に回
路基板の側面に設けた端子電極を親回路基板上のランド
電極にはんだ付けすることにより、回路部品からの発熱
を親回路基板に伝達して放熱する放熱モジュールが示さ
れている。Further, in Japanese Patent Application Laid-Open No. 10-50926, a circuit component having a heat generating property is housed in a recess of a circuit board, and a solder bump of the circuit component is soldered to a land electrode of the circuit board, and By mounting the circuit board obtained in this way on the parent circuit board via the heat conductive member, and by soldering the terminal electrodes provided on the side surface of the circuit board to the land electrodes on the parent circuit board, A heat dissipation module that transfers the heat generated by the above to the main circuit board to dissipate heat is shown.

【０００９】[0009]

【発明が解決しようとする課題】前記従来の半導体モジ
ュールは、放熱フランジ２０１とキャップ２０３とによ
り構成される半導体モジュール２０６本体部分の寸法
は、たとえば縦２１ｍｍ，横１０ｍｍ，高さ３．７ｍｍ
と小型化されている。しかし半導体モジュール２０６の
周囲には、例えば２ｍｍ程度の長さの面付用フィン２０
５を有している。この面付用フィン２０５は高周波パワ
ーモジュール２０６の３辺側にそれぞれ設けられること
から、実装面積の更なる縮小化の妨げとなる。また、前
記能動部品と外部配線とを結線するボンディングワイヤ
は半導体モジュールの高さを低くすること、すなわち更
なる薄型化の妨げとなる。In the conventional semiconductor module, the dimensions of the main body of the semiconductor module 206 constituted by the heat radiation flange 201 and the cap 203 are, for example, 21 mm in length, 10 mm in width, and 3.7 mm in height.
And has been miniaturized. However, the surface mounting fin 20 having a length of, for example, about 2 mm is provided around the semiconductor module 206.
Have five. Since the surface-mounting fins 205 are provided on the three sides of the high-frequency power module 206, respectively, the mounting area is prevented from being further reduced. In addition, the bonding wire connecting the active component and the external wiring reduces the height of the semiconductor module, that is, hinders further reduction in thickness.

【００１０】また、前記公報に示されるモジュールは、
前記回路基板と回路部品及び回路部品と親基板との接合
はいずれもはんだ接合を用いており、これらの接合温度
に階層を設けることは比較的困難である。また、前記回
路部品と親基板は膜状の熱伝導部材を介して接着され、
更に回路的な接合は回路基板の側面に設けた端子電極を
親回路基板上のランド電極にはんだ付けすることにより
行われている。このためモジュールを構成する前記回路
部品の放熱及びモジュールの高集積化に不利である。Further, the module shown in the above publication is
The circuit board and the circuit component and the circuit component and the parent board are all joined by solder joining, and it is relatively difficult to provide a hierarchy at these joining temperatures. In addition, the circuit component and the parent board are bonded via a film-shaped heat conducting member,
Further, the circuit connection is performed by soldering the terminal electrode provided on the side surface of the circuit board to the land electrode on the parent circuit board. For this reason, it is disadvantageous in heat dissipation of the circuit components constituting the module and high integration of the module.

【００１１】本発明はこれらの問題点に鑑みてなされた
もので、実装面積の縮小化、薄型化が達成できる高周波
パワーモジュールを提供する。The present invention has been made in view of these problems, and provides a high frequency power module capable of achieving a reduction in mounting area and a reduction in thickness.

【００１２】[0012]

【課題を解決するための手段】本発明は、上記の課題を
解決するために次のような手段を採用した。The present invention adopts the following means in order to solve the above problems.

【００１３】多層配線基板１の一方の面側に凹部を設け
るとともに該凹部の底面にバンプを形成し、該バンプを
介して半導体素子の一方面側の端子と接続する多層配線
基板１と、放熱性配線板を備え、該放熱性配線板をＳｎ
系のろう材を介して前記半導体素子の他方の面側の端子
と接続してなる回路基板とからなり、前記バンプは、Ａ
ｌあるいはＡｌ合金またはＡｕあるいはＡｕ合金からな
り、且つ前記多層配線基板１は少なくとも受動部品を含
む回路部品を備える。A multilayer wiring board 1 is provided with a concave portion on one surface side of the multilayer wiring board 1, bumps are formed on the bottom surface of the concave portion, and the multilayer wiring board 1 is connected to a terminal on the one surface side of a semiconductor element through the bump, and heat dissipation. Heat dissipative wiring board
A circuit board which is connected to a terminal on the other surface side of the semiconductor element via a brazing material of a system, and the bump is A
1 or Al alloy or Au or Au alloy, and the multilayer wiring board 1 includes circuit components including at least passive components.

【００１４】[0014]

【発明の実施の形態】以下、本発明の実施形態を添付図
面を参照しながら説明する。DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

【００１５】（実施例１）図１は、本発明の一実施例で
ある半導体モジュール１００の構成を示した概略図であ
り、図２は図１のＡ−Ａ’部の断面図である。本実施例
の半導体モジュールの厚さは０．４５ｍｍである。(Embodiment 1) FIG. 1 is a schematic view showing a structure of a semiconductor module 100 which is an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA 'in FIG. The semiconductor module of this embodiment has a thickness of 0.45 mm.

【００１６】図１及び図２において、１はガラス−セラ
ミックス製基板である。ガラス−セラミックス基板１は
多層構造になっており、層間に伝送配線１０７が形成さ
れ、該配線間にはコンデンサ、抵抗、インダクタ等の受
動素子も形成されている。1 and 2, reference numeral 1 is a glass-ceramic substrate. The glass-ceramic substrate 1 has a multi-layer structure, transmission wirings 107 are formed between the layers, and passive elements such as capacitors, resistors, and inductors are also formed between the wirings.

【００１７】また、ガラス−セラミックス基板１には、
半導体材料で構成されたＭＯＳＦＥＴ素子１０１を実装
するための凹部１０２が形成されている。１０３はガラ
ス−セラミックス基板１を実装する回路基板、１０４は
ＭＯＳＦＥＴ素子１０１とガラス−セラミックス基板１
とを電気的に接続するためのＡｌ製バンプ（突起物）で
ある。ＭＯＳＦＥＴ素子１０１の前記接続面とは反対側
の面（下面）と回路基板１０３上に形成した放熱配線板
１０５とは、Ｓｎ系のろう材（Snと、Ag、Au、Al、Cu、
Ni、Ge、Ga、In、P、Bi、Znの群から選択された少なく
とも１元素、及び不可避的な不純物を含むろう材）１０
６を介して接続される。放熱配線板１０５は、ＭＯＳＦ
ＥＴ素子１０１より幅広く、かつ凹部１０２より狭くな
るよう配置される。１０８は回路基板１０３上に形成し
た配線であり、ガラス−セラミックス基板１とＳｎ系ろ
う材１０６を介して電気的に接続されている。放熱配線
板１０５は、回路基板１０３上に形成した配線１０８の
一部としても機能する。Further, the glass-ceramic substrate 1 includes
A recess 102 for mounting the MOSFET element 101 made of a semiconductor material is formed. 103 is a circuit board on which the glass-ceramic substrate 1 is mounted, and 104 is the MOSFET element 101 and the glass-ceramic substrate 1.
It is an Al bump (projection) for electrically connecting and. The surface (lower surface) of the MOSFET element 101 opposite to the connection surface and the heat dissipation wiring board 105 formed on the circuit board 103 are made of Sn-based brazing material (Sn, Ag, Au, Al, Cu,
A brazing material containing at least one element selected from the group of Ni, Ge, Ga, In, P, Bi and Zn, and inevitable impurities) 10
Connected via 6. The heat radiation wiring board 105 is a MOSF.
It is arranged so as to be wider than the ET element 101 and narrower than the recess 102. Wirings 108 are formed on the circuit board 103, and are electrically connected to the glass-ceramic substrate 1 via the Sn-based brazing material 106. The heat dissipation wiring board 105 also functions as a part of the wiring 108 formed on the circuit board 103.

【００１８】なお、本実施例における半導体モジュール
は、放熱配線板１０５、回路基板１０３上に形成した配
線１０８、Ｓｎ系ろう材１０６、ＭＯＳＦＥＴ素子１０
１、及びＭＯＳＦＥＴ素子１０１を実装したガラス−セ
ラミックス基板１で構成される集合体を指す。The semiconductor module of this embodiment includes a heat dissipation wiring board 105, wiring 108 formed on the circuit board 103, Sn-based brazing material 106, and MOSFET element 10.
1 and a glass-ceramic substrate 1 on which the MOSFET element 101 is mounted.

【００１９】次に、本発明におけるコンデンサ、抵抗、
インダクタを構成したガラス−セラミックス基板につい
て詳細に説明する。Next, the capacitor, resistor, and
The glass-ceramic substrate forming the inductor will be described in detail.

【００２０】基板に形成するコンデンサ素子は、２つの
金属電極で無機材料からなる誘電体材料を挟んだ構造の
１つあるいは複数のコンデンサ素子群と、２つの金属電
極で誘電体材料を挟んだ構造の１つあるいは複数のコン
デンサ素子群とからなる。さらに無機材料とは一般にコ
ンデンサ用誘電体材料として用いられているものであれ
ば制限はなく、例えばＴａ、Ｍｇ、Ｓｒ等の酸化物が挙
げられる。その形成法も特に制限はなく、スパッタ法、
プラズマＣＶＤ法などのドライ法、陽極酸化法などのウ
ェット法を用いることもできる。The capacitor element formed on the substrate is one or a plurality of capacitor element groups having a structure in which a dielectric material made of an inorganic material is sandwiched between two metal electrodes, and a structure in which a dielectric material is sandwiched between two metal electrodes. 1 or a plurality of capacitor element groups. Further, the inorganic material is not limited as long as it is generally used as a dielectric material for capacitors, and examples thereof include oxides of Ta, Mg, Sr and the like. The forming method is not particularly limited, and the sputtering method,
A dry method such as a plasma CVD method or a wet method such as an anodic oxidation method can also be used.

【００２１】基板に形成するインダクタ素子は、いわゆ
る誘導性回路要素であれば特に制限はなく、例えば平面
に形成されたスパイラル型、さらにはそれを複数個重ね
たもの、あるいはソレノイド型などが用いられる。更に
インダクタ素子および金属配線とは同一の素材であって
も異なる素材であっても良く、電気伝導性、および周囲
の材料との接着性、形成法などによって適宜選択され
る。さらにその形成方法も特に制限されるものではな
い。例えばスパッタ法などを用いてＣｕを形成しても良
く、周囲の材料との接着性を考慮してその界面にＴｉ、
Ｃｒなどを形成しても良い。更にスパッタ法などで種膜
となる薄膜をＣｕ等で形成した後、電解めっき法などで
形成してもかまわない。さらに配線およびインダクタ素
子のパターンニング法としては、エッチング法、リフト
オフ法などの一般の配線パターンニング法を用いること
ができる。また、Ａｇなどの金属を含有する樹脂ペース
トを用いて印刷法などで形成しても良い。さらに、前記
無機誘電体の形成温度が高い場合には、Ｐｔなどの耐酸
化性、耐熱性の高い金属を用いることもできる。The inductor element formed on the substrate is not particularly limited as long as it is a so-called inductive circuit element. For example, a spiral type formed on a plane, a plurality of stacked layers, or a solenoid type is used. . Further, the inductor element and the metal wiring may be made of the same material or different materials, and are appropriately selected depending on electric conductivity, adhesiveness with surrounding materials, forming method, and the like. Furthermore, the forming method is not particularly limited. For example, Cu may be formed by using a sputtering method or the like, and Ti at the interface in consideration of adhesiveness with surrounding materials,
Cr or the like may be formed. Further, a thin film to be a seed film may be formed by Cu or the like by a sputtering method or the like and then formed by an electrolytic plating method or the like. Further, as a wiring and inductor element patterning method, a general wiring patterning method such as an etching method or a lift-off method can be used. Alternatively, a resin paste containing a metal such as Ag may be used to form it by a printing method or the like. Furthermore, when the formation temperature of the inorganic dielectric is high, a metal having high oxidation resistance and heat resistance such as Pt can be used.

【００２２】基板に形成する抵抗素子は、２つの金属電
極で抵抗材料を挟んだ構造であり、抵抗材料としては一
般に抵抗体材料として用いられているものであれば特に
制限はなく、例えばＣｒ−Ｓｉ系材料、ＴｉＮなどが用
いられる。その形成法も特に制限はなく、例えばスパッ
タ法、プラズマＣＶＤ法などが用いられる。The resistance element formed on the substrate has a structure in which a resistance material is sandwiched between two metal electrodes, and the resistance material is not particularly limited as long as it is generally used as a resistance material, and for example, Cr- Si-based material, TiN, etc. are used. The forming method is not particularly limited, and for example, a sputtering method, a plasma CVD method or the like is used.

【００２３】ガラス−セラミックス基板は、各素子の効
率を落とさないよう、絶縁性の高い基板であれば特に制
限はなく、強度、加工性などを考慮して選択される。特
にＳｃ，Ｙ，Ｌａ，Ｐｒ，Ｎｄ，Ｐｍ，Ｓｍ，Ｅｕ，Ｇ
ｄ，Ｔｂ，Ｄｙ，Ｈｏ，Ｅｒ，Ｔｍ，Ｙｂ，Ｌｕの群か
ら選ばれた少なくとも１種の希土類元素を含有すること
が望ましい。さらには、希土類元素はＬｎ２Ｏ３（Ｌｎ
は希土類元素）の酸化物換算で、ガラス全体に対して
０．５ 〜２０重量％含有し、他の成分としてＳｉＯ２
：４０〜８０重量％，Ｂ２Ｏ３：０〜２０重量％，Ｒ
２Ｏ （Ｒはアルカリ金属）：０〜２０重量％，ＲＯ
（Ｒはアルカリ土類金属）：０〜２０重量％，Ａｌ２Ｏ
３：０〜１７重量％を含み、かつＲ２Ｏ＋ＲＯ：１０〜
３０重量％であることが望ましい。こうすることでガラ
ス−セラミックス基板の強度が大幅に向上し加工性も格
段に良好となる。また、より小型化を達成するためガラ
ス−セラミックス基板は多層構造であることが望まし
い。The glass-ceramic substrate is not particularly limited as long as it is a substrate having a high insulating property so as not to reduce the efficiency of each element, and is selected in consideration of strength, workability and the like. Especially Sc, Y, La, Pr, Nd, Pm, Sm, Eu, G
It is desirable to contain at least one rare earth element selected from the group of d, Tb, Dy, Ho, Er, Tm, Yb and Lu. Furthermore, the rare earth element is Ln 2 O 3 (Ln
In terms of oxide of rare earth elements), and amount of 0.5 to 20 wt% based on the entire glass, SiO 2 as the other component
: 40-80 wt%, B 2 O 3: 0~20 wt%, R
2 O (R is an alkali metal): 0 to 20% by weight, RO
(R is an alkaline earth metal): 0 to 20% by weight, Al 2 O
3 : 0 to 17% by weight, and R 2 O + RO: 10
It is preferably 30% by weight. By doing so, the strength of the glass-ceramic substrate is significantly improved and the workability is remarkably improved. Further, it is desirable that the glass-ceramic substrate has a multilayer structure in order to achieve further miniaturization.

【００２４】ガラス−セラミックス基板の各素子の配置
は特に制限はないが、各素子のカップリングによる寄生
容量の発生による性能の低下、及び求められる電子回路
部品の大きさに基づくその集積度に応じて、各素子の配
置を適宜設計する必要がある。たとえば小型化をさほど
必要としない電子回路部品であれば、各素子は同一面上
に並べる、あるいは各層間の距離を大きくして各素子間
の影響を小さくすることが必要である。設置面すなわち
グランド層を設けるのも一つの方法である。また、より
小型化を求めるのならば、基板の両面に多数の面上に各
素子を形成することが必要である。The arrangement of each element on the glass-ceramic substrate is not particularly limited, but the performance is deteriorated due to the generation of parasitic capacitance due to the coupling of each element, and the degree of integration is determined based on the required size of electronic circuit parts. Therefore, it is necessary to appropriately design the arrangement of each element. For example, in the case of an electronic circuit component that does not require a small size, it is necessary to arrange the elements on the same plane or increase the distance between the layers to reduce the influence between the elements. One method is to provide an installation surface, that is, a ground layer. Further, if further miniaturization is required, it is necessary to form each element on a large number of surfaces on both surfaces of the substrate.

【００２５】このように、従来単体部品で搭載していた
インダクタ、コンデンサ、抵抗などの受動素子を基板上
に集積化することで、実装面積を半分にすることがで
き、より小型にすることができる。基板に絶縁性の高い
材料を用いることで、各素子の効率の低下を防ぐことが
でき、従来のシリコン基板を用いたものと比較して約５
倍の効率が得られる。さらにはシリコン基板を用いたも
のの半分のコストで製造できる。In this way, by integrating passive elements such as inductors, capacitors, and resistors, which are conventionally mounted as single parts, on a substrate, the mounting area can be halved and the size can be further reduced. it can. By using a highly insulating material for the substrate, it is possible to prevent a decrease in the efficiency of each element, and it is possible to reduce the efficiency by about 5% compared to the conventional silicon substrate.
Double the efficiency. Furthermore, it can be manufactured at half the cost of using a silicon substrate.

【００２６】次に図１及び図２に示す本実施例モジュー
ルについて、その製造方法を述べる。Next, a method of manufacturing the module of this embodiment shown in FIGS. 1 and 2 will be described.

【００２７】まず、焼結法により伝送配線及び前記受動
素子を形成した多層構造のガラス−セラミックス基板
（０．３５ｍｍ厚）を用意した。該ガラス−セラミック
ス基板１の回路基板搭載側には、ガラス−セラミックス
基板形成加工時、ＭＯＳＦＥＴ１０１が実装可能な程度
の大きさの凹部１０２を形成しておく。該凹部の深さ
は、ＭＯＳＦＥＴ搭載後、ＭＯＳＦＥＴ１０１の裏面が
ガラス−セラミックス基板の回路基板搭載側の面と同等
の高さになるような寸法にする。前記凹部のＭＯＳＦＥ
Ｔ搭載面にはＡｌ配線が形成されており、該Ａｌ配線上
にはＭＯＳＦＥＴとの接続用バンプ１０４が、例えば固
相接合により形成されている。First, a glass-ceramic substrate (thickness: 0.35 mm) having a multi-layer structure in which the transmission wiring and the passive element were formed by a sintering method was prepared. On the side of the glass-ceramic substrate 1 on which the circuit board is mounted, a recess 102 having a size large enough to mount the MOSFET 101 during the glass-ceramic substrate forming process is formed. The depth of the recess is such that after mounting the MOSFET, the back surface of the MOSFET 101 has the same height as the surface of the glass-ceramic substrate on the circuit board mounting side. MOSFE of the recess
An Al wiring is formed on the T mounting surface, and a bump 104 for connection with a MOSFET is formed on the Al wiring by, for example, solid phase bonding.

【００２８】次に、図３を参照してＭＯＳＦＥＴ搭載か
ら回路基板搭載までの製造フローを説明する。Next, a manufacturing flow from mounting the MOSFET to mounting the circuit board will be described with reference to FIG.

【００２９】先ず、ＭＯＳＦＥＴを、上記ガラス−セラ
ミックス基板の凹部に超音波を併用したフリップチップ
接続法で接続（固相接合）する（（ａ）〜（ｂ））。こ
のとき熱を加えても良い。なお、前述のようにＡｌ配線
上にＭＯＳＦＥＴとの接続用バンプ１０４を予め形成し
ておくことにより、前記ガラス−セラミックス基板上に
ＭＯＳＦＥＴを搭載する際におけるＭＯＳＦＥＴに加わ
る接合圧力の印加回数を１回に限定することができる。First, the MOSFET is connected (solid phase bonding) to the concave portion of the glass-ceramic substrate by the flip-chip connection method using ultrasonic waves ((a)-(b)). At this time, heat may be applied. By forming the bumps 104 for connecting to the MOSFET on the Al wiring in advance as described above, the number of times of application of the bonding pressure applied to the MOSFET when mounting the MOSFET on the glass-ceramic substrate is once. Can be limited to

【００３０】次に、回路基板上に形成された、ガラス−
セラミックス基板の回路基板搭載部及びガラス−セラミ
ックス基板に搭載したＭＯＳＦＥＴの裏面に対応する配
線上にＳｎ系ろう材ペーストをスクリーン印刷する。こ
のときのＳｎ系ろう材ペーストの厚さはおよそ５００μ
ｍである。Next, the glass formed on the circuit board
The Sn-based brazing material paste is screen-printed on the circuit board mounting portion of the ceramic substrate and the wiring corresponding to the back surface of the MOSFET mounted on the glass-ceramic substrate. At this time, the thickness of the Sn-based brazing filler metal paste is approximately 500 μm.
m.

【００３１】次に、このＳｎ系ろう材ペーストが印刷さ
れた回路基板上に、ＭＯＳＦＥＴを搭載した一体型基板
を所定の位置になるよう位置合せして載置し（ｃ）、そ
の後、ピーク温度２５０℃のリフロー炉を通させる。こ
れによりＭＯＳＦＥＴを搭載した一体型基板の回路基板
への搭載が完了し、本実施例の高周波パワーモジュール
が完成する（ｄ）。本実施例ではペーストろう材を用い
るため、ＭＯＳＦＥＴを搭載した一体型基板の高さのば
らつきをキャンセルすることができる。なお、このとき
の高周波パワーモジュールは、同一の回路基板上に搭載
された他の部品の何れよりも高さが低いことが望まし
い。Next, an integrated type substrate having a MOSFET mounted thereon is aligned and placed at a predetermined position on the circuit substrate on which the Sn-based brazing material paste is printed (c), and then the peak temperature is set. Pass through a reflow oven at 250 ° C. As a result, the mounting of the integrated substrate on which the MOSFET is mounted on the circuit board is completed, and the high frequency power module of this embodiment is completed (d). In this embodiment, since the paste brazing material is used, it is possible to cancel the height variation of the integrated substrate on which the MOSFET is mounted. In this case, it is desirable that the high frequency power module has a height lower than that of any other component mounted on the same circuit board.

【００３２】発熱源であるパワーＭＯＳＦＥＴの放熱対
策として、従来はＭＯＳＦＥＴ搭載基板にサーマルビア
ホールを設け、前記発熱をＭＯＳＦＥＴ搭載基板内に分
散させていた。これに対して本実施例ではパワーＭＯＳ
ＦＥＴの裏面全体から熱伝導性に優れる金属材料（Ｓｎ
系ろう材、及び回路基板上に形成した放熱電極板）を介
して放熱するため、放熱を高効率に行うことができる。
なお、ＭＯＳＦＥＴを搭載する一体型基板の凹部には、
機械的衝撃及び湿気等を原因とする化学変化からＭＯＳ
ＦＥＴを保護するため樹脂を充填することが望ましい
（ｂ）。As a heat dissipation measure of the power MOSFET which is a heat source, conventionally, a thermal via hole is provided in the MOSFET mounting substrate to disperse the heat generation in the MOSFET mounting substrate. On the other hand, in this embodiment, the power MOS
Metallic material (Sn
Since heat is radiated through the brazing filler metal and the heat dissipation electrode plate formed on the circuit board, heat dissipation can be performed with high efficiency.
In addition, in the concave portion of the integrated substrate on which the MOSFET is mounted,
MOS due to chemical changes caused by mechanical shock and moisture
It is desirable to fill with resin to protect the FET (b).

【００３３】また、図１、及び図２は本発明の一実施例
であり、各素子の配置はこれに限定されるものではな
い。ＭＯＳＦＥＴのような能動素子は単数、あるいは３
素子以上搭載してもよい。また、図２において、回路基
板１０３上に形成した放熱配線板１０５は回路基板１０
３上に形成した配線１０８とは独立している構造であっ
てもよい。また、本実施例において、ガラス−セラミッ
クス基板に形成した凹部のＭＯＳＦＥＴ搭載面に、Ａｕ
配線を形成し、かつＭＯＳＦＥＴとの接続用バンプがＡ
ｕ製であってもよい。また、ガラス−セラミックス基板
の代わりに、アルミナ製、窒化アルミ製、ガラス製、及
び有機材料製多層配線基板であってもよい。FIGS. 1 and 2 show one embodiment of the present invention, and the arrangement of each element is not limited to this. A single active device, such as a MOSFET, or three
More than one element may be mounted. Further, in FIG. 2, the heat dissipation wiring board 105 formed on the circuit board 103 is the circuit board 10
The structure may be independent of the wiring 108 formed on the wiring 3. Further, in the present embodiment, Au is formed on the MOSFET mounting surface of the recess formed in the glass-ceramic substrate.
A wiring is formed and the bump for connecting to the MOSFET is A
It may be made of u. Further, instead of the glass-ceramic substrate, a multilayer wiring substrate made of alumina, aluminum nitride, glass, or organic material may be used.

【００３４】（実施例２）図４は、本発明の一実施例で
ある半導体モジュール１００の構成を示した概略図であ
り、図５は、図４のＢ−Ｂ’部の断面図である。本実施
例半導体モジュールの厚さは０．５５ｍｍである。(Embodiment 2) FIG. 4 is a schematic view showing the structure of a semiconductor module 100 which is an embodiment of the present invention, and FIG. 5 is a sectional view taken along the line BB 'in FIG. . The thickness of the semiconductor module of this embodiment is 0.55 mm.

【００３５】図４及び図５において、１はアルミナ製基
板である。基板１は多層構造になっており、層間に伝送
配線１０７が形成され、コンデンサ、抵抗、インダクタ
等の受動素子も形成されている。また、基板１には、半
導体材料で構成されたＭＯＳＦＥＴ素子１０１を実装す
るための凹部１０２が形成されている。１０３は基板１
を実装する回路基板、１０４はＭＯＳＦＥＴ素子１０１
と基板１とを電気的に接続するためのＡｌ製バンプであ
る。ＭＯＳＦＥＴ素子１０１の前記接続面とは反対側の
面（下面）と回路基板１０３上に形成した放熱配線板１
０５とは、Ｓｎ系ろう材１０６を介して接続される。放
熱配線板１０５は、ＭＯＳＦＥＴ素子１０１より幅広
く、かつ凹部１０２より狭くなるよう配置される。１０
８は回路基板１０３上に形成した配線であり、ガラス−
セラミックス基板１とＳｎ系ろう材１０６を介して電気
的に接続されている。放熱配線板１０５は、回路基板１
０３上に形成した配線１０８の一部としても機能する。
１１１は基板１上に金属ろう材（図示せず）を介して搭
載したコンデンサ、ソレノイド、抵抗等の部品、１０９
は基板１上に金属ろう材（図示せず）を介して搭載した
集積回路素子、１１５は集積回路素子１０９と基板１上
に形成した電極とを電気的に接続するためのボンディン
グワイヤ、１１４は集積回路素子１０９を搭載するため
の基板１に形成した凹部、１１０は基板１上に搭載され
たコンデンサ、ソレノイド、抵抗等の部品１１１、集積
回路素子１０９及びボンディングワイヤ１１５を覆うよ
うに形成したエポキシ樹脂である。In FIGS. 4 and 5, reference numeral 1 is an alumina substrate. The substrate 1 has a multi-layer structure, the transmission wiring 107 is formed between layers, and passive elements such as capacitors, resistors, and inductors are also formed. Further, the substrate 1 is provided with a recess 102 for mounting the MOSFET element 101 made of a semiconductor material. 103 is the substrate 1
A circuit board for mounting the device, 104 is a MOSFET device 101
And an Al bump for electrically connecting the substrate 1 to the substrate 1. Heat dissipation wiring board 1 formed on the surface (lower surface) of the MOSFET element 101 opposite to the connection surface and the circuit board 103.
05 is connected through a Sn-based brazing material 106. The heat dissipation wiring board 105 is arranged so as to be wider than the MOSFET element 101 and narrower than the recess 102. 10
Reference numeral 8 denotes wiring formed on the circuit board 103, which is made of glass-
The ceramics substrate 1 is electrically connected to the Sn-based brazing material 106. The heat dissipation wiring board 105 is the circuit board 1.
03 also functions as a part of the wiring 108 formed on.
111 is a component such as a capacitor, a solenoid, or a resistor mounted on the substrate 1 via a metal brazing material (not shown), 109
Is an integrated circuit element mounted on the substrate 1 via a metal brazing material (not shown), 115 is a bonding wire for electrically connecting the integrated circuit element 109 and an electrode formed on the substrate 1, 114 is a A recess formed in the substrate 1 for mounting the integrated circuit element 109, 110 is an epoxy formed so as to cover the components 111 such as capacitors, solenoids and resistors mounted on the substrate 1, the integrated circuit element 109 and the bonding wire 115. It is a resin.

【００３６】なお、本実施例における半導体モジュール
は、放熱配線板１０５、回路基板１０３上に形成した配
線１０８、Ｓｎ系ろう材１０６、ＭＯＳＦＥＴ素子１０
１、ＭＯＳＦＥＴ素子１０１を実装した基板１、基板１
上に搭載されたコンデンサ、ソレノイド、抵抗等の部品
１１１、集積回路素子１０９、ボンディングワイヤ１１
５、並びに基板１上に搭載されたコンデンサ、ソレノイ
ド、抵抗等の部品１１１、集積回路素子１０９及びボン
ディングワイヤ１１５を覆うように形成したエポキシ樹
脂からなる集合体を指す。また、本実施例におけるコン
デンサ、抵抗、インダクタを構成した基板１については
実施例１と同様である。The semiconductor module of this embodiment includes a heat dissipation wiring board 105, wiring 108 formed on the circuit board 103, Sn-based brazing material 106, and MOSFET element 10.
1, substrate 1 on which MOSFET device 101 is mounted, substrate 1
Parts 111 such as capacitors, solenoids and resistors mounted on the integrated circuit element 109, bonding wire 11
5 and parts 111 such as capacitors, solenoids, resistors, etc. mounted on the substrate 1, the integrated circuit element 109, and the epoxy resin formed so as to cover the bonding wires 115. Further, the substrate 1 that constitutes the capacitors, resistors, and inductors in this embodiment is the same as that in the first embodiment.

【００３７】次に、図４及び図５を参照して、本実施例
のモジュールについてその製造方法を説明する。Next, with reference to FIGS. 4 and 5, a method of manufacturing the module of this embodiment will be described.

【００３８】まず、焼結法により伝送配線及び前記受動
素子を形成した多層構造のアルミナ基板（０．５ｍｍ
厚）を用意する。該アルミナ基板１の回路基板搭載側に
は、アルミナ基板形成加工時、ＭＯＳＦＥＴ１０１が実
装可能な程度の大きさの凹部１０２を形成しておく。凹
部１０２の深さは、ＭＯＳＦＥＴ１０１搭載後、ＭＯＳ
ＦＥＴの裏面がアルミナ基板１の回路基板搭載側の面と
同等の高さになるような寸法にする。凹部１０２のＭＯ
ＳＦＥＴ搭載面にはＡｌ配線が形成されており、ＭＯＳ
ＦＥＴとの接続用バンプ１０４も同時に形成されてい
る。First, an alumina substrate (0.5 mm) having a multilayer structure in which the transmission wiring and the passive element are formed by a sintering method.
Thickness) is prepared. On the circuit board mounting side of the alumina substrate 1, a recess 102 having a size large enough to mount the MOSFET 101 at the time of forming the alumina substrate is formed. The depth of the recess 102 is determined by mounting the MOSFET 101,
The size is set so that the back surface of the FET has the same height as the surface of the alumina substrate 1 on the circuit board mounting side. MO of recess 102
Al wiring is formed on the SFET mounting surface,
The bump 104 for connection with the FET is also formed at the same time.

【００３９】また、アルミナ基板の上面にはコンデン
サ、ソレノイド、抵抗等の部品１１１の搭載に対応する
ように電極配線が形成され、集積回路素子１０９を搭載
する領域にはＭＯＳＦＥＴ搭載部と同様の凹部１１４が
設けられている。この凹部１１４はアルミナ基板形成加
工時に同時に形成することができる。なお、前記凹部１
１４の底面には集積回路搭載用配線、放熱用配線、ある
いはグランド接続用配線等を形成しても良い。しかし、
金属バンプは形成しない。Further, electrode wiring is formed on the upper surface of the alumina substrate so as to correspond to the mounting of components 111 such as capacitors, solenoids and resistors, and a recess similar to that of the MOSFET mounting portion is formed in the area where the integrated circuit element 109 is mounted. 114 is provided. The recess 114 can be formed simultaneously with the alumina substrate forming process. The recess 1
An integrated circuit mounting wiring, a heat radiation wiring, a ground connection wiring, or the like may be formed on the bottom surface of 14. But,
No metal bumps are formed.

【００４０】次に、図６を参照して、アルミナ基板への
ＭＯＳＦＥＴ搭載からアルミナ基板の回路基板への搭載
までの製造フローを説明する。Next, with reference to FIG. 6, a manufacturing flow from mounting the MOSFET on the alumina substrate to mounting the alumina substrate on the circuit board will be described.

【００４１】先ず、超音波を併用したフリップチップ接
続法を用い、上記アルミナ基板の凹部にＭＯＳＦＥＴを
接続する（（ａ）〜（ｂ））。なお、接続に際して熱を
加えても良い。次に、アルミナ基板上の所定の位置（ア
ルミナ基板のＭＯＳＦＥＴ搭載面の裏側）に、コンデン
サ、ソレノイド、抵抗等の部品をＰｂを９０ｗｔ％、Ｓ
ｎを１０ｗｔ％含むペーストろう材を介して配置する。
このＰｂを主体としたペーストろう材の融点は、ＭＯＳ
ＦＥＴ搭載後のアルミナ基板を回路基板上に搭載する際
に用いられるＳｎを主体としたペーストろう材よりも高
い。また、集積回路素子は凹部に同様に配置する。次い
で、３３０℃程度の高温下でコンデンサ、ソレノイド、
抵抗等の部品、及び集積回路素子をろう付けする
（ｃ）。First, a MOSFET is connected to the concave portion of the alumina substrate by using a flip chip connection method using ultrasonic waves ((a)-(b)). Note that heat may be applied when connecting. Next, at a predetermined position on the alumina substrate (the backside of the MOSFET mounting surface of the alumina substrate), components such as a capacitor, a solenoid and a resistor are provided with 90 wt% of Pb and S
It is arranged via a paste brazing material containing 10 wt% of n.
The melting point of this Pb-based paste brazing material is MOS.
It is higher than the paste brazing material mainly composed of Sn used when mounting the alumina substrate after mounting the FET on the circuit board. Further, the integrated circuit element is similarly arranged in the recess. Then, at a high temperature of about 330 ° C, a condenser, a solenoid,
Components such as resistors and integrated circuit elements are brazed (c).

【００４２】次に、集積回路素子上に形成した電極パッ
ドとアルミナ基板上に形成した電極とを、φ３０μｍの
Ａｕワイヤを用いて超音波振動を併用したワイヤボンデ
ィング法により接続する（ｄ）。次に、アルミナ基板上
に搭載したコンデンサ、ソレノイド、抵抗、集積回路素
子等の部品上にエポキシ樹脂を所定の型を用いて流し込
み、そのまま１２０℃程度の高温下でエポキシ樹脂を固
化させる（ｅ）。Next, the electrode pad formed on the integrated circuit element and the electrode formed on the alumina substrate are connected by a wire bonding method using ultrasonic vibration together with an Au wire of φ30 μm (d). Next, an epoxy resin is poured onto components such as capacitors, solenoids, resistors, and integrated circuit elements mounted on an alumina substrate using a predetermined mold, and the epoxy resin is solidified at a high temperature of about 120 ° C. (e). .

【００４３】次に、アルミナ基板の回路基板搭載部、及
びアルミナ基板に搭載したＭＯＳＦＥＴの裏面に対応す
る配線上にＳｎ系ろう材ペーストをスクリーン印刷す
る。このときのＳｎ系ろう材ペーストの厚さはおよそ５
００μｍである。次に、前記Ｓｎ系ろう材ペーストが印
刷された回路基板上に、ＭＯＳＦＥＴを搭載したアルミ
ナ基板を位置合せして載置し（ｆ）、その後、ピーク温
度２６０℃のリフロー炉を通す。これによりＭＯＳＦＥ
Ｔを搭載したアルミナ基板の回路基板への搭載が完了
し、本実施例の高周波パワーモジュールが完成する
（ｇ）。Next, a Sn-based brazing material paste is screen-printed on the circuit board mounting portion of the alumina substrate and the wiring corresponding to the back surface of the MOSFET mounted on the alumina substrate. At this time, the thickness of the Sn-based brazing filler metal paste is about 5
It is 00 μm. Next, the alumina substrate on which the MOSFET is mounted is aligned and placed on the circuit board on which the Sn-based brazing material paste is printed (f), and then the reflow furnace having a peak temperature of 260 ° C. is passed. This allows MOSFE
The mounting of the alumina substrate on which T is mounted on the circuit board is completed, and the high frequency power module of this embodiment is completed (g).

【００４４】本実施例では、ペーストろう材を用いるた
め、ＭＯＳＦＥＴを搭載したアルミナ基板の高さのばら
つきはキャンセルされる。また、コンデンサ、ソレノイ
ド、抵抗、集積回路素子等の部品搭載に用いたペースト
ろう材はＰｂ主成分のろう材でＳｎ系ろう材よりも融点
が高いため、アルミナ基板の回路基板搭載時に再溶融す
ることはない。なお、高周波パワーモジュールは、同一
の回路基板上に搭載された他の部品の何れかよりも高さ
が低いことが望ましい（ｂ）。In this embodiment, since the paste brazing material is used, the variation in the height of the alumina substrate on which the MOSFET is mounted is canceled. Further, since the paste brazing material used for mounting components such as capacitors, solenoids, resistors and integrated circuit elements is a Pb-based brazing material and has a higher melting point than the Sn-based brazing material, it remelts when the alumina substrate is mounted on the circuit board. There is no such thing. It is desirable that the high frequency power module has a lower height than any of the other components mounted on the same circuit board (b).

【００４５】なお、ＭＯＳＦＥＴを搭載したアルミナ基
板の凹部には、機械的衝撃及び湿気等を原因とする化学
変化からＭＯＳＦＥＴを保護するため、樹脂を充填する
ことが望ましい。また、図４及び図５は本発明の一実施
例であり、各素子の配置はこれに限定されるものではな
い。また、ＭＯＳＦＥＴのような能動素子は単数、また
は３素子以上搭載してもよい。発熱源であるパワーＭＯ
ＳＦＥＴからの放熱は、パワーＭＯＳＦＥＴの裏面全体
から熱伝導性に優れる金属材料（Ｓｎ系ろう材、及び回
路基板上に形成した放熱電極板）を介して放熱するた
め、放熱を高効率に行うことができる また、図５において、回路基板１０３上に形成した放熱
配線板１０５が回路基板１０３上に形成した配線１０８
と独立している構造であってもよい。なお、本実施例に
おいて、アルミナ基板凹部のＭＯＳＦＥＴ搭載面に、Ａ
ｕ配線が形成され、かつＭＯＳＦＥＴとの接続用バンプ
がＡｕ製であってもよい。また、アルミナ基板の代わり
に、ガラス−セラミック製、窒化アルミ製、ガラス製、
及び有機材料製の多層配線基板であってもよい。また、
図７、図８に示すように基板の集積回路素子１０９搭載
部に凹部を設けないで、基板上に集積回路素子を直接配
置することができる。It should be noted that it is desirable to fill the concave portion of the alumina substrate on which the MOSFET is mounted with resin in order to protect the MOSFET from chemical changes caused by mechanical shock and moisture. 4 and 5 show one embodiment of the present invention, and the arrangement of each element is not limited to this. Further, a single active element such as MOSFET or three or more active elements may be mounted. Power MO that is a heat source
Since heat is radiated from the SFET through the metal material (Sn-based brazing material and heat radiating electrode plate formed on the circuit board) having excellent thermal conductivity from the entire back surface of the power MOSFET, heat must be radiated with high efficiency. In addition, in FIG. 5, the heat dissipation wiring board 105 formed on the circuit board 103 is connected to the wiring 108 formed on the circuit board 103.
The structure may be independent of. In addition, in the present embodiment, A
The u wiring may be formed and the bump for connecting to the MOSFET may be made of Au. Further, instead of the alumina substrate, glass-ceramic, aluminum nitride, glass,
It may also be a multilayer wiring board made of an organic material. Also,
As shown in FIGS. 7 and 8, it is possible to directly arrange the integrated circuit element on the substrate without providing a recess in the integrated circuit element 109 mounting portion of the substrate.

【００４６】（実施例３）図９は、本発明の一実施例で
ある半導体モジュール１００の構成を示した概略図であ
り、図１０は図９のＣ−Ｃ’部の断面図である。本実施
例半導体モジュールの厚さは０．４５ｍｍである。(Embodiment 3) FIG. 9 is a schematic view showing the structure of a semiconductor module 100 which is an embodiment of the present invention, and FIG. 10 is a sectional view taken along the line CC 'of FIG. The thickness of the semiconductor module of this embodiment is 0.45 mm.

【００４７】図９及び図１０において、１はガラス−セ
ラミック製基板である。基板１は多層構造になってお
り、層間に伝送配線１０７が形成され、コンデンサ、抵
抗、インダクタ等の受動素子も形成されている。また、
基板１には、半導体材料で構成されたＭＯＳＦＥＴ素子
１０１を実装するための凹部１０２が形成されている。
１０３は基板１を実装する回路基板、１０４はＭＯＳＦ
ＥＴ素子１０１と基板１とを電気的に接続するためのＡ
ｌ製バンプである。ＭＯＳＦＥＴ素子１０１の実装面と
は反対側の面（下面）と回路基板１０３とは、回路基板
１０３上に形成した放熱配線板１０５とＳｎ系ろう材１
０６とを介して接続されている。放熱配線板１０５は、
ＭＯＳＦＥＴ素子１０１より幅広く、かつ凹部１０２よ
り狭くなるよう配置されている。１０８は回路基板１０
３上に形成した配線であり、基板１とＳｎ系ろう材１０
６を介して電気的に接続されている。放熱配線板１０５
は、回路基板１０３上に形成した配線１０８の一部とし
ても機能する。１１１は基板１上に金属ろう材（図示せ
ず）を介して搭載されたコンデンサ、ソレノイド、抵抗
等の部品、１０９は基板１上に金属ろう材（図示せず）
を介して搭載さた集積回路素子、１１４は集積回路素子
１０９を搭載するための基板１に形成した凹部、１１０
は基板１上に搭載されたコンデンサ、ソレノイド、抵抗
等の部品１１１及び集積回路素子１０９を覆うように形
成されたエポキシ樹脂である。In FIGS. 9 and 10, reference numeral 1 is a glass-ceramic substrate. The substrate 1 has a multi-layer structure, the transmission wiring 107 is formed between layers, and passive elements such as capacitors, resistors, and inductors are also formed. Also,
The substrate 1 is provided with a recess 102 for mounting a MOSFET element 101 made of a semiconductor material.
103 is a circuit board on which the board 1 is mounted, and 104 is a MOSF
A for electrically connecting the ET element 101 and the substrate 1
It is a l-made bump. The surface (lower surface) opposite to the mounting surface of the MOSFET element 101 and the circuit board 103 are the heat radiation wiring board 105 and the Sn-based brazing material 1 formed on the circuit board 103.
06 are connected to each other. The heat dissipation wiring board 105 is
It is arranged so as to be wider than the MOSFET element 101 and narrower than the recess 102. 108 is the circuit board 10
Wirings formed on the substrate 3, the substrate 1 and the Sn-based brazing material 10
It is electrically connected via 6. Heat dissipation wiring board 105
Also functions as a part of the wiring 108 formed on the circuit board 103. 111 is a component such as a capacitor, solenoid or resistor mounted on the substrate 1 via a metal brazing material (not shown), and 109 is a metal brazing material (not shown) on the substrate 1.
Integrated circuit element mounted via the substrate, 114 is a recess formed in the substrate 1 for mounting the integrated circuit element 109, and 110
Is an epoxy resin formed so as to cover the components 111 such as capacitors, solenoids and resistors mounted on the substrate 1 and the integrated circuit element 109.

【００４８】本実施例における半導体モジュールは、放
熱配線板１０５、回路基板１０３上に形成した配線１０
８、Ｓｎ系ろう材１０６、ＭＯＳＦＥＴ素子１０１、Ｍ
ＯＳＦＥＴ素子１０１を実装した基板１、基板１上に搭
載されたコンデンサ、ソレノイド、抵抗等の部品１１
１、集積回路素子１０９、並びに基板１上に搭載された
部品１１１及び集積回路素子１０９を覆うように形成し
たエポキシ樹脂からなる集合体を指す。なお、本実施例
におけるコンデンサ、抵抗、インダクタを構成した基板
については実施例１と同様である。In the semiconductor module of this embodiment, the wiring 10 formed on the heat dissipation wiring board 105 and the circuit board 103 is used.
8, Sn-based brazing material 106, MOSFET element 101, M
Substrate 1 on which the OSFET element 101 is mounted, and components 11 such as capacitors, solenoids and resistors mounted on the substrate 1
1, an integrated circuit element 109, and an assembly made of an epoxy resin formed so as to cover the component 111 mounted on the substrate 1 and the integrated circuit element 109. The substrate on which the capacitors, resistors, and inductors in this embodiment are formed is the same as in the first embodiment.

【００４９】次に、図９及び図１０を参照して本実施例
モジュールについてその製造方法を説明する。Next, a method of manufacturing the module of this embodiment will be described with reference to FIGS.

【００５０】まず、焼結法により伝送配線及び前記受動
素子が形成された多層構造のガラス−セラミック基板
（０．３０ｍｍ厚）を用意した。ガラス−セラミック基
板１の回路基板搭載側には、ＭＯＳＦＥＴが実装可能な
程度の大きさの凹部１０２がガラス−セラミック基板形
成加工時に同時に形成されている。凹部１０２の深さ
は、ＭＯＳＦＥＴ搭載後、ＭＯＳＦＥＴの裏面がガラス
−セラミック基板１の回路基板搭載側の面と同等の高さ
になるような寸法にする。凹部１０２のＭＯＳＦＥＴ搭
載面にはＡｌ配線が形成されており、ＭＯＳＦＥＴとの
接続用バンプも同時に形成されている。コンデンサ、ソ
レノイド、抵抗等の部品１１１及び集積回路素子１０９
を搭載する側の面にはコンデンサ、ソレノイド、抵抗等
の部品搭載に対応するように電極配線が形成され、集積
回路素子１０９を搭載する領域にはＭＯＳＦＥＴ搭載部
と同様の凹部１１４が設けられている。この凹部１１４
はガラス−セラミック基板形成加工時に同時に形成され
る。この集積回路搭載用凹部の底面には集積回路搭載用
配線が形成されている。First, a glass-ceramic substrate (0.30 mm thick) having a multi-layer structure in which the transmission wiring and the passive element were formed by a sintering method was prepared. On the circuit board mounting side of the glass-ceramic substrate 1, a recess 102 having a size large enough to mount a MOSFET is formed at the same time when the glass-ceramic substrate is formed. The depth of the recess 102 is set such that after mounting the MOSFET, the back surface of the MOSFET has the same height as the surface of the glass-ceramic substrate 1 on the circuit board mounting side. Al wiring is formed on the MOSFET mounting surface of the recess 102, and a bump for connection with the MOSFET is also formed at the same time. Parts 111 such as capacitors, solenoids, and resistors, and integrated circuit elements 109
Electrode wiring is formed on the surface on which the ICs are mounted so as to accommodate components such as capacitors, solenoids and resistors, and a recess 114 similar to the MOSFET mounting section is provided in the area where the integrated circuit element 109 is mounted. There is. This recess 114
Are simultaneously formed during the glass-ceramic substrate forming process. The integrated circuit mounting wiring is formed on the bottom surface of the integrated circuit mounting recess.

【００５１】次に、図１１を参照して、ガラス−セラミ
ック基板へのＭＯＳＦＥＴ搭載からガラス−セラミック
基板の回路基板への搭載までの製造フローを説明する。Next, with reference to FIG. 11, a manufacturing flow from mounting the MOSFET on the glass-ceramic substrate to mounting the glass-ceramic substrate on the circuit board will be described.

【００５２】先ず、超音波を併用したフリップチップ接
続法を用い、上記ガラス−セラミック基板の凹部にＭＯ
ＳＦＥＴを接続する（（ａ）〜（ｂ））。なお、このと
き熱を加えても良い。次に、ガラス−セラミック基板上
の所定の位置にコンデンサ、ソレノイド、抵抗等の部品
をＰｂ９０ｗｔ％、Ｓｎを１０ｗｔ％含むペーストろう
材を介して配置する。このＰｂを主体としたペーストろ
う材の融点は、ＭＯＳＦＥＴ搭載後のアルミナ基板を回
路基板上に搭載する際に用いられるＳｎを主体としたペ
ーストろう材よりも高い。また、集積回路素子は凹部に
同様に配置する。なお、集積回路素子主面に形成した外
部配線との結線用電極（電極パッド）上には、めっき法
により前記Ｐｂを主体としたペーストろう材と同等の組
成のＰｂ９０ｗｔ％−Ｓｎ１０ｗｔ％バンプが形成され
ている。このため、集積回路素子は、前記バンプが対応
するアルミナ基板凹部の底面に形成した配線電極上に位
置するように配置する。First, by using the flip-chip connection method using ultrasonic waves in combination, the MO is formed in the concave portion of the glass-ceramic substrate.
SFET is connected ((a)-(b)). At this time, heat may be applied. Next, components such as a capacitor, a solenoid, and a resistor are arranged at predetermined positions on the glass-ceramic substrate through a paste brazing material containing 90 wt% of Pb and 10 wt% of Sn. The melting point of the Pb-based paste brazing material is higher than that of the Sn-based paste brazing material used when mounting the alumina substrate after mounting the MOSFET on the circuit board. Further, the integrated circuit element is similarly arranged in the recess. On the electrode (electrode pad) for connection with the external wiring formed on the main surface of the integrated circuit element, a Pb 90 wt% -Sn 10 wt% bump having the same composition as the paste brazing material mainly containing Pb was formed by a plating method. Has been done. Therefore, the integrated circuit element is arranged such that the bump is located on the wiring electrode formed on the bottom surface of the corresponding alumina substrate recess.

【００５３】次に、３３０℃程度の温度下でコンデン
サ、ソレノイド、抵抗等の部品、及び集積回路素子をろ
う付けする（ｃ）。次に、ガラス−セラミック基板上に
搭載したコンデンサ、ソレノイド、抵抗、集積回路素子
等の部品上にエポキシ樹脂を所定の型を用いて流し込
み、そのまま１２０℃程度の高温下でエポキシ樹脂を固
化させる（ｄ）。次に、ガラス−セラミック基板の回路
基板搭載部、及びガラス−セラミック基板に搭載したＭ
ＯＳＦＥＴの裏面に対応する配線上に、Ｓｎ系ろう材ペ
ーストをスクリーン印刷する。このときのＳｎ系ろう材
ペーストの厚さはおよそ５００μｍである。次に、Ｓｎ
系ろう材ペーストが印刷された回路基板上に、ＭＯＳＦ
ＥＴを搭載したガラス−セラミック基板を所定の位置に
なるよう位置合せして配置し（ｅ）、その後、ピーク温
度２５０℃のリフロー炉を通す。これによりＭＯＳＦＥ
Ｔを搭載したガラス−セラミック基板の回路基板への搭
載が完了し、本実施例の高周波パワーモジュールが完成
する（ｆ）。Next, components such as capacitors, solenoids and resistors, and integrated circuit elements are brazed at a temperature of about 330 ° C. (c). Next, an epoxy resin is poured onto parts such as capacitors, solenoids, resistors and integrated circuit elements mounted on a glass-ceramic substrate using a predetermined mold, and the epoxy resin is solidified at a high temperature of about 120 ° C. ( d). Next, the circuit board mounting portion of the glass-ceramic board and the M mounted on the glass-ceramic board
Sn-based brazing material paste is screen-printed on the wiring corresponding to the back surface of the OSFET. At this time, the Sn-based brazing material paste has a thickness of about 500 μm. Next, Sn
MOSF is printed on the circuit board where the brazing paste is printed.
The glass-ceramic substrate on which ET is mounted is aligned and arranged so as to be in a predetermined position (e), and then passed through a reflow furnace having a peak temperature of 250 ° C. This allows MOSFE
The mounting of the glass-ceramic substrate on which T is mounted on the circuit board is completed, and the high frequency power module of this embodiment is completed (f).

【００５４】本実施例では、ペーストろう材を用いるた
め、ＭＯＳＦＥＴを搭載したガラス−セラミック基板の
高さばらつきはキャンセルされる。コンデンサ、ソレノ
イド、抵抗、集積回路素子等の部品搭載に用いたペース
トろう材はＰｂ主成分のろう材でＳｎ系ろう材よりも融
点が高いため、ガラス−セラミック基板搭載時に再溶融
することはない。なお、高周波パワーモジュールは、同
一の回路基板上に搭載された他の部品の何れかよりも高
さが低いことが望ましい（ｂ）。In this embodiment, since the paste brazing material is used, the height variation of the glass-ceramic substrate on which the MOSFET is mounted is canceled. Since the paste brazing material used for mounting capacitors, solenoids, resistors, integrated circuit elements, etc. is a Pb-based brazing material and has a higher melting point than Sn-based brazing material, it does not remelt when mounted on a glass-ceramic substrate. . It is desirable that the high frequency power module has a lower height than any of the other components mounted on the same circuit board (b).

【００５５】なお、ＭＯＳＦＥＴを搭載したガラス−セ
ラミック基板の凹部には、機械的衝撃及び湿気等を原因
とする化学変化からＭＯＳＦＥＴを保護するため、樹脂
を充填することが望ましい。また、図９及び図１０は本
発明の一実施例であり、各素子の配置はこれに限定され
るものではない。また、ＭＯＳＦＥＴのような能動素子
は単数、または３素子以上搭載してもよい。発熱源であ
るパワーＭＯＳＦＥＴからの放熱は、パワーＭＯＳＦＥ
Ｔの裏面全体から熱伝導性に優れる金属材料（Ｓｎ系ろ
う材、及び回路基板上に形成した放熱電極板）を介して
放熱させるため、放熱を高効率に行うことができる。The glass-ceramic substrate on which the MOSFET is mounted is preferably filled with a resin in order to protect the MOSFET from chemical changes caused by mechanical shock and moisture. 9 and 10 show one embodiment of the present invention, and the arrangement of each element is not limited to this. Further, a single active element such as MOSFET or three or more active elements may be mounted. The heat released from the power MOSFET, which is a heat source, is generated by the power MOSFET.
Since heat is dissipated from the entire back surface of T through the metal material having excellent thermal conductivity (Sn brazing material and heat dissipation electrode plate formed on the circuit board), heat dissipation can be performed with high efficiency.

【００５６】また、図１０において、回路基板１０３上
に形成した放熱配線板１０５が回路基板１０３上に形成
した配線１０８とは独立している構造であってもよい。
なお、本実施例において、ガラス−セラミック基板凹部
のＭＯＳＦＥＴ搭載面に、Ａｕ配線が形成され、かつＭ
ＯＳＦＥＴとの接続用バンプがＡｕ製であってもよい。
ガラス−セラミック基板の代わりに、アルミナ製、窒化
アルミ製、ガラス製、及び有機材料製多層配線基板であ
ってもよい。また、本実施例において、図１２に示すよ
うに基板の集積回路素子１０９搭載部に凹部を設けなく
てもよい。Further, in FIG. 10, the heat dissipation wiring board 105 formed on the circuit board 103 may be independent of the wiring 108 formed on the circuit board 103.
In this embodiment, Au wiring is formed on the MOSFET mounting surface of the concave portion of the glass-ceramic substrate, and M
The bump for connection with the OSFET may be made of Au.
Instead of the glass-ceramic substrate, a multilayer wiring substrate made of alumina, aluminum nitride, glass, or organic material may be used. Further, in this embodiment, as shown in FIG. 12, the recess may not be provided in the integrated circuit element 109 mounting portion of the substrate.

【００５７】（実施例４）図１３は本発明の一実施例で
ある半導体モジュール１００の構成を示した概略断面図
である。本実施例半導体モジュールの厚さは０．６５ｍ
ｍである。(Embodiment 4) FIG. 13 is a schematic sectional view showing the structure of a semiconductor module 100 which is an embodiment of the present invention. The thickness of the semiconductor module of this embodiment is 0.65 m.
m.

【００５８】図１３において１は窒化アルミ製基板であ
る。基板１は多層構造になっており、層間に伝送配線１
０７が形成され、コンデンサ、抵抗、インダクタ等の受
動素子も形成されている。In FIG. 13, 1 is a substrate made of aluminum nitride. The substrate 1 has a multi-layer structure, and the transmission wiring 1 is provided between the layers.
07 are formed, and passive elements such as capacitors, resistors, and inductors are also formed.

【００５９】また、基板１には半導体材料で構成された
ＭＯＳＦＥＴ素子１０１を実装するための凹部１０２が
形成されている。１０３は基板１を実装する回路基板、
１０４はＭＯＳＦＥＴ素子１０１と基板１とを電気的に
接続するためのＡｌ製バンプである。ＭＯＳＦＥＴ素子
１０１の実装面とは反対側の面（下面）と回路基板１０
３とは、回路基板１０３上に形成した放熱配線板１０５
とＳｎ系ろう材１０６とを介して接続されている。放熱
配線板１０５はＭＯＳＦＥＴ素子１０１より幅広く、か
つ凹部１０２より狭くなるよう配置されている。１０８
は回路基板１０３上に形成した配線であり、基板１とＳ
ｎ系ろう材１０６を介して電気的に接続されている。放
熱配線板１０５は、回路基板１０３上に形成した配線１
０８の一部としても機能している。１１１は基板１上に
金属ろう材（図示せず）を介して搭載したコンデンサ、
ソレノイド、抵抗等の部品、１０９は基板１上に金属ろ
う材（図示せず）を介して搭載さた集積回路素子、１１
５は集積回路素子１０９と基板１上に形成した電極とを
電気的に接続するためのボンディングワイヤ、１１４は
集積回路素子１０９を搭載するための基板１に形成した
凹部、１１２は基板１上に搭載されたコンデンサ、ソレ
ノイド、抵抗等の部品１１１、及び集積回路素子１０
９、ボンディングワイヤ１１５等を覆うようにポッティ
ング法により形成された封止樹脂、１１３は基板１上に
搭載されたコンデンサ、ソレノイド、抵抗、集積回路素
子等の部品１１１、１０９及び封止樹脂１１２を保護
し、かつ外部からの磁場、高調波等を遮蔽するための金
属製のキャップである。Further, the substrate 1 is provided with a recess 102 for mounting a MOSFET element 101 made of a semiconductor material. 103 is a circuit board on which the board 1 is mounted,
Reference numeral 104 is an Al bump for electrically connecting the MOSFET element 101 and the substrate 1. The circuit board 10 and the surface (lower surface) opposite to the mounting surface of the MOSFET element 101.
3 is a heat dissipation wiring board 105 formed on the circuit board 103.
And a Sn-based brazing material 106. The heat dissipation wiring board 105 is arranged so as to be wider than the MOSFET element 101 and narrower than the recess 102. 108
Is a wiring formed on the circuit board 103,
It is electrically connected via an n-based brazing material 106. The heat dissipation wiring board 105 is a wiring 1 formed on the circuit board 103.
It also functions as part of 08. 111 is a capacitor mounted on the substrate 1 via a metal brazing material (not shown),
Components such as solenoids and resistors, 109 is an integrated circuit element mounted on the substrate 1 via a metal brazing material (not shown), 11
5 is a bonding wire for electrically connecting the integrated circuit element 109 and an electrode formed on the substrate 1, 114 is a concave portion formed on the substrate 1 for mounting the integrated circuit element 109, and 112 is on the substrate 1. Parts 111 such as mounted capacitors, solenoids, and resistors, and integrated circuit element 10
9, a sealing resin formed by a potting method so as to cover the bonding wires 115 and the like, 113 denotes parts 111 and 109 such as capacitors, solenoids, resistors, integrated circuit elements and the sealing resin 112 mounted on the substrate 1. It is a metal cap that protects and shields magnetic fields and harmonics from the outside.

【００６０】なお、本実施例における半導体モジュール
は、放熱配線板１０５、回路基板１０３上に形成した配
線１０８、Ｓｎ系ろう材１０６、ＭＯＳＦＥＴ素子１０
１、ＭＯＳＦＥＴ素子１０１を実装した基板１、基板１
上に搭載されたコンデンサ、ソレノイド、抵抗等の部品
１１１、集積回路素子１０９、封止樹脂１１２、及びキ
ャップ１１３からなる集合体を指す。なお、本実施例に
おけるコンデンサ、抵抗、インダクタを構成した基板に
ついては実施例１と同様である。In the semiconductor module of this embodiment, the heat dissipation wiring board 105, the wiring 108 formed on the circuit board 103, the Sn-based brazing material 106, and the MOSFET element 10 are used.
1, substrate 1 on which MOSFET device 101 is mounted, substrate 1
It refers to an assembly including a component 111 such as a capacitor, a solenoid, and a resistor mounted above, an integrated circuit element 109, a sealing resin 112, and a cap 113. The substrate on which the capacitors, resistors, and inductors in this embodiment are formed is the same as in the first embodiment.

【００６１】次に、本実施例のモジュールについてその
製造方法を説明刷る。Next, the manufacturing method of the module of this embodiment will be described.

【００６２】まず、焼結法により伝送配線及び前記受動
素子を形成した多層構造の窒化アルミ基板（０．５ｍｍ
厚）を用意する。窒化アルミ基板１の回路基板搭載側に
は、ＭＯＳＦＥＴ１０１が実装可能な程度の大きさの凹
部１０２が窒化アルミ基板形成加工時に同時に形成され
ている。凹部の深さは、ＭＯＳＦＥＴ搭載後、ＭＯＳＦ
ＥＴの裏面が窒化アルミ基板１の回路基板搭載側の面と
同等の高さになるような寸法にする。凹部のＭＯＳＦＥ
Ｔ搭載面にはＡｌ配線が形成されており、ＭＯＳＦＥＴ
との接続用バンプも同時に形成されている。コンデン
サ、ソレノイド、抵抗等の部品１１１、及び集積回路素
子１０９を搭載する側の面にはコンデンサ、ソレノイ
ド、抵抗等の部品搭載に対応するように電極配線が形成
され、集積回路素子を搭載する領域にはＭＯＳＦＥＴ搭
載部と同様の凹部１１４が設けられている。この凹部１
１４は窒化アルミ基板形成加工時に同時に形成すること
ができる。この集積回路搭載用凹部１１４の底面には集
積回路搭載用配線、放熱用配線、あるいはグランド接続
用配線等を形成しても良い。しかし、金属バンプは形成
しない。First, a multilayer aluminum nitride substrate (0.5 mm) in which transmission wiring and the passive element are formed by a sintering method is formed.
Thickness) is prepared. On the circuit board mounting side of the aluminum nitride substrate 1, a recess 102 of a size large enough to mount the MOSFET 101 is simultaneously formed during the aluminum nitride substrate forming process. The depth of the recess is MOSF after mounting the MOSFET.
The size of the back surface of the ET is set to be the same height as the surface of the aluminum nitride substrate 1 on the circuit board mounting side. Recessed MOSFE
Al wiring is formed on the T mounting surface,
Bumps for connection with are also formed at the same time. Electrode wiring is formed on the surface on which the parts 111 such as capacitors, solenoids and resistors and the integrated circuit element 109 are mounted so as to accommodate parts such as capacitors, solenoids and resistors, and the area where the integrated circuit elements are mounted. Is provided with a recess 114 similar to the MOSFET mounting portion. This recess 1
14 can be formed at the same time when the aluminum nitride substrate is formed. On the bottom surface of the integrated circuit mounting recess 114, an integrated circuit mounting wiring, a heat radiation wiring, a ground connection wiring, or the like may be formed. However, no metal bump is formed.

【００６３】次に、図１４を参照して、窒化アルミ基板
へのＭＯＳＦＥＴ搭載から窒化Ａｌ基板の回路基板への
搭載までの製造フローを示す。Next, with reference to FIG. 14, there is shown a manufacturing flow from mounting the MOSFET on the aluminum nitride substrate to mounting the Al nitride substrate on the circuit board.

【００６４】先ず、ＭＯＳＦＥＴを、上記窒化アルミ基
板の凹部に超音波を併用したフリップチップ接続法で接
続する（（ａ）〜（ｂ））。このとき熱を加えても良
い。次に、窒化アルミ基板上の所定の位置に、コンデン
サ、ソレノイド、抵抗等の部品をＰｂ９０ｗｔ％、Ｓｎ
を１０ｗｔ％含むペーストろう材を介して配置する。こ
のＰｂを主体としたペーストろう材の融点は、ＭＯＳＦ
ＥＴ搭載後のアルミナ基板を回路基板上に搭載する際に
用いられるＳｎを主体としたペーストろう材よりも高
い。また、集積回路素子は凹部に同様に配置する。この
とき、３３０℃程度の高温下でコンデンサ、ソレノイ
ド、抵抗等の部品、集積回路素子をろう付けする
（ｃ）。First, the MOSFET is connected to the recess of the aluminum nitride substrate by the flip-chip connection method using ultrasonic waves ((a)-(b)). At this time, heat may be applied. Next, at a predetermined position on the aluminum nitride substrate, components such as a capacitor, a solenoid, and a resistor are added with Pb of 90 wt% and Sn.
Is placed through a paste brazing material containing 10 wt% of. The melting point of this Pb-based paste brazing material is MOSF.
It is higher than the paste brazing material mainly composed of Sn used when mounting the alumina substrate after the ET mounting on the circuit board. Further, the integrated circuit element is similarly arranged in the recess. At this time, components such as capacitors, solenoids, resistors, and integrated circuit elements are brazed at a high temperature of about 330 ° C. (c).

【００６５】次に、集積回路素子上に形成した電極パッ
ドとアルミナ基板上に形成した電極とを、φ３０μｍの
Ａｕワイヤを用いて超音波振動を併用したワイヤボンデ
ィング法により接続する（ｄ）。次に、窒化アルミ基板
上に搭載したコンデンサ、ソレノイド、抵抗、集積回路
素子等の部品上にポッティング法によりゲル状の封止樹
脂を流し込み、１２０℃程度の高温下で樹脂を固化させ
る（ｅ）。その後、金属キャップを窒化アルミ基板上に
被せる（ｆ）。Next, the electrode pad formed on the integrated circuit element and the electrode formed on the alumina substrate are connected by a wire bonding method using ultrasonic vibration with an Au wire of φ30 μm (d). Next, a gel-like sealing resin is poured onto components such as capacitors, solenoids, resistors, and integrated circuit elements mounted on an aluminum nitride substrate by the potting method to solidify the resin at a high temperature of about 120 ° C (e). . Then, a metal cap is put on the aluminum nitride substrate (f).

【００６６】次に、窒化アルミ基板の回路基板搭載部及
び窒化アルミ基板に搭載したＭＯＳＦＥＴの裏面に対応
する配線上にＳｎ系ろう材ペーストをスクリーン印刷す
る。このときのＳｎ系ろう材ペーストの厚さはおよそ５
００μｍである。次に、Ｓｎ系ろう材ペーストが印刷さ
れた回路基板上に、ＭＯＳＦＥＴを搭載した窒化アルミ
基板を所定の位置になるよう位置合せして載置し
（ｇ）、その後、ピーク温度２６０℃のリフロー炉を通
す。これによりＭＯＳＦＥＴを搭載した窒化アルミ基板
の回路基板への搭載が完了し、本実施例の高周波パワー
モジュールが完成する（ｈ）。Next, Sn-based brazing material paste is screen-printed on the circuit board mounting portion of the aluminum nitride substrate and the wiring corresponding to the back surface of the MOSFET mounted on the aluminum nitride substrate. At this time, the thickness of the Sn-based brazing filler metal paste is about 5
It is 00 μm. Next, on the circuit board on which the Sn-based brazing material paste is printed, the aluminum nitride board on which the MOSFET is mounted is aligned and mounted so as to be in a predetermined position (g), and then the reflow at a peak temperature of 260 ° C. is performed. Pass through the furnace. As a result, the mounting of the aluminum nitride substrate on which the MOSFET is mounted on the circuit board is completed, and the high frequency power module of this embodiment is completed (h).

【００６７】本実施例では、ペーストろう材を用いるた
め、ＭＯＳＦＥＴを搭載した一体型基板の高さのばらつ
きはキャンセルされる。また、コンデンサ、ソレノイ
ド、抵抗、集積回路素子等の部品搭載に用いたペースト
ろう材はＰｂ主成分のろう材でＳｎ系ろう材よりも融点
が高いため、窒化アルミ基板搭載時に再溶融することは
ない。なお、高周波パワーモジュールは、同一の回路基
板上に搭載された他の部品の何れかよりも高さが低いこ
とが望ましい（ｂ）。In the present embodiment, since the paste brazing material is used, the height variation of the integrated substrate on which the MOSFET is mounted is canceled. Further, since the paste brazing material used for mounting components such as capacitors, solenoids, resistors, and integrated circuit elements is a Pb-based brazing material having a higher melting point than the Sn-based brazing material, it does not remelt when mounted on an aluminum nitride substrate. Absent. It is desirable that the high frequency power module has a lower height than any of the other components mounted on the same circuit board (b).

【００６８】なお、ＭＯＳＦＥＴを搭載した窒化アルミ
基板の凹部には、機械的衝撃及び湿気等を原因とする化
学変化からＭＯＳＦＥＴを保護するため、樹脂を充填す
ることが望ましい。また、図１３は本発明の一実施例で
あり、各素子の配置はこれに限定されるものではない。
ＭＯＳＦＥＴのような能動素子は単数、または３素子以
上搭載してもよい。発熱源であるパワーＭＯＳＦＥＴか
らの放熱は、パワーＭＯＳＦＥＴの裏面全体から熱伝導
性に優れる金属材料（Ｓｎ系ろう材、及び回路基板上に
形成した放熱電極板）を介して分散させるため、高効率
である。It should be noted that it is desirable to fill the concave portion of the aluminum nitride substrate on which the MOSFET is mounted with resin in order to protect the MOSFET from chemical changes caused by mechanical shock and moisture. Further, FIG. 13 shows one embodiment of the present invention, and the arrangement of each element is not limited to this.
A single active element such as a MOSFET or three or more active elements may be mounted. The heat radiation from the power MOSFET, which is a heat source, is distributed from the entire back surface of the power MOSFET through the metal material (Sn-based brazing material and the heat dissipation electrode plate formed on the circuit board) having excellent thermal conductivity, so that the efficiency is high. Is.

【００６９】また、図１３において、回路基板１０３上
に形成した放熱配線板１０５が回路基板１０３上に形成
した配線１０８とは独立している構造であってもよい。
なお、本実施例において、窒化アルミ基板凹部のＭＯＳ
ＦＥＴ搭載面に、Ａｕ配線が形成され、かつＭＯＳＦＥ
Ｔとの接続用バンプがＡｕ製であってもよい。窒化アル
ミ基板の代わりに、ガラス−セラミック製、アルミナ
製、ガラス製、及び有機材料製多層配線基板であっても
よい。なお、本実施例において、基板の集積回路素子１
０９搭載部に凹部を設けなくてもよい。In FIG. 13, the heat dissipation wiring board 105 formed on the circuit board 103 may be independent of the wiring 108 formed on the circuit board 103.
In this embodiment, the MOS of the concave portion of the aluminum nitride substrate is
Au wiring is formed on the FET mounting surface, and MOSFE
The bump for connection with T may be made of Au. Instead of the aluminum nitride substrate, a glass-ceramic, alumina, glass, or organic material multilayer wiring substrate may be used. In this embodiment, the integrated circuit element 1 on the substrate
The 09 mounting portion need not be provided with a recess.

【００７０】（実施例５）図１５は、本発明の一実施例
である半導体モジュール１００の構成を示した概略図で
ある。本実施例の半導体モジュールの厚さは０．５５ｍ
ｍである。(Embodiment 5) FIG. 15 is a schematic diagram showing the structure of a semiconductor module 100 which is an embodiment of the present invention. The thickness of the semiconductor module of this embodiment is 0.55 m.
m.

【００７１】図１５において、１はガラス−セラミック
製基板である。基板１は多層構造になっており、層間に
伝送配線１０７が形成され、コンデンサ、抵抗、インダ
クタ等の受動素子も形成されている。In FIG. 15, reference numeral 1 is a glass-ceramic substrate. The substrate 1 has a multi-layer structure, the transmission wiring 107 is formed between layers, and passive elements such as capacitors, resistors, and inductors are also formed.

【００７２】また、基板１には、半導体材料で構成され
たＭＯＳＦＥＴ素子１０１を実装するための凹部１０２
が形成されている。１０３は基板１が実装される回路基
板、１０４はＭＯＳＦＥＴ素子１０１と基板１とを電気
的に接続するためのＡｌ製バンプである。ＭＯＳＦＥＴ
素子１０１の実装面とは反対側の面（下面）と回路基板
１０３とは、回路基板１０３上に形成した放熱配線板１
０５とＳｎ系ろう材１０６とを介して接続されている。
放熱配線板１０５は、ＭＯＳＦＥＴ素子１０１より幅広
く、かつ凹部１０２より狭くなるよう配置されている。
１０８は回路基板１０３上に形成した配線であり、基板
１とＳｎ系ろう材１０６を介して電気的に接続されてい
る。放熱配線板１０５は、回路基板１０３上に形成した
配線１０８の一部としても機能している。１１１は基板
１上に金属ろう材（図示せず）を介して搭載されたコン
デンサ、ソレノイド、抵抗等の部品、１０９は基板１上
に金属ろう材（図示せず）を介して搭載さた集積回路素
子、１１５は集積回路素子１０９と基板１上に形成した
電極とを電気的に接続するためのボンディングワイヤ、
１１４は集積回路素子１０９を搭載するための基板１に
形成した凹部、１１２は基板１上に搭載されたコンデン
サ、ソレノイド、抵抗等の部品１１１、及び集積回路素
子１０９、ボンディングワイヤ１１５等を覆うようにポ
ッティング法により形成された封止樹脂、１１３は基板
１上に搭載されたコンデンサ、ソレノイド、抵抗、集積
回路素子等の部品１１１、１０９、封止樹脂１１２を保
護し、かつ外部からの磁場、高調波等を遮蔽するための
金属製のキャップである。Further, the substrate 1 is provided with a recess 102 for mounting a MOSFET element 101 made of a semiconductor material.
Are formed. Reference numeral 103 is a circuit board on which the substrate 1 is mounted, and 104 is a bump made of Al for electrically connecting the MOSFET element 101 and the substrate 1. MOSFET
The surface (lower surface) opposite to the mounting surface of the element 101 and the circuit board 103 are the heat radiation wiring board 1 formed on the circuit board 103.
No. 05 and Sn-based brazing material 106 are connected.
The heat dissipation wiring board 105 is arranged so as to be wider than the MOSFET element 101 and narrower than the recess 102.
Wirings 108 are formed on the circuit board 103, and are electrically connected to the board 1 through the Sn-based brazing material 106. The heat dissipation wiring board 105 also functions as a part of the wiring 108 formed on the circuit board 103. 111 is a component such as a capacitor, a solenoid, or a resistor mounted on the substrate 1 via a metal brazing material (not shown), and 109 is an integrated device mounted on the substrate 1 via a metal brazing material (not shown). A circuit element 115 is a bonding wire for electrically connecting the integrated circuit element 109 and an electrode formed on the substrate 1,
Reference numeral 114 denotes a concave portion formed on the substrate 1 for mounting the integrated circuit element 109, and 112 denotes a component 111 such as a capacitor, a solenoid, and a resistor mounted on the substrate 1 so as to cover the integrated circuit element 109, the bonding wire 115, and the like. Is a sealing resin formed by the potting method, 113 is a component 111, 109 such as capacitors, solenoids, resistors, integrated circuit elements and the like mounted on the substrate 1 and the sealing resin 112, and a magnetic field from the outside, It is a metal cap for shielding higher harmonics.

【００７３】なお、本実施例における半導体モジュール
は、放熱配線板１０５、回路基板１０３上に形成した配
線１０８、Ｓｎ系ろう材１０６、ＭＯＳＦＥＴ素子１０
１、ＭＯＳＦＥＴ素子１０１を実装した基板１、基板１
上に搭載されたコンデンサ、ソレノイド、抵抗等の部品
１１１、集積回路素子１０９、封止樹脂１１２、キャッ
プ１１３で構成される集合体を指す。また、本実施例に
おけるコンデンサ、抵抗、インダクタを構成した基板に
ついては実施例１と同様である。The semiconductor module according to the present embodiment includes the heat dissipation wiring board 105, the wiring 108 formed on the circuit board 103, the Sn-based brazing material 106, and the MOSFET element 10.
1, substrate 1 on which MOSFET device 101 is mounted, substrate 1
It refers to an assembly composed of a component 111 such as a capacitor, a solenoid, and a resistor mounted on the top, an integrated circuit element 109, a sealing resin 112, and a cap 113. The substrate on which the capacitors, resistors, and inductors in this embodiment are formed is the same as in the first embodiment.

【００７４】次に、図１５に示す本実施例モジュールに
ついてその製造方法を説明する。まず、焼結法により伝
送配線、及び前記受動素子１１１を形成した多層構造の
ガラス−セラミック基板（０．３０ｍｍ厚）を用意し
た。ガラス−セラミック基板１の回路基板搭載側には、
ＭＯＳＦＥＴ１０１が実装可能な程度の大きさの凹部１
０２がガラス−セラミック基板形成加工時に同時に形成
されている。凹部１０２の深さは、ＭＯＳＦＥＴ搭載
後、ＭＯＳＦＥＴの裏面がガラス−セラミック基板１の
回路基板搭載側の面と同等の高さになるような寸法にす
る。凹部のＭＯＳＦＥＴ搭載面にはＡｌ配線が形成され
ており、ＭＯＳＦＥＴとの接続用バンプ１０４も同時に
形成されている。コンデンサ、ソレノイド、抵抗等の部
品１１１、及び集積回路素子を搭載する側の面には前記
コンデンサ、ソレノイド、抵抗等の部品搭載に対応する
ように電極配線が形成され、集積回路素子１０９を搭載
する領域にはＭＯＳＦＥＴ搭載部と同様の凹部１１４が
設けられている。これもガラス−セラミック基板形成加
工時に同時に形成される。この集積回路搭載用凹部の底
面には集積回路搭載用配線が形成されている。Next, a method of manufacturing the module of this embodiment shown in FIG. 15 will be described. First, a glass-ceramic substrate (0.30 mm thick) having a multi-layer structure in which the transmission wiring and the passive element 111 were formed by a sintering method was prepared. On the circuit board mounting side of the glass-ceramic board 1,
Recess 1 that is large enough to mount MOSFET 101
02 is formed at the same time as the glass-ceramic substrate forming process. The depth of the recess 102 is set such that after mounting the MOSFET, the back surface of the MOSFET has the same height as the surface of the glass-ceramic substrate 1 on the circuit board mounting side. Al wiring is formed on the MOSFET mounting surface of the recess, and a bump 104 for connection with the MOSFET is also formed at the same time. Electrode wiring is formed on the surface on which the parts 111 such as capacitors, solenoids and resistors and the integrated circuit elements are mounted so as to accommodate the parts such as capacitors, solenoids and resistors, and the integrated circuit elements 109 are mounted. A recess 114 similar to the MOSFET mounting portion is provided in the region. This is also formed at the same time as the glass-ceramic substrate forming process. The integrated circuit mounting wiring is formed on the bottom surface of the integrated circuit mounting recess.

【００７５】次に、図１６を参照して、ガラス−セラミ
ック基板へのＭＯＳＦＥＴ搭載からガラス−セラミック
基板の回路基板への搭載までの製造フローを説明する。Next, with reference to FIG. 16, a manufacturing flow from mounting the MOSFET on the glass-ceramic substrate to mounting the glass-ceramic substrate on the circuit board will be described.

【００７６】先ず、ＭＯＳＦＥＴを、上記アルミナ基板
の凹部に超音波を併用したフリップチップ接続法で接続
する（（ａ）〜（ｂ））。このとき熱を加えても良い。
次に、ガラス−セラミック基板上の所定の位置に、コン
デンサ、ソレノイド、抵抗等の部品をＰｂ９０ｗｔ％、
Ｓｎを１０ｗｔ％含むペーストろう材を介して配置す
る。このＰｂを主体としたペーストろう材の融点は、Ｍ
ＯＳＦＥＴ搭載後のガラス−セラミック基板を回路基板
上に搭載する際に用いられるＳｎを主体としたペースト
ろう材よりも高い。なお、集積回路素子主面に形成した
外部配線との結線用電極（電極パッド）上には、めっき
法により前記Ｐｂを主体としたペーストろう材と同等の
組成のＰｂ９０ｗｔ％−Ｓｎ１０ｗｔ％バンプが形成さ
れている。このため、集積回路素子は、前記バンプを対
応するアルミナ基板凹部の底面に形成した配線電極上に
位置するように配置する。この後、３３０℃程度の温度
下でコンデンサ、ソレノイド、抵抗等の部品、及び集積
回路素子をろう付けする（ｃ）。First, the MOSFET is connected to the concave portion of the alumina substrate by a flip chip connection method using ultrasonic waves ((a)-(b)). At this time, heat may be applied.
Next, Pb90wt%, such as a capacitor, a solenoid, and a resistor are placed at predetermined positions on the glass-ceramic substrate.
It is arranged via a paste brazing material containing 10 wt% of Sn. The melting point of the Pb-based paste brazing material is M
It is higher than the paste brazing material mainly composed of Sn used when mounting the glass-ceramic substrate after mounting the OSFET on the circuit board. On the electrode (electrode pad) for connection with the external wiring formed on the main surface of the integrated circuit element, a Pb 90 wt% -Sn 10 wt% bump having the same composition as the paste brazing material mainly containing Pb was formed by a plating method. Has been done. Therefore, the integrated circuit element is arranged so that the bumps are located on the wiring electrodes formed on the bottom surface of the corresponding alumina substrate recesses. Thereafter, components such as capacitors, solenoids, resistors, and integrated circuit elements are brazed at a temperature of about 330 ° C. (c).

【００７７】次に、基板上に搭載したコンデンサ、ソレ
ノイド、抵抗、集積回路素子等の部品上にポッティング
法によりゲル状の封止樹脂を流し込み、１２０℃程度の
高温下で樹脂を固化させる（ｄ）。その後、金属キャッ
プをガラス−セラミック基板上に被せる（ｅ）。Next, a gel-like sealing resin is poured by a potting method onto parts such as capacitors, solenoids, resistors and integrated circuit elements mounted on the substrate, and the resin is solidified at a high temperature of about 120 ° C. (d). ). Then, a metal cap is put on the glass-ceramic substrate (e).

【００７８】次に、回路基板上に形成された、ガラス−
セラミック基板の回路基板搭載部、及びガラス−セラミ
ック基板に搭載したＭＯＳＦＥＴの裏面に対応する配線
上に、Ｓｎ系ろう材ペーストをスクリーン印刷する。こ
のときのＳｎ系ろう材ペーストの厚さはおよそ５００μ
ｍである。次に、このＳｎ系ろう材ペーストが印刷され
た回路基板上に、ＭＯＳＦＥＴを搭載したガラス−セラ
ミック基板を所定の位置になるよう位置合せして置かれ
（ｆ）、その後、ピーク温度２５０℃のリフロー炉を通
す。これによりＭＯＳＦＥＴを搭載したガラス−セラミ
ック基板の回路基板への搭載が完了し、本実施例の高周
波パワーモジュールが完成する（ｇ）。Next, the glass formed on the circuit board
The Sn-based brazing material paste is screen-printed on the circuit board mounting portion of the ceramic substrate and the wiring corresponding to the back surface of the MOSFET mounted on the glass-ceramic substrate. At this time, the thickness of the Sn-based brazing filler metal paste is approximately 500 μm.
m. Next, the glass-ceramic substrate on which the MOSFET is mounted is aligned and placed on the circuit board on which the Sn-based brazing paste is printed (f), and then the peak temperature of 250 ° C. Pass through the reflow oven. As a result, the mounting of the glass-ceramic substrate on which the MOSFET is mounted on the circuit board is completed, and the high frequency power module of this embodiment is completed (g).

【００７９】本実施例では、ペーストろう材を用いるた
め、ＭＯＳＦＥＴを搭載したガラス−セラミック基板の
高さばらつきはキャンセルされる。コンデンサ、ソレノ
イド、抵抗、集積回路素子等の部品搭載に用いたペース
トろう材はＰｂ主成分のろう材でＳｎ系ろう材よりも融
点が高いため、ガラス−セラミック基板搭載時に再溶融
することはない。なお、高周波パワーモジュールは、同
一の回路基板上に搭載された他の部品の何れかよりも高
さが低いことが望ましい（ｂ）。In this embodiment, since the paste brazing material is used, the height variation of the glass-ceramic substrate on which the MOSFET is mounted is canceled. Since the paste brazing material used for mounting capacitors, solenoids, resistors, integrated circuit elements, etc. is a Pb-based brazing material and has a higher melting point than Sn-based brazing material, it does not remelt when mounted on a glass-ceramic substrate. . It is desirable that the high frequency power module has a lower height than any of the other components mounted on the same circuit board (b).

【００８０】なお、ＭＯＳＦＥＴが搭載されたガラス−
セラミック基板の凹部には、機械的衝撃及び湿気等を原
因とする化学変化からＭＯＳＦＥＴを保護するため、樹
脂を充填することが望ましい。また、図１５は本発明の
一実施例であり、各素子の配置はこれに限定されるもの
ではない。ＭＯＳＦＥＴのような能動素子は単数、また
は３素子以上搭載してもよい。発熱源であるパワーＭＯ
ＳＦＥＴからの放熱は、パワーＭＯＳＦＥＴの裏面全体
から熱伝導性に優れる金属材料（Ｓｎ系ろう材、及び回
路基板上に形成した放熱電極板）を介して分散するた
め、放熱を高効率に行うことができる。The glass on which the MOSFET is mounted
It is desirable to fill the concave portion of the ceramic substrate with resin in order to protect the MOSFET from chemical changes caused by mechanical shock and moisture. Further, FIG. 15 shows one embodiment of the present invention, and the arrangement of each element is not limited to this. A single active element such as a MOSFET or three or more active elements may be mounted. Power MO that is a heat source
Since the heat radiation from the SFET is dispersed from the entire back surface of the power MOSFET through the metal material (Sn-based brazing material and the heat radiation electrode plate formed on the circuit board) having excellent thermal conductivity, the heat radiation should be performed with high efficiency. You can

【００８１】また、図１５において、回路基板１０３上
に形成した放熱配線板１０５が回路基板１０３上に形成
した配線１０８とは独立している構造であってもよい。
なお、本実施例において、ガラス−セラミック基板凹部
のＭＯＳＦＥＴ搭載面に、Ａｕ配線が形成され、かつＭ
ＯＳＦＥＴとの接続用バンプがＡｕ製であってもよい。
また、ガラス−セラミック基板の代わりに、アルミナ
製、窒化アルミ製、ガラス製、及び有機材料製多層配線
基板であってもよい。また、ガラス−セラミック基板の
集積回路素子１０９搭載部に凹部を設けなくてもよい。In FIG. 15, the heat dissipation wiring board 105 formed on the circuit board 103 may be independent of the wiring 108 formed on the circuit board 103.
In this embodiment, Au wiring is formed on the MOSFET mounting surface of the concave portion of the glass-ceramic substrate, and M
The bump for connection with the OSFET may be made of Au.
Further, instead of the glass-ceramic substrate, a multilayer wiring substrate made of alumina, aluminum nitride, glass, or organic material may be used. Further, the recess may not be provided in the integrated circuit element 109 mounting portion of the glass-ceramic substrate.

【００８２】（実施例６）本実施例では、図２、図５、
図８、図１０、図１２、図１３、及び図１５におけるＡ
ｌ製バンプ１０４をＡｕ製バンプに置換する。また、モ
ジュールの製造に際しては、ＭＯＳＦＥＴの電極パッド
部に超音波併用熱圧着法によりＡｕ、またはＡｕ合金製
バンプを形成する（これ以外はは全て実施例１、実施例
２、実施例３、実施例４、及び実施例５と同様であ
る）。超音波併用熱圧着法による前記Ａｕバンプ形成は
接合温度１７０℃で行うことができる。なお、このとき
基板のＭＯＳＦＥＴ搭載用凹部にはＡｌ製バンプは形成
されていない。さらにフリップチップ接続前には、基板
の表面にＡｒガスによるプラズマクリーニングを施して
おくことが望ましい。(Embodiment 6) In this embodiment, as shown in FIGS.
A in FIGS. 8, 10, 12, 13, and 15.
The l-made bumps 104 are replaced with Au-made bumps. Further, when manufacturing the module, bumps made of Au or Au alloy are formed on the electrode pad portion of the MOSFET by the ultrasonic combined thermocompression bonding method (other than this, all of Example 1, Example 2, Example 3, and Example 3 are performed). (Similar to Example 4 and Example 5). The Au bumps can be formed by the thermocompression bonding method using ultrasonic waves at a bonding temperature of 170 ° C. At this time, no Al bump is formed in the MOSFET mounting recess of the substrate. Furthermore, it is desirable to perform plasma cleaning with Ar gas on the surface of the substrate before flip-chip connection.

【００８３】以上説明した各実施例は、セルラー電話機
等の送信部に用いる高周波電力増幅装置の製造に適用で
きる。Each of the embodiments described above can be applied to the manufacture of a high frequency power amplifier used in a transmitter of a cellular telephone or the like.

【００８４】図１７は、本実施例の半導体モジュールを
適用した携帯電話の回路ブロック図である。マイクロホ
ンから入力する入力音声信号は混合器において発信器か
らの高周波信号に変換され、電力増幅器である絶縁型半
導体装置（ＭＯＳＦＥＴ）、アンテナ共用器を通してア
ンテナから電波として発射される。送信電力は結合器に
よってモニタされ、該モニタ出力を電力増幅器である絶
縁型半導体装置に帰還することによって一定に保たれて
いる。この携帯電話には８００〜１０００ＭＨｚ帯の電
波が使用されている。以上、本発明の実施例を高周波電
力増幅器に関連して説明したが、本発明の半導体モジュ
ール１００は、実施例記載の範囲に限定されるものでは
ない。FIG. 17 is a circuit block diagram of a mobile phone to which the semiconductor module of this embodiment is applied. An input audio signal input from a microphone is converted into a high frequency signal from a transmitter in a mixer, and is emitted as a radio wave from an antenna through an insulating semiconductor device (MOSFET) which is a power amplifier and an antenna duplexer. The transmission power is monitored by a coupler and is kept constant by feeding back the monitor output to an insulating semiconductor device which is a power amplifier. This mobile phone uses radio waves in the 800 to 1000 MHz band. Although the embodiments of the present invention have been described above in relation to the high frequency power amplifier, the semiconductor module 100 of the present invention is not limited to the scope described in the embodiments.

【００８５】以上説明したように、本発明の各実施例に
よれば、例えば抵抗、コンデンサ、ソレノイド等を含む
回路を内部に形成した多層基板の一方の面に凹部を設
け、該凹部の底面に形成した配線と半導体素子の主面
を、前記配線側に予め形成した金属突起物（バンプ）を
介して接続し、更にこのようにして形成した多層基板と
回路基板をＳｎを含む１種類の金属ろう材を介して接合
するので、半導体モジュールの小型化、薄型化を達成す
ることができる。As described above, according to each of the embodiments of the present invention, a concave portion is provided on one surface of a multilayer substrate in which a circuit including, for example, a resistor, a capacitor and a solenoid is formed, and the bottom surface of the concave portion is formed. The formed wiring and the main surface of the semiconductor element are connected to each other through a metal protrusion (bump) formed in advance on the wiring side, and the multilayer substrate and circuit board thus formed are made of one kind of metal containing Sn. Since the joining is performed through the brazing material, the semiconductor module can be downsized and thinned.

【００８６】[0086]

【発明の効果】以上説明したように本発明によれば、実
装面積を縮小化し薄型化可能な高周波パワーモジュール
を提供することができる。As described above, according to the present invention, it is possible to provide a high frequency power module which can be reduced in mounting area and thinned.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例１の半導体モジュールの構成を示した概
略図である。FIG. 1 is a schematic diagram showing a configuration of a semiconductor module of Example 1.

【図２】図１のＡ−Ａ’部の断面図である。2 is a cross-sectional view taken along the line A-A 'in FIG.

【図３】実施例１のＭＯＳＦＥＴ搭載から回路基板搭載
までの製造フローを示す図である。FIG. 3 is a diagram showing a manufacturing flow from mounting the MOSFET to mounting the circuit board according to the first embodiment.

【図４】実施例２の半導体モジュールの構成を示した概
略図である。FIG. 4 is a schematic diagram showing a configuration of a semiconductor module of Example 2.

【図５】図４のＢ−Ｂ’部の断面図である。5 is a cross-sectional view of a B-B 'portion in FIG.

【図６】実施例２のＭＯＳＦＥＴ搭載から回路基板搭載
までの製造フローを示す図である。FIG. 6 is a diagram showing a manufacturing flow from mounting the MOSFET to mounting the circuit board according to the second embodiment.

【図７】実施例２の変形例を示した概略図である。FIG. 7 is a schematic diagram showing a modification of the second embodiment.

【図８】図７のＢ−Ｂ’部の断面図である。8 is a cross-sectional view taken along the line B-B 'of FIG.

【図９】実施例３の半導体モジュールの構成を示した概
略図である。FIG. 9 is a schematic diagram showing the configuration of a semiconductor module of Example 3;

【図１０】図９のＣ−Ｃ’部の断面図である。10 is a cross-sectional view taken along the line C-C 'of FIG.

【図１１】実施例３のＭＯＳＦＥＴ搭載から回路基板搭
載までの製造フローである。FIG. 11 is a manufacturing flow from mounting the MOSFET to mounting the circuit board according to the third embodiment.

【図１２】実施例３の変形例を示した概略図である。FIG. 12 is a schematic diagram showing a modification of the third embodiment.

【図１３】実施例４の半導体モジュールの構成を示した
概略図である。FIG. 13 is a schematic diagram showing a configuration of a semiconductor module of Example 4.

【図１４】実施例４のＭＯＳＦＥＴ搭載から回路基板搭
載までの製造フローである。FIG. 14 is a manufacturing flow from mounting the MOSFET to mounting the circuit board according to the fourth embodiment.

【図１５】実施例５の半導体モジュールの構成を示した
概略図である。FIG. 15 is a schematic diagram showing the configuration of a semiconductor module of Example 5;

【図１６】実施例５のＭＯＳＦＥＴ搭載から回路基板搭
載までの製造フローである。FIG. 16 is a manufacturing flow from mounting the MOSFET to mounting the circuit board according to the fifth embodiment.

【図１７】本発明の実施例の半導体モジュールを適用し
た携帯電話の回路ブロック図である。FIG. 17 is a circuit block diagram of a mobile phone to which the semiconductor module of the embodiment of the invention is applied.

【図１８】従来例を示した図である。FIG. 18 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

１…基板（多層基板）、１００…半導体モジュール、１
０１…ＭＯＳＦＥＴ、１０２…凹部、１０３…回路基
板、１０４…バンプ、１０５…放熱配線板、１０６…Ｓ
ｎ系ろう材、１０７…伝送配線、１０８…配線、１０９
…集積回路素子、１１０…樹脂、１１１…受動部品、１
１２…封止樹脂、１１３…キャップ、１１４…凹部、１
１５…ボンディングワイヤ、２０１…放熱フランジ、２
０２…ガラス−セラミックス基板、２０３…キャップ、
２０４…リード、２０５…面付用フィン、２０６…高周
波パワーモジュール1 ... Substrate (multilayer substrate), 100 ... Semiconductor module, 1
01 ... MOSFET, 102 ... Recess, 103 ... Circuit board, 104 ... Bump, 105 ... Heat dissipation wiring board, 106 ... S
n-based brazing material, 107 ... transmission wiring, 108 ... wiring, 109
... integrated circuit element, 110 ... resin, 111 ... passive component, 1
12 ... Sealing resin, 113 ... Cap, 114 ... Recess, 1
15 ... Bonding wire, 201 ... Heat dissipation flange, 2
02 ... glass-ceramic substrate, 203 ... cap,
204 ... Leads, 205 ... Surface mounting fins, 206 ... High frequency power module

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 多層配線基板の一方の面側に凹部を設け
るとともに該凹部の底面にバンプを形成し、該バンプを
介して半導体素子の一方面側の端子と接続する多層配線
基板と、 放熱性配線板を備え、該放熱性配線板をＳｎ系のろう材
を介して前記半導体素子の他方の面側の端子と接続して
なる回路基板とからなり、 前記凹部底面に形成したバンプと前記半導体素子の一方
の面側の端子とは固相接合してなることを特徴とする半
導体モジュール。1. A multilayer wiring board having a concave portion on one surface side of a multilayer wiring board, a bump formed on the bottom surface of the concave portion, and connecting to a terminal on one surface side of a semiconductor element through the bump, A circuit board having a heat-dissipating wiring board and connecting the heat-dissipating wiring board to a terminal on the other surface side of the semiconductor element via a Sn-based brazing material, and the bumps formed on the bottom surface of the recess and A semiconductor module characterized by being solid-phase bonded to a terminal on one surface side of a semiconductor element. 【請求項２】 多層配線基板の一方の面側に凹部を設け
るとともに該凹部の底面にバンプを形成し、該バンプを
介して半導体素子の一方面側の端子と接続する多層配線
基板と、 放熱性配線板を備え、該放熱性配線板をＳｎ系のろう材
を介して前記半導体素子の他方の面側の端子と接続して
なる回路基板とからなり、 前記バンプは、ＡｌあるいはＡｌ合金からなり、且つ前
記多層配線基板は少なくとも受動部品を含む回路部品を
備えることを特徴とする半導体モジュール。2. A multilayer wiring board, wherein a concave portion is provided on one surface side of a multilayer wiring board, bumps are formed on the bottom surface of the concave portion, and the bumps are connected to terminals on one surface side of a semiconductor element via the bumps. A circuit board having a heat-dissipating wiring board connected to a terminal on the other surface side of the semiconductor element through a Sn-based brazing material, and the bumps are made of Al or an Al alloy. In addition, the multi-layer wiring board includes a circuit component including at least a passive component. 【請求項３】 請求項１ないし請求項２の何れか１の記
載において、 前記回路部品は、前記多層配線基板の前記回路基板と対
向しない面に配置するとともに樹脂で包囲したことを特
徴とする半導体モジュール。3. The circuit component according to claim 1, wherein the circuit component is arranged on a surface of the multilayer wiring board that does not face the circuit board and is surrounded by a resin. Semiconductor module. 【請求項４】 請求項３の記載において、多層配線基板
の前記回路基板と対向しない面に配置する回路部品は金
属製の蓋で被覆したことを特徴とする半導体モジュー
ル。4. The semiconductor module according to claim 3, wherein the circuit component arranged on the surface of the multilayer wiring board that does not face the circuit board is covered with a metal lid. 【請求項５】 請求項１ないし請求項３の何れか１の記
載において、 前記多層配線基板の前記回路基板と対向しない面には凹
部を設け、該凹部に前記回路部品を装填したことを特徴
とする半導体モジュール。5. The method according to claim 1, wherein a recess is provided in a surface of the multilayer wiring board that does not face the circuit board, and the circuit component is loaded in the recess. And semiconductor module. 【請求項６】 半導体モジュールであって、受動素子を
少なくとも一つ以上含む回路を内部に形成した多層配線
基板の少なくとも一方の面に凹部を設け、前記多層基板
を搭載する回路基板と対向する面側に形成した前記凹部
の底面に形成した配線と半導体素子の主面がAl、あるい
はAl合金で構成されたバンプを介して電気的に接続さ
れ、かつ前記半導体素子の他方の面、及び、前記多層基
板に設けた、前記配線基板と電気的導通を取るための配
線が、前記回路基板上に形成した金属配線上にSnと、A
g、Au、Al、Cu、Ni、Ge、Ga、In、P、Bi、Znの群から選
択された少なくとも１元素、及び不可避的な不純物を含
む1種類のろう材を介して接合されている構造の半導体
モジュール。6. A semiconductor module, wherein a concave portion is provided on at least one surface of a multilayer wiring board in which a circuit including at least one passive element is formed, and a surface facing a circuit board on which the multilayer board is mounted. The wiring formed on the bottom surface of the concave portion formed on the side and the main surface of the semiconductor element are electrically connected via a bump formed of Al, or an Al alloy, and the other surface of the semiconductor element, and Wiring for electrical conduction with the wiring board provided on the multi-layer substrate is Sn and A on the metal wiring formed on the circuit board.
Bonded through at least one element selected from the group consisting of g, Au, Al, Cu, Ni, Ge, Ga, In, P, Bi and Zn, and a brazing filler metal containing inevitable impurities. Structure semiconductor module. 【請求項７】 半導体モジュールであって、受動素子を
少なくとも１つ以上含む回路を内部に形成した多層基板
の少なくとも一方の面に凹部を設け、かつ前記多層基板
の前記多層基板を搭載する回路基板とは対向しない側の
面に部品が搭載され、かつ前記多層基板の前記回路基板
とは対向しない側の面に搭載された部品を樹脂で包埋
し、かつ前記回路基板と対向する側に形成した凹部の底
面に形成した配線と半導体素子の主面がAl、あるいはAl
合金で構成された突起物を介して電気的に接続され、か
つ前記半導体素子の他方の面、及び、前記多層基板に設
けた、前記回路基板と電気的導通を取るための配線が、
前記回路基板上に形成した金属配線上にSnと、Ag、Au、
Al、Cu、Ni、Ge、Ga、In、P、Bi、Znの群から選択され
た少なくとも１元素、及び不可避的な不純物を含む１種
類のろう材を介して接合されている構造の半導体モジュ
ール。7. A semiconductor module, which is a circuit board in which a concave portion is provided on at least one surface of a multilayer substrate in which a circuit including at least one passive element is formed, and the multilayer substrate of the multilayer substrate is mounted. Parts are mounted on the surface not facing the circuit board, and the parts mounted on the surface not facing the circuit board of the multilayer board are embedded in resin and formed on the side facing the circuit board. The wiring formed on the bottom of the recess and the main surface of the semiconductor element are Al or Al
Electrically connected through a protrusion made of an alloy, and the other surface of the semiconductor element, and the wiring provided on the multi-layer substrate for electrical conduction with the circuit board,
Sn on the metal wiring formed on the circuit board, Ag, Au,
A semiconductor module having a structure in which at least one element selected from the group of Al, Cu, Ni, Ge, Ga, In, P, Bi, and Zn and a kind of brazing filler metal containing unavoidable impurities are bonded together. . 【請求項８】 半導体モジュールであって、受動素子を
少なくとも１つ以上含む回路を内部に形成した多層基板
の少なくとも一方の面に凹部を設け、かつ前記多層基板
の前記多層基板を搭載する回路基板とは対向しない側の
面に部品が搭載され、かつ前記多層基板の前記回路基板
とは対向しない側の面に搭載された部品を樹脂で包埋
し、かつ前記多層基板の前記回路基板とは対向しない側
に金属製の蓋が装備され、かつ前記回路基板と対向する
側に形成した前記多層基板の凹部の底面に形成した配線
と半導体素子の主面がAl、あるいはAl合金で構成された
突起物を介して電気的に接続され、かつ前記半導体素子
の他方の面、及び、前記多層基板に設けた、前記回路基
板と電気的導通を取るための配線が、前記回路基板上に
形成した金属配線上にSnと、Ag、Au、Al、Cu、Ni、Ge、
Ga、In、P、Bi、Znの群から選択された少なくとも１元
素、及び不可避的な不純物を含む1種類のろう材を介し
て接合されている構造の半導体モジュール。8. A semiconductor module, which is a circuit board in which a concave portion is provided on at least one surface of a multilayer substrate in which a circuit including at least one passive element is formed, and the multilayer substrate of the multilayer substrate is mounted. Parts are mounted on the surface not facing the circuit board, and the parts mounted on the surface not facing the circuit board of the multilayer board are embedded with resin, and the circuit board of the multilayer board is A metal lid is provided on the non-opposing side, and the wiring formed on the bottom surface of the recess of the multilayer substrate formed on the side facing the circuit board and the main surface of the semiconductor element are made of Al or an Al alloy. Wirings electrically connected to each other through the protrusions and provided on the other surface of the semiconductor element and the multilayer board for establishing electrical continuity with the circuit board are formed on the circuit board. Sn on metal wiring And Ag, Au, Al, Cu, Ni, Ge,
A semiconductor module having a structure in which at least one element selected from the group of Ga, In, P, Bi, and Zn and one kind of brazing filler metal containing unavoidable impurities are bonded together. 【請求項９】 半導体モジュールであって、受動素子を
少なくとも１つ以上含む回路を内部に形成した多層基板
の少なくとも一方の面に凹部を設け、かつ前記多層基板
の前記多層基板を搭載する回路基板とは対向しない側の
面に部品が搭載され、かつ前記回路基板と面する側に形
成した前記多層基板の凹部の底面に形成した配線と半導
体素子の主面がAl、あるいはAl合金で構成された突起物
を介して電気的に接続され、かつ前記半導体素子の他方
の面、及び、前記多層基板に設けた、前記回路基板と電
気的導通を取るための配線が、前記回路基板上に形成し
た金属配線上にSnと、Ag、Au、Al、Cu、Ni、Ge、Ga、I
n、P、Bi、Znの群から選択された少なくとも１元素、及
び不可避的な不純物を含む1種類のろう材を介して接合
されている構造の半導体モジュール。9. A semiconductor module, which is a circuit board in which a concave portion is provided on at least one surface of a multi-layer substrate in which a circuit including at least one passive element is formed, and the multi-layer substrate is mounted. The component is mounted on the surface of the side opposite to and the main surface of the wiring and the semiconductor element formed on the bottom surface of the recess of the multilayer substrate formed on the side facing the circuit board is made of Al, or an Al alloy. Formed on the circuit board, the wiring being electrically connected via the protrusions and being provided on the other surface of the semiconductor element and on the multilayer board for electrical connection with the circuit board. Sn, Ag, Au, Al, Cu, Ni, Ge, Ga, I on the metal wiring
A semiconductor module having a structure in which at least one element selected from the group of n, P, Bi, and Zn and one kind of brazing material containing unavoidable impurities are bonded together. 【請求項１０】 多層配線基板の一方の面側に凹部を設
ける工程と、 該凹部の底面にバンプを形成し、該バンプを介して半導
体素子の一方面側の端子を前記多層配線基板に超音波を
併用したフリップチップ接続法により接続する工程と、 放熱性配線板を備えた回路基板の前記放熱性配線板上に
Ｓｎ系のろう材をスクリーン印刷する工程と、 前記ろう材をスクリーン印刷した回路基板上に前記半導
体素子を搭載した多層配線基板を載置し、リフロー炉を
通過させる工程を含むことを特徴とする半導体モジュー
ルの製造方法。10. A step of providing a concave portion on one surface side of a multilayer wiring board, a bump is formed on a bottom surface of the concave portion, and a terminal on one surface side of a semiconductor element is superposed on the multilayer wiring board via the bump. The step of connecting by a flip-chip connection method that also uses sound waves, the step of screen-printing an Sn-based brazing material on the heat-dissipating wiring board of the circuit board having the heat-dissipating wiring board, and the screen-printing of the brazing material A method of manufacturing a semiconductor module, comprising: mounting a multilayer wiring board on which a semiconductor element is mounted on a circuit board and passing through a reflow furnace. 【請求項１１】 多層配線基板の一方の面及び他方の側
に凹部を設ける工程と、 一方の凹部の底面にバンプを形成し、該バンプを介して
半導体素子の一方面側の端子を前記多層配線基板に超音
波を併用したフリップチップ接続法により接続する工程
と、 他方の凹部の底面にペーストろう材を介して回路素子を
配置し、該回路素子と前記多層配線基板をワイヤボンデ
ィング法により接続する工程と、 前記回路素子上に所定の型を用いて樹脂を注入し、固化
させる工程と、 放熱性配線板を備えた回路基板の前記放熱性配線板上に
Ｓｎ系のろう材をスクリーン印刷する工程と、 前記ろう材をスクリーン印刷した回路基板上に前記半導
体素子を搭載した多層配線基板を載置し、リフロー炉を
通過させる工程を含むことを特徴とする半導体モジュー
ルの製造方法。11. A step of forming a concave portion on one surface and the other side of a multilayer wiring board, and forming a bump on the bottom surface of one concave portion, and forming a terminal on one surface side of the semiconductor element through the bump, The step of connecting to the wiring board by the flip-chip connection method that also uses ultrasonic waves, and arranging the circuit element on the bottom surface of the other recess via the paste brazing material and connecting the circuit element and the multilayer wiring board by the wire bonding method And a step of injecting a resin onto the circuit element using a predetermined mold to solidify the resin, and a screen printing of a Sn-based brazing material on the heat radiation wiring board of the circuit board having the heat radiation wiring board. And a step of placing a multilayer wiring board on which the semiconductor element is mounted on a circuit board on which the brazing material is screen-printed and passing through a reflow furnace. Manufacturing method.
JP2002025752A 2002-02-01 2002-02-01 Semiconductor module and manufacturing method therefor Pending JP2003229521A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258430A (en) * 2006-03-23 2007-10-04 Fujitsu Ltd Semiconductor device
WO2009066504A1 (en) * 2007-11-20 2009-05-28 Murata Manufacturing Co., Ltd. Module with embedded components
JP2015090924A (en) * 2013-11-06 2015-05-11 株式会社豊田自動織機 Semiconductor device
JP2018200990A (en) * 2017-05-29 2018-12-20 京セラ株式会社 Electronic apparatus
CN112202318A (en) * 2019-07-08 2021-01-08 夏普株式会社 Power module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258430A (en) * 2006-03-23 2007-10-04 Fujitsu Ltd Semiconductor device
WO2009066504A1 (en) * 2007-11-20 2009-05-28 Murata Manufacturing Co., Ltd. Module with embedded components
US8139368B2 (en) 2007-11-20 2012-03-20 Murata Manufacturing Co., Ltd. Component-containing module
JP2015090924A (en) * 2013-11-06 2015-05-11 株式会社豊田自動織機 Semiconductor device
JP2018200990A (en) * 2017-05-29 2018-12-20 京セラ株式会社 Electronic apparatus
CN112202318A (en) * 2019-07-08 2021-01-08 夏普株式会社 Power module

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