JPWO2006001087A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JPWO2006001087A1
JPWO2006001087A1 JP2006527634A JP2006527634A JPWO2006001087A1 JP WO2006001087 A1 JPWO2006001087 A1 JP WO2006001087A1 JP 2006527634 A JP2006527634 A JP 2006527634A JP 2006527634 A JP2006527634 A JP 2006527634A JP WO2006001087 A1 JPWO2006001087 A1 JP WO2006001087A1
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semiconductor device
wiring board
semiconductor
semiconductor chip
chip
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浩一 中嶋
浩一 中嶋
小西　聡
聡 小西
雅志 岡野
雅志 岡野
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10371—Shields or metal cases
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

半導体装置（１）は、配線基板（２）と、配線基板（２）上にフリップチップ実装された半導体チップ（３）と、配線基板（２）上に搭載された受動部品（４）と、半導体チップ（３）を覆うように配線基板（２）に搭載され、半導体チップ（３）の裏面（３ｂ）に接続された放熱用部材（５）とを有している。受動部品（４）は、半導体チップ（３）よりも高さが高い受動部品（４ａ）を含んでおり、半導体チップ（３）よりも高さが高い受動部品（４ａ）は、放熱用部材（５）の外部の配線基板（２）の上面（２ａ）に搭載され、放熱用部材（５）の内部の配線基板（２）の上面（２ａ）には搭載されない。The semiconductor device (1) includes a wiring board (2), a semiconductor chip (3) flip-chip mounted on the wiring board (2), a passive component (4) mounted on the wiring board (2), A heat dissipation member (5) is mounted on the wiring board (2) so as to cover the semiconductor chip (3) and connected to the back surface (3b) of the semiconductor chip (3). The passive component (4) includes a passive component (4a) whose height is higher than that of the semiconductor chip (3), and the passive component (4a) whose height is higher than that of the semiconductor chip (3) is a member for heat dissipation ( 5) mounted on the upper surface (2a) of the external wiring board (2) and not mounted on the upper surface (2a) of the wiring board (2) inside the heat dissipation member (5).

Description

本発明は、半導体装置に関し、特に、高周波電力増幅装置に適用して有効な技術に関するものである。  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a high-frequency power amplifier.

ＲＦパワーモジュールのような半導体装置は、配線基板上に半導体チップや受動部品のような種々の電子部品を搭載することによって形成される。近年、このような半導体装置に対する小型化や薄型化の要求が高まってきている。
また、特開２００２−２６１５８１号公報には、多層基板上に表面弾性波素子とその他の表面実装素子とが搭載され、表面弾性波素子が多層基板の金属膜を施した電極上に直接フリップチップ搭載され、かつ複数の表面弾性波素子が一つの封止部材により一括して覆われ気密封止されている構成の高周波モジュール部品に関する技術が記載されている。A semiconductor device such as an RF power module is formed by mounting various electronic components such as semiconductor chips and passive components on a wiring board. In recent years, there has been an increasing demand for such semiconductor devices to be reduced in size and thickness.
Japanese Patent Laid-Open No. 2002-261581 discloses that a surface acoustic wave element and other surface mount elements are mounted on a multilayer substrate, and the surface acoustic wave element is flip-chip directly on the electrode on which the metal film of the multilayer substrate is applied. A technique relating to a high-frequency module component that is mounted and has a configuration in which a plurality of surface acoustic wave elements are collectively covered with a single sealing member and hermetically sealed is described.

本発明者の検討によれば、次のことが新たに見出された。
ＲＦパワーモジュールのような半導体装置において、配線基板に半導体チップをフリップチップ実装した場合、ワイヤボンディング方式に比べて、ＲＦパワーモジュール全体の薄型化や小型化には有利であるが、半導体チップで発生した熱の放熱経路がバンプ電極を介して配線基板に放熱する経路だけだと、半導体チップの発熱を充分に放熱することができず、ＲＦパワーモジュールの性能が低下する可能性がある。また、半導体チップの発熱がバンプ電極を介して配線基板へ放熱される際に、バンプ電極に熱が集中すると、バンプ電極が熱劣化する可能性もある。
このため、配線基板上に金属キャップを被せ、この金属キャップを半導体チップの裏面に接続して、半導体チップの発熱を金属キャップを介して配線基板へ放熱させることで、放熱特性を向上させることが考えられる。
しかしながら、配線基板には、半導体チップ以外にも受動部品が搭載されており、配線基板上に金属キャップを被せただけでは、ＲＦパワーモジュール全体の厚みが厚くなってしまう。ＲＦパワーモジュール全体の薄型化を実現するためには、配線基板上に搭載する各電子部品の外形寸法を総合的に勘案した対策が必要となる。
本発明の目的は、半導体装置の薄型化を可能とする技術を提供することにある。
本発明の他の目的は、半導体装置の放熱特性を向上できる技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
本発明は、半導体チップと受動部品とを配線基板上に搭載した半導体装置において、半導体チップをフリップチップ実装し、半導体チップを覆うような放熱用部材を配線基板に搭載して半導体チップの裏面に接続させ、半導体チップよりも高さが高い受動部品は放熱用部材の外部の配線基板上に搭載して放熱用部材の内部の配線基板上には搭載しないものである。
また、本発明は、半導体増幅素子チップと他の電子部品とを配線基板上に搭載した半導体装置において、半導体増幅素子チップをフリップチップ実装し、半導体増幅素子チップを覆うような放熱用部材を配線基板に搭載して半導体増幅素子チップの裏面に接続させ、半導体増幅素子チップよりも高さが高い電子部品は放熱用部材の外部の配線基板上に搭載して放熱用部材の内部の配線基板上には搭載しないものである。According to the study by the present inventor, the following has been newly found.
In a semiconductor device such as an RF power module, when a semiconductor chip is flip-chip mounted on a wiring board, it is advantageous for making the entire RF power module thinner and smaller than the wire bonding method. If the only heat dissipation path is the path that dissipates heat to the wiring board via the bump electrodes, the heat generated by the semiconductor chip cannot be sufficiently dissipated, and the performance of the RF power module may be degraded. In addition, when heat generated in the semiconductor chip is radiated to the wiring substrate through the bump electrode, if the heat concentrates on the bump electrode, the bump electrode may be thermally deteriorated.
For this reason, a metal cap is put on the wiring board, this metal cap is connected to the back surface of the semiconductor chip, and the heat generation of the semiconductor chip is radiated to the wiring board through the metal cap, thereby improving the heat dissipation characteristics. Conceivable.
However, passive components other than the semiconductor chip are mounted on the wiring board, and the thickness of the entire RF power module increases only by covering the wiring board with a metal cap. In order to reduce the thickness of the entire RF power module, it is necessary to take a measure that comprehensively considers the external dimensions of each electronic component mounted on the wiring board.
An object of the present invention is to provide a technique that enables a semiconductor device to be thinned.
Another object of the present invention is to provide a technique capable of improving the heat dissipation characteristics of a semiconductor device.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
The present invention relates to a semiconductor device in which a semiconductor chip and a passive component are mounted on a wiring board. The semiconductor chip is flip-chip mounted, and a heat dissipation member that covers the semiconductor chip is mounted on the wiring board. A passive component having a height higher than that of the semiconductor chip is mounted on the wiring board outside the heat radiating member and not mounted on the wiring board inside the heat radiating member.
The present invention also relates to a semiconductor device in which a semiconductor amplification element chip and other electronic components are mounted on a wiring board, wherein the semiconductor amplification element chip is flip-chip mounted, and a heat radiating member that covers the semiconductor amplification element chip is wired. Mounted on a substrate and connected to the back surface of the semiconductor amplifying element chip, and an electronic component having a height higher than that of the semiconductor amplifying element chip is mounted on the wiring board outside the heat radiating member and placed on the wiring board inside the heat radiating member. Is not installed.

図１は、本発明の一実施の形態である半導体装置の概念的な構造を示す上面図である。
図２は、図１の半導体装置の断面図である。
図３は、図１において放熱用部材を透視した状態を示す上面図である。
図４は、図１の半導体装置で用いられる放熱用部材の上面図である。
図５は、図４の放熱用部材の断面図である。
図６は、図４の放熱用部材の断面図である。
図７は、半導体チップの回路構成の一例を示す回路ブロック図である。
図８は、図１の半導体装置が実装基板に実装された状態を概念的に示す断面図である。
図９は、本発明の一実施の形態である半導体装置の製造工程中の断面図である。
図１０は、図９に続く半導体装置の製造工程中における断面図である。
図１１は、図１０に続く半導体装置の製造工程中における断面図である。
図１２は、本発明の他の実施の形態である半導体装置が実装基板に実装された状態を概念的に示す断面図である。
図１３は、本発明の他の実施の形態である半導体装置の概念的な構造を示す上面図である。
図１４は、図１３の半導体装置の断面図である。
図１５は、図１３において放熱用部材を透視した状態を示す上面図である。
図１６は、本発明の他の実施の形態である半導体装置の概念的な構造を示す上面図である。
図１７は、図１６の半導体装置の断面図である。
図１８は、図１６の半導体装置が実装基板に実装された状態を概念的に示す断面図である。FIG. 1 is a top view showing a conceptual structure of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the semiconductor device of FIG.
FIG. 3 is a top view showing a state where the heat radiation member is seen through in FIG. 1.
FIG. 4 is a top view of a heat dissipation member used in the semiconductor device of FIG.
FIG. 5 is a cross-sectional view of the heat dissipation member of FIG.
6 is a cross-sectional view of the heat dissipation member of FIG.
FIG. 7 is a circuit block diagram showing an example of the circuit configuration of the semiconductor chip.
FIG. 8 is a cross-sectional view conceptually showing a state where the semiconductor device of FIG. 1 is mounted on a mounting substrate.
FIG. 9 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention during the manufacturing process.
FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
FIG. 12 is a cross-sectional view conceptually showing a state in which a semiconductor device according to another embodiment of the present invention is mounted on a mounting board.
FIG. 13 is a top view showing a conceptual structure of a semiconductor device according to another embodiment of the present invention.
14 is a cross-sectional view of the semiconductor device of FIG.
FIG. 15 is a top view showing a state where the heat radiation member is seen through in FIG. 13.
FIG. 16 is a top view showing a conceptual structure of a semiconductor device according to another embodiment of the present invention.
17 is a cross-sectional view of the semiconductor device of FIG.
18 is a cross-sectional view conceptually showing a state in which the semiconductor device of FIG. 16 is mounted on a mounting board.

以下の実施の形態においては便宜上その必要があるときは、複数のセクションに分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲についても同様である。
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。
また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。また、平面図などであっても図面を見易くするためにハッチングを付す場合もある。
（実施の形態１）
本実施の形態の半導体装置（電子装置）を図面を参照して説明する。本実施の形態では、半導体装置（電子装置）として、例えば高周波パワーアンプモジュール（高周波電力増幅器モジュール、ＲＦ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ）パワーモジュール、高周波電力増幅装置、電力増幅装置）などである高周波モジュールに適用した場合について説明する。
図１は、本実施の形態の半導体装置（ＲＦモジュール）１の概念的な構造を示す上面図（平面図）であり、図２は半導体装置１の概念的な断面図（側面断面図）である。図３は、図１において、放熱用部材５を透視（省略）した状態を示す上面図（平面図）である。図４は、半導体装置１で用いられる放熱用部材５の上面図（平面図）であり、図５および図６は、放熱用部材５の断面図である。図２は、半導体装置１の各構成部品の高さ位置関係などを明確にするための概念的な断面構造が示されており、例えば放熱用部材５を省略しなかったときの図３のＡ−Ａ線の断面にほぼ対応するものである。また、図５は図４のＢ−Ｂ線の断面に対応し、図６は図４のＣ−Ｃ線の断面に対応する。
図１〜図３に示される本実施の形態の半導体装置（ここではＲＦパワーモジュールまたは高周波電力増幅装置）１は、配線基板（多層基板、多層配線基板、モジュール基板）２と、配線基板２に搭載（実装）された能動素子からなる半導体チップ（半導体素子、能動素子）３と、配線基板２に搭載（実装）された受動素子からなる受動部品（受動素子、チップ部品）４と、半導体チップ３を覆うように配線基板２に搭載（接合）された放熱用部材（金属キャップ、金属カバー、放熱用キャップ、放熱用カバー、放熱板）５とを有している。半導体チップ３および受動部品４は、配線基板２の導体層（電極、配線、伝送線路）に電気的に接続されている。また、半導体装置１は、例えば図示しない外部回路基板またはマザーボードなどに実装することもできる。
配線基板２は、例えば、複数の絶縁体層（誘電体層）１１と、複数の導体層（配線層）とを積層して一体化した多層基板（多層配線基板）を用いることができる。図２では、４つの絶縁体層１１が積層されて配線基板２が形成されているが、積層される絶縁体層１１の数はこれに限定されるものではなく種々変更可能である。配線基板２の絶縁体層１１を形成する材料としては、例えばアルミナ（酸化アルミニウム、Ａｌ２Ｏ３）などのようなセラミック材料を用いることができる。この場合、配線基板２はセラミック多層基板である。絶縁体層１１を樹脂材料よりも熱伝導率が高いセラミック材料により形成して配線基板２をセラミック基板（セラミック多層基板）とすることで、半導体装置１の放熱特性をより向上させることができる。配線基板２の絶縁体層１１の材料は、セラミック材料に限定されるものではなく種々変更可能であり、例えばガラスエポキシ樹脂などを用いることもできる。
配線基板２の上面（表面、主面、第１の主面）２ａと下面（裏面、主面）２ｂと各絶縁体層１１間とには、配線形成用の導体層（配線層、配線パターン、導体パターン）が形成されている。配線基板２の最上層の導体層によって、配線基板２の上面２ａに導電体からなる基板側端子（端子、電極）１２ａが形成され、配線基板２の最下層の導体層によって、配線基板２の下面２ｂに導電体からなる外部接続端子（端子、電極、モジュール電極）１２ｂが形成されている。配線基板２の内部、すなわち絶縁体層１１の間にも導体層（配線層、配線パターン、導体パターン）が形成されているが、図２では簡略化のために図示を省略している。配線基板２の導体層を形成する材料としては、例えば銅または銅合金などの導電性および熱伝導性の良い材料などを用いることができる。例えば、配線基板２の上面２ａおよび下面２ｂの導体層（例えば基板側端子１２ａおよび外部接続端子１２ｂ）は、銅（Ｃｕ）とタングステン（Ｗ）との合金の表面にニッケル（Ｎｉ）メッキおよび金（Ａｕ）メッキを順に施したものとすることができる。この金メッキは、導体層の酸化や侵食を防ぐ機能を有している。また、配線基板２の内部（内層）の導体層（絶縁体層１１間の導体層）は、例えば銅（Ｃｕ）とタングステン（Ｗ）との合金により形成することができる。また、配線基板２の導体層により形成される配線パターンのうち、基準電位供給用の配線パターン（例えば配線基板２の下面２ｂの基準電位供給用端子１２ｃなど）は、絶縁体層１１の配線形成面の大半の領域を覆うようなベタパターンで形成し、伝送線路用の配線パターンは帯状のパターンで形成することができる。
配線基板２を構成する各導体層（配線層）は、必要に応じて絶縁体層１１に形成されたビアホール（スルーホール）１３内の導体または導体膜を通じて電気的に接続されている。ビアホール１３内の導体膜は、例えば銅（Ｃｕ）とタングステン（Ｗ）との合金からなる。従って、配線基板２の上面２ａの基板側端子１２ａは、必要に応じて配線基板２の上面２ａおよび／または内部の配線層（絶縁体層１１間の配線層）やビアホール１３内の導体膜などを介して、配線基板２の下面２ｂの外部接続端子１２ｂに電気的に接続されている。なお、ビアホール１３のうち、半導体チップ３の下方に設けられたビアホール１３ａは、半導体素子３で生じた熱を配線基板２の下面２ｂ側に伝導させるためのサーマルビアとして機能することができる。
配線基板２の上面２ａには、複数の受動部品４が搭載されている。受動部品４は、抵抗素子（例えばチップ抵抗）、容量素子（例えばチップコンデンサ）またはインダクタ素子（例えばチップインダクタ）などの受動素子からなる。受動部品４としては、チップ部品などを用いることができる。また、受動部品４として、集積受動部品（ＩＰＣ：Ｉｎｔｅｇｒａｔｅｄ Ｐａｓｓｉｖｅ Ｃｏｍｐｏｎｅｎｔ，ＩＰＤ：Ｉｎｔｅｇｒａｔｅｄ Ｐａｓｓｉｖｅ Ｄｅｖｉｃｅ）を用いることもできる。受動部品４の電極１４は、半田などの導電性の接合材（接着材）１５により、配線基板２の上面２ａの基板側端子１２ａに接合（実装、接続）され、電気的に接続されている。
半導体チップ３は、能動素子からなり、例えば半導体増幅素子チップ（高周波用電力増幅素子チップ）である。例えば、半導体チップ３は、半導体装置１において電力増幅回路を構成する半導体増幅素子である。
半導体チップ３の表層部分または内部には、例えば、ＧａＡｓまたはＩｎＰなどを主成分とするヘテロ接合バイポーラトランジスタ、ＳｉＧｅあるいはＳｉ−ＭＩＳＦＥＴ（Ｍｅｔａｌ Ｉｎｓｕｌａｔｏｒ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）などの電界効果トランジスタ、またはＧａＡｓなどを主成分とするＨＥＭＴ（Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ：高電子移動度トランジスタ）などの半導体素子（半導体増幅素子）が形成されている。半導体チップ３は、例えば、単結晶シリコンなどからなる半導体基板（半導体ウエハ）に種々の半導体素子（半導体増幅素子）または半導体集積回路を形成した後、必要に応じて半導体基板の裏面研削を行ってから、ダイシングなどにより半導体基板を各半導体チップ３に分離したものである。半導体チップ３の表面（半導体素子形成側の主面）３ａには、複数のバンプ電極（突起状電極）１７が形成されている。バンプ電極１７は、例えば半田バンプなどである。バンプ電極１７として金バンプなどを用いることもできる。バンプ電極１７は、半導体チップ３に形成された半導体素子（半導体増幅素子）または半導体集積回路に電気的に接続されている。
図７は、半導体チップ３の回路構成の一例を示す回路ブロック図である。図７には、例えばＧＳＭ９００とＤＣＳ１８００との２つの周波数帯が使用可能（デュアルバンド方式）なＲＦパワーモジュールに使用される増幅回路用の半導体チップ３の回路ブロックが例示されている。図７の回路では、２つの周波数帯域（ＧＳＭとＤＣＳ）を２つの増幅回路に分けて増幅している。各増幅回路は、例えば、３段増幅しており、各段にそれぞれ１つずつのトランジスタ２０ａ（例えばＭＩＳＦＥＴ）が使用されている。また、各段の増幅回路（トランジスタ２０ａ）は制御回路２０ｂによりコントロールされている。また、半導体チップ３は、図７の増幅回路を１チップ内に取り込んでいる。従って、半導体装置１は、このような増幅用の１つの半導体チップ３と、受動部品４（複数）とにより回路構成されている。
半導体チップ３は、配線基板２の上面２ａにフリップチップ接続（フリップチップ実装）されている。すなわち、半導体チップ３は、その裏面（半導体素子形成側の主面とは逆側の主面）３ｂが上方を向き、その表面（半導体素子形成側の主面）３ａが配線基板２の上面２ａに対向する向きで、配線基板２の上面２ａに搭載（実装）されている。従って、半導体チップ３は配線基板２の上面２ａにフェースダウンボンディングされている。半導体チップ３の表面３ａのバンプ電極１７は、配線基板２の上面２ａの基板側端子１２ａに接合（実装、接続）され、電気的に接続されている。このため、半導体チップ３に形成された半導体素子（半導体増幅素子）または半導体集積回路は、バンプ電極１７を介して配線基板２の上面２ａの基板側端子１２ａに電気的に接続される。また、半導体チップ３と配線基板２との熱膨張率の差によるバンプ電極１７への負担を緩衝するために、半導体チップ３と配線基板２の上面２ａとの間にアンダーフィル樹脂（図示せず）を充填することも可能である。
本実施の形態では、上記のように、配線基板２に半導体チップ３をフェースダウンボンディングしてフリップチップ実装している。このため、本実施の形態とは異なり、配線基板２に半導体チップ３をフェースアップボンディングしてボンディングワイヤによって配線基板２の基板側端子１２ａと半導体チップ３のボンディングパッドとを接続する場合に比べて、ボンディングワイヤのループ高さの分だけ、半導体装置１の厚み（高さ）を薄く（低く）することができる。従って、半導体装置の薄型化に有利となる。
配線基板２の上面２ａには、半導体チップ３を覆うように、放熱用部材（金属キャップ、金属カバー、放熱用キャップ、放熱用カバー、放熱板）５が搭載（接合）されており、放熱用部材５の内面に半導体チップ３の裏面３ｂが接続（接合）されている。放熱用部材５は、熱伝導性の良い（高い）材料からなり、例えば銅（Ｃｕ）などの金属材料からなる。放熱用部材５は、例えば金属キャップであり、金属板を加工することなどにより形成することができる。また、放熱用部材５は、成形性の良い材料により形成されていれば、より好ましい。放熱用部材５を例えば銅（Ｃｕ）または銅を主成分とする合金により形成すれば、放熱用部材５の熱伝導性および成形性を高めることができ、更に放熱用部材５の部材コストも低減できる。
放熱用部材５は、半導体チップ３の周囲を囲む側壁部（脚部）５ａと、側壁部５ａの上部を連結し、半導体チップ３の上部を覆う天井部（上壁部、天板部、屋根部）５ｂとを有している。放熱用部材５の天井部５ｂの内面（下面、内壁）５ｃは、半導体チップ３の裏面３ｂに、接合材（接着材）１８によって接続（接合、接着）されている。半導体チップ３と放熱用部材５とを接合する接合材１８は、熱伝導性の良い（高い）接合材からなることが好ましく、例えば銀ペーストまたは半田などからなる。
放熱用部材５の（側壁部５ａの）少なくとも一部（ここでは接合部５ｅ）は、配線基板２の上面２ａの基板側端子１２ａに、接合材（接着材）１９によって接合（接続、接着）されている。放熱用部材５と配線基板２の上面２ａの基板側端子１２ａとを接合する接合材１９は、熱伝導性の良い（高い）接合材からなることが好ましく、例えば半田または銀ペーストなどからなる。放熱用部材５が接合材１９を介して接合された基板側端子１２ａは、配線基板２の上面２ａまたは内部の配線層（絶縁体層１１間の配線層）やビアホール１３内の導体膜などを介して、配線基板２の下面２ｂの基準電位供給用端子１２ｃに電気的に接続されている。
また、図１〜図６に示されるように、放熱用部材５の側壁部５ａの最下部に接続してそこから配線基板２の上面２ａに略平行な方向に延在（突出）する接合部５ｅを、放熱用部材５の側壁部５ａの下部の少なくとも一部に設け、この放熱用部材５の接合部５ｅを接合材１９を介して配線基板２の上面２ａの基板側端子１２ａに接合すれば、放熱用部材５と配線基板２の上面２ａの基板側端子１２ａとの接合面積を増大し、接合強度を高めることが可能になる。なお、放熱用部材５の側壁部５ａ、天井部５ｂおよび接合部５ｅは、一体的に形成された一部材とすることができ、例えば金属板などを加工することにより放熱用部材５を形成することができる。また、放熱用部材５（の接合部５ｅ）を配線基板２の上面２ａに接合する構造とすることで、配線基板２への放熱用部材５の搭載（接合）工程が容易となり、半導体装置１の製造工程が複雑化せず、半導体装置１の製造コストを低減できる。
また、放熱用部材５の天井部５ａの上面（外面）５ｄに製品番号などのマーキング２１を行うこともできる。マーキング２１は、配線基板２に放熱用部材５を搭載した後に、半導体装置１の製品番号（記号や符号などを含むこともできる）やロット番号（記号や符号などを含むこともできる）などを放熱用部材５の天井部５ａの上面（外面）５ｄに印刷することなどにより形成できる。本実施の形態では、後述するように、半導体チップ３と半導体チップ３よりも低い受動部品４ｂとを覆うように、放熱用部材５を配線基板２に搭載しているので、放熱用部材５の天井部５ｂの上面５ｄの面積を比較的大きくすることができ、放熱用部材５の上面５ｄをマーキングエリアとして用いることが容易になる。また、放熱用部材５の上面５ｄは、半導体装置１を吸着して移動させるために際の吸着エリアとして用いることもできる。なお、マーキング２１は、不要であれば省略することもできる。
半導体チップ３で発生した熱は、半導体チップ３の表面３ａ側から、バンプ電極１７および基板側端子１２ａを介して配線基板２に伝導されるとともに、更に、半導体チップ３の裏面３ｂ側から、接合材１８、放熱用部材５、接合材１９および基板側端子１２ａを介して配線基板２に伝導される。特に、半導体チップ３が半導体増幅素子チップの場合、半導体チップ３の発熱量が多いため、半導体チップ３の放熱特性を高めないと、半導体チップ３およびそれを搭載した半導体装置１の性能が低下してしまう。本実施の形態では、半導体チップ３の放熱経路を、バンプ電極１７を介して配線基板２に放熱する放熱経路だけでなく、放熱用部材５を介して配線基板２に放熱する放熱経路を設けたことにより、半導体チップ３およびそれを搭載した半導体装置１の放熱特性を向上でき、半導体装置１の性能を向上することができる。また、半導体チップ３の発熱を、バンプ１７を介して配線基板２に放熱する経路よりも、放熱用部材５から配線基板２に放熱する経路でより多く放熱することが可能になり、バンプ１７の熱劣化を抑制でき、半導体装置の信頼性を向上することができる。
また、本実施の形態では、半導体チップ３を配線基板２にフリップチップ実装しているので、配線基板２に半導体チップ３をフェースアップボンディングしてワイヤボンディングによって配線基板２の基板側端子１２ａと半導体チップ３のボンディングパッドとを接続する場合に比べて、ボンディングワイヤのループ高さの分だけ、半導体装置１全体の厚み（高さ）Ｔ０を薄く（低く）することができる。従って、半導体装置１の薄型化に有利となる。また、半導体チップ３で発生した熱は、半導体チップ３の表面３ａ側から、バンプ電極１７を介して配線基板２に放熱し、半導体チップ３の裏面３ｂ側から、放熱用部材５を介して配線基板２に放熱することができるので、配線基板２に半導体チップ３をフェースアップボンディングしてワイヤボンディングによって配線基板２の基板側端子１２ａと半導体チップ３のボンディングパッドとを接続した場合と同等かそれ以上の放熱特性を得ることができる。
また、本実施の形態では、半導体チップ３を配線基板２にフリップチップ実装し、半導体チップ３をバンプ電極１７を介して配線基板２の基板側端子１２ａに接続している。このため、ワイヤボンディングによって半導体チップ３と配線基板２とを接続する場合に比べて、半導体チップ３の表面３ａの電極や配線基板２の基板側端子１２ａの面積を縮小することができる。従って、半導体チップ３および配線基板２の面積を小さくすることが可能になり、半導体装置１の小型化に有利となる。
また、本実施の形態では、半導体チップ３の発熱の放熱を補助するために、半導体チップ３の下方にサーマルビアとしてのビアホール１３ａを設けており、このビアホール１３ａにより、半導体装置３およびそれを搭載した半導体装置１の放熱特性をより向上させることができるが、半導体チップ３の発熱は、放熱用部材５を介して配線基板２に放熱することができるので、半導体チップ３の下方に配置されるサーマルビアとしてのビアホール１３ａは、その形成を省略することも可能である。半導体チップ３の下方に配置されるサーマルビアとしてのビアホール１３ａを省略することで、配線基板２の小型化（小面積化）や配線基板２をより複雑な配線構造とすることが可能になる。
上記のように配線基板２の上面２ａには、半導体チップ３以外の電子部品として複数の受動部品４が搭載されているが、本実施の形態では、受動部品４のうち、その高さ（最上部の高さ）ｈ１が半導体チップ３の高さ（最上部の高さ）ｈ０よりも高いような受動部品４ａ（受動部品４ａの高さｈ１＞半導体チップ３の高さｈ０）は、配線基板２の上面２ａのうちの放熱用部材５に覆われていない領域（放熱用部材５の外部の領域）２２ａ上に搭載され、配線基板２の上面２ａのうちの放熱用部材５に覆われた領域（放熱用部材５の内部の領域）２２ｂには搭載されない。すなわち、受動部品４のうちの受動部品４ａの高さｈ１は半導体チップ３の高さｈ０よりも高く（受動部品４ａの高さｈ１＞半導体チップ３の高さｈ０）、配線基板２ａの上面２ａには、このような半導体チップ３よりも高さが高い受動部品４ａを含む受動部品４が搭載されており、半導体チップ３よりも高さが高い受動部品４ａは、放熱用部材５の外部の配線基板２の上面２ａに搭載され、放熱用部材５の内部の配線基板２の上面２ａには搭載されない。
また、本実施の形態では、受動部品４のうち、その高さ（最上部の高さ）ｈ２が半導体チップ３の高さ（最上部の高さ）ｈ０よりも低いような受動部品４ｂ（受動部品４ｂの高さｈ２＜半導体チップ３の高さｈ０）は、配線基板２の上面２ａのうちの放熱用部材５に覆われていない領域（放熱用部材５の外部の領域）２２ａ上と、配線基板２の上面２ａのうちの放熱用部材５に覆われた領域（放熱用部材５の内部の領域）２２ｂ上に搭載されている。すなわち、受動部品４のうちの受動部品４ｂの高さｈ２は半導体チップ３の高さｈ０よりも低く（受動部品４ｂの高さｈ２＜半導体チップ３の高さｈ０）、このような半導体チップ３よりも高さが低い受動部品４ｂは、放熱用部材５の外部の配線基板２の上面２ａ（すなわち領域２２ａ）および放熱用部材５の内部の配線基板２の上面２ａ（すなわち領域２２ｂ）に搭載されている。
従って、本実施の形態では、放熱用部材５は、半導体チップ３と半導体チップ３よりも高さが低い受動部品４ｂとを覆い、かつ半導体チップ３よりも高さが高い受動部品４ａを覆わないように、配線基板２の上面２ａに搭載（接合）されている。
なお、本実施の形態では、半導体チップ３の高さｈ０とは、半導体チップ３の最上部の高さｈ０に対応し、配線基板２の上面２ａに半導体チップ３を搭載（実装）したときの、配線基板２の上面２ａから半導体チップ３の最上部までの高さ（配線基板２の上面２ａに垂直な方向の高さ）ｈ０に対応する。半導体チップ３をフリップチップ実装している場合は、半導体チップ３の裏面３ｂが半導体チップ３の最上部に対応するので、配線基板２の上面２ａから半導体チップ３の裏面３ｂまでの高さ（配線基板２の上面２ａに垂直な方向の高さ）が半導体チップ３の高さｈ０に対応することになる。また、受動部品４（４ａ，４ｂ）の高さｈ１，ｈ２とは、受動部品４（４ａ，４ｂ）の最上部の高さｈ１，ｈ２に対応し、配線基板２の上面２ａに受動部品４（４ａ，４ｂ）を搭載（実装）したときの、配線基板２の上面２ａから受動部品４（４ａ，４ｂ）の最上部までの高さ（配線基板２の上面２ａに垂直な方向の高さ）ｈ１，ｈ２に対応する。受動部品４（４ａ，４ｂ）がチップ部品である場合は、受動部品４（４ａ，４ｂ）の上面１６が受動部品４（４ａ，４ｂ）の最上部に対応するので、配線基板２の上面２ａから受動部品４（４ａ，４ｂ）の上面１６までの高さ（配線基板２の上面２ａに垂直な方向の高さ）が受動部品４（４ａ，４ｂ）の高さｈ１，ｈ２に対応することになる。
放熱用部材５の高さは、放熱用部材５の内部の電子部品（受動部品４および半導体チップ３）のうちの最も高さが高い電子部品（素子）の高さによって規定されてしまう。本実施の形態とは異なり、半導体チップ３とともに半導体チップ３よりも高い受動部品４ａも覆うように、放熱用部材５を配線基板２の上面２ａに搭載（接合）することも考えられるが、この場合、放熱用部材５の高さは、半導体チップ３ではなく、半導体チップ３よりも高い受動部品４ａの高さｈ１によって規定されることになる。半導体チップ３よりも高い受動部品４ａの更に上に放熱用部材５の天井部５ｂが配置されることになるので、半導体装置１全体の厚みが厚くなってしまう。また、短絡防止の観点から、受動部品４の電極１４には、銅などの金属材料からなる放熱用部材５を接触させない方が良いので、半導体チップ３よりも高さが高い受動部品４ａと放熱用部材５との間に隙間を設ける必要があり、半導体装置１全体の厚みが更に厚くなってしまう。また、放熱用部材５を受動部品４ｂには接触させずに半導体チップ３の裏面３ｂに接合させるには、放熱用部材５の内面５ｃに凹凸を設ける必要があり、放熱用部材５の加工が容易ではない。
それに対して、本実施の形態では、半導体チップ３とともに、半導体チップ３よりも高さが低い電子部品（受動部品４ｂ）は覆うが、半導体チップ３よりも高さが高い電子部品（受動部品４ａ）は覆わないように、放熱用部材５を配線基板２の上面２ａに搭載（接合）している。半導体チップ３よりも高さが高い電子部品（受動部品４ａ）は、放熱用部材５の外部の配線基板２の上面２ａに搭載され、放熱用部材５の内部の配線基板２の上面２ａには搭載されない。このため、放熱用部材５の内部の電子部品（ここでは受動部品４ｂおよび半導体チップ３）のうちの最も高さが高い電子部品（素子）は半導体チップ３となるので、放熱用部材５の高さｈ３は、半導体チップ３の高さによって規定されることになる。半導体チップ３よりも高さが高い電子部品（受動部品４ａ）の上に放熱用部材５が配置されるこことはない。このため、半導体装置１全体の厚み（高さ）Ｔ０を薄く（低く）することができる。例えば、半導体装置１全体の厚みＴ０を１ｍｍ以下にすることができる。従って、使用する半導体装置の薄型化が特に要求される電子機器、例えば携帯電話などへの半導体装置１の使用がより容易になる。例えば、本実施の形態の半導体装置１を、携帯電話に搭載される電力増幅装置などに適用すれば、より効果が大きい。
また、本実施の形態では、半導体チップ３よりも高さが高い電子部品（受動部品４ａ）は覆わないように、放熱用部材５を配線基板２の上面２ａに搭載（接合）しているので、放熱用部材５の天井部５ｂが平板状で内面５ｃが平坦であっても、放熱用部材５内にある電子部品（半導体チップ３および受動部品４ｂ）のうちの半導体チップ３以外の電子部品である受動部品４ｂに、銅などの導電体からなる放熱用部材５が接触することはない。このため、半導体チップ３以外の電子部品（受動部品４ｂ）と放熱用部材５との間の短絡を防止することができる。また、放熱用部材５の天井部５ｂの内面５ｃを平坦にでき、放熱用部材５を比較的単純な構造とすることができるので、放熱用部材５の加工が容易である。このため、半導体装置の製造コストを低減できる。また、放熱用部材５の天井部５ｂを平板状にしてその上面５ｄも平坦にできるので、放熱用部材５の上面５ｄへのマーキングが容易となり、また、放熱用部材５の上面５ｄを吸着エリアとして使用するのも容易となる。
また、放熱用部材５の高さ（最上部の高さ）ｈ３を、配線基板２の上面２ａに搭載された受動部品４のうち、高さが最も高い受動部品の（最上部の）高さ（ここでは受動部品４ａの高さｈ１）と同じかそれよりも低く（放熱用部材５の高さｈ３≦受動部品４ａの高さｈ１）すれば、より好ましい。なお、本実施の形態では、放熱用部材５の高さｈ３とは、放熱用部材５の最上部の高さｈ３に対応し、配線基板２に放熱用部材５を搭載（接合）したときの、配線基板２の上面２ａから放熱用部材５の最上部までの高さ（配線基板２の上面２ａに垂直な方向の高さ）ｈ３に対応する。放熱用部材５の天井部５ｂの上面（外面）５ｄが放熱用部材５の最上部に対応するので、配線基板２の上面２ａから放熱用部材５の上面５ｄまでの高さ（配線基板２の上面２ａに垂直な方向の高さ）が放熱用部材５の高さｈ３に対応することになる。
半導体基板（半導体ウエハ）に半導体集積回路を形成した後、半導体基板のダイシングを行う前に半導体基板の裏面研削を行うことで、半導体チップ３の厚みを薄くすることが可能であり、例えば半導体チップ３の厚みを１５０〜３００μｍ程度にすることができ、これによって、配線基板２に半導体チップ３を搭載した際の半導体チップ３の高さｈ０を低くすることができる。半導体チップ３の高さｈ０を低くして、半導体チップ３を覆うように配線基板２に搭載した放熱用部材５の高さｈ３（すなわち放熱用部材５の上面５ｄの高さ）を、配線基板２の上面２ａに搭載された受動部品４のうち、高さが最も高い受動部品４の高さ（ここでは受動部品４ａの高さｈ１）と同じかそれよりも低くする（ｈ３≦ｈ１）ことで、半導体装置１全体の厚み（高さ）Ｔ０が、配線基板２の厚みと最も高さが高い受動部品４の高さ（ここでは受動部品４ａの高さｈ１）とでほぼ決まることになり、配線基板２に放熱用部材５を搭載しても半導体装置１全体の厚みＴ０は増加せず、半導体装置１全体の厚み（高さ）Ｔ０を最も薄く（低く）することができる。例えば、半導体装置１全体の厚みＴ０を１ｍｍ以下にすることができる。
また、本実施の形態では、半導体チップ３だけでなく、半導体チップ３よりも高さが低い受動部品４ｂも覆うように、放熱用部材５を配線基板２の上面２ａに搭載（接合）しているので、放熱用部材５の天井部５ｂの上面５ｄの面積を比較的大きくすることができる。このため、放熱用部材５の上面５ｄをマーキングエリア（マーキング２１を行う領域）として使用するのが容易になる。また、半導体装置１を吸着する際の吸着エリアとして、放熱用部材５の上面５ｄを利用することが容易になる。
また、半導体チップ３を金属材料などからなる放熱用部材５で覆うことで、すなわち半導体チップ３を金属材料などからなる放熱用部材５内に封止することで、半導体チップ３を電磁界または静電気に対してシールドすることができる。このため、放熱用部材５内の半導体チップ３に対する放熱用部材５外部からの高周波の影響を、放熱用部材５のシールド効果によって防止でき、半導体チップ３の誤動作を防止することができる。また、放熱用部材５内の半導体チップ３から発生した高周波が放熱用部材５外部に漏れるのを防止でき、半導体装置１外部の周辺機器（周辺部品）の誤動作や特性劣化などを防止できる。
配線基板２に半導体チップ３をフリップチップ実装し、半導体チップ３を覆うような放熱用部材５を配線基板２に搭載して半導体チップ３の裏面３ｂに放熱用部材を接続させることで、半導体増幅素子チップのような発熱量が多い半導体チップ３の発熱を放熱用部材５を介して配線基板２へ放熱させて放熱特性を向上させることができるが、配線基板２には、半導体チップ３以外の電子部品（受動部品４）が搭載されているので、配線基板２上に放熱用部材５を搭載しただけでは、半導体装置（ＲＦパワーモジュール）全体の厚みが厚くなる可能性があるが、本実施の形態では、発熱量が多く放熱特性の向上が必要な半導体チップ３は覆うが、その高さが半導体チップの高さｈ０よりも高い電子部品（受動部品４ａ）は覆わないように、放熱用部材５を配線基板２に搭載（接合）し、半導体チップ３よりも高さが高い電子部品（受動部品４ａ）は、放熱用部材５の外部の配線基板２の上面２ａに搭載して、放熱用部材５の内部の配線基板２の上面２ａには搭載しないようにすることで、半導体装置（ＲＦパワーモジュール）全体の薄型化を可能としており、放熱特性の向上と半導体装置（ＲＦパワーモジュール）の薄型化の両立が可能になる。
図８は、半導体装置１が実装基板３１に実装（２次実装）された状態を概念的に示す断面図である。
上記のような構成を有する半導体装置１は、半導体装置１の出荷先などで、図８に示されるように、実装基板（配線基板、外部回路基板、マザーボード）３１に実装される。
実装基板３１の上面には、実装基板電極（端子、電極）３２が形成されており、半導体装置１の配線基板２の下面２ｂの外部接続端子１２ｂが実装基板３１の実装基板電極３２に半田などの接合材３３を介して接合（接続、半田接続、実装）され、電気的に接続されている。半導体装置１の配線基板２の下面２ｂの基準電位供給用端子１２ｃは、実装基板３１の基準電位供給用の実装基板電極３２ａに接合材３３を介して接合（半田接続）され、半導体装置１の基準電位供給用端子１２ｃに基準電位（例えば接地電位）が供給される。
半導体装置１の配線基板２を実装基板３１に接合材３３を介して実装（接合）しているので、半導体チップ３で発生した熱は、放熱用部材５およびバンプ電極１７を介して配線基板２に伝導され、更に実装基板３１に伝導されて放熱される。特に、半導体装置１の配線基板２の下面２ｂの基準電位供給用端子１２ｃを実装基板３１の実装基板電極３２ａに接合（半田接続）するので、半導体チップ３で発生した熱は、半導体チップ３の裏面３ｂから、接合材１８、放熱用部材５、接合材１９、基板側端子１２ａ、ビアホール１３内の導体（導体膜）、基準電位供給用端子１２ｃおよび接合材３３を経て実装基板３１に放熱し、また、半導体チップ３の表面３ａから、バンプ電極１７、基板側端子１２ａ、ビアホール１３ａ内の導体（導体膜）、基準電位供給用端子１２ｃおよび接合材３３を経て実装基板３１に放熱することができる。
図９〜図１１は、本発明の一実施の形態である半導体装置の製造工程中の断面図である。
まず、図９に示されるように、配線基板２を準備する。配線基板２は、例えば印刷法、シート積層法またはビルドアップ法などを用いて製造することができる。
次に、図１０に示されるように、配線基板２の上面２ａの受動部品４を搭載予定の領域（受動部品４を接続すべき基板側端子１２ａ）に半田（接合材１５）を印刷または塗布する。それから、配線基板２の上面２ａ上に受動部品４を搭載し、配線基板２の上面２ａ上に半導体チップ３を搭載する。配線基板２の上面２ａ上に受動部品４を先に搭載しても、あるいは半導体チップ３を先に搭載してもよい。配線基板２に半導体チップ３を搭載する際には、半導体チップ３の裏面３ｂ側が上方を向き、表面３ａ側が配線基板２の上面２ａ側を向くようにし、半導体チップ３の表面３ａに設けられている半田バンプ（バンプ電極１７）が配線基板２の上面２ａの基板側端子１２ａに対向するように位置合わせされる。
それから、半田リフロー処理などを行って、受動部品４および半導体チップ３を配線基板２に半田（接合材１５）や半田バンプ（バンプ電極１７）を介して接合し、電気的に接続する。
次に、図１１に示されるように、放熱用部材５を搭載予定の基板側端子１２ａ上に銀ペースト（接合材１９）を塗布し、半導体チップ３の裏面３ｂ上に銀ペースト（接合材１８）を塗布する。それから、半導体チップ３と、半導体チップ３よりも高さが低い受動部品４ｂとを覆うように、配線基板２の上面２ａ上に放熱用部材５を搭載する。この際、放熱用部材５の接合部５ｅは、銀ペースト（接合材１９）を介して配線基板２の上面２ａの基板側端子１２ａ上に配置され、半導体チップ３の天井部５ｂの内面５ｃは、銀ペースト（接合材１８）を介して半導体チップ３の裏面３ｂに接触する。そして、熱処理などにより銀ペースト（接合材１８，１９）を硬化し、放熱用部材５の接合部５ｅを配線基板２の上面２ａの基板側端子１２ａ上に接合し、半導体チップ３の裏面３ｂを半導体チップ３の天井部５ｂの内面５ｃに接合する。接合材１８，１９は半田により形成することもでき、この場合、受動部品４や半導体チップ３を配線基板２に接合するために用いた半田（接合材１５）および半田バンプ（バンプ電極１７）の融点よりも高い融点を有する半田を、放熱用部材５を配線基板２および半導体チップ３の裏面３ｂに接合するための半田（接合材１８，１９）に用いることが好ましい。これにより、放熱用部材５を配線基板２に接合するための半田リフロー処理（配線基板２に放熱用部材５を搭載した後の半田リフロー処理）の際に、受動部品４や半導体チップ３を配線基板２に接合する半田（接合材１５、バンプ電極１７）が溶融するのを防止することができる。
このようにして、図１〜図３に示されるような半導体装置１を製造することができる。１枚の配線基板２から複数の半導体装置１を製造する場合は、放熱用部材５を配線基板２に接合した後、配線基板２を所定の位置で分割し、各個片としての半導体装置１を得ることができる。
（実施の形態２）
図１２は、本発明の他の実施の形態である半導体装置１ａが実装基板３１に実装（２次実装）された状態を概念的に示す断面図（側面断面図）であり、上記実施の形態１の図８に対応する。
本実施の形態の半導体装置１ａは、半導体チップ３の裏面３ｂに裏面電極（例えばＭＩＳＦＥＴの裏面ソース電極）３ｃが形成されており、この半導体チップ３の裏面電極３ｃを接合材１８を介して放熱用部材５の内面５ｃに接続（接合、接着）している。半導体装置１ａの他の構成は、上記実施の形態１の半導体装置１とほぼ同様であるので、ここではその説明を省略する。
本実施の形態の半導体装置１ａは、半導体チップ３の裏面電極３ｃを接合材１８を介して放熱用部材５の内面５ｃに接続（接合、接着）しているので、接合材１８、放熱用部材５および接合材１９を導電性材料により形成することで（例えば、放熱用部材５を金属材料により形成し、接合材１８，１９を銀ペーストまたは半田により形成することで）、半導体チップ３ｂの裏面電極３ｃに放熱用部材５を介して基準電位（例えば接地電位）などを供給することが可能になる。
また、図１２のように、半導体装置１ａを実装基板３１に実装した場合、実装基板３１の基準電位供給用の実装基板電極３２ａから、導電性の接合材３３、配線基板２の基準電位供給用端子１２ｃ、ビアホール１３内の導体（導体膜）、配線基板２の基板側端子１２ａ、導電性の接合材１９、導電性の放熱用部材５および導電性の接合材１８を介して、半導体チップ３の裏面電極３ｃに基準電位（例えば接地電位）などを供給することができる。
本実施の形態では、上記実施の形態１とほぼ同様の効果を得ることができ、更に、放熱用部材５を介して半導体チップ３の裏面電極３ｃに基準電位（例えば接地電位）などを供給することができる。
（実施の形態３）
図１３は、本発明の他の実施の形態である半導体装置１ｂの概念的な構造を示す上面図（平面図）であり、図１４は半導体装置１ｂの概念的な断面図（側面断面図）であり、図１５は、図１３において、放熱用部材５を透視（省略）した状態を示す上面図（平面図）である。図１３は上記実施の形態１の図１に対応し、図１４は上記実施の形態１の図２に対応し、図１５は上記実施の形態１の図３に対応する。
図１３〜図１５に示される本実施の形態の半導体装置（例えばＲＦパワーモジュールまたは高周波電力増幅装置）１ｂは、配線基板２ａの上面２ａにおける半導体チップ３、受動部品４および放熱用部材５の配置の位置関係以外は上記実施の形態１の半導体装置１とほぼ同様の構成を有するので、半導体チップ３、受動部品４および放熱用部材５の配置の位置関係以外についてはここではその説明を省略する。
上記実施の形態１の半導体装置１では、放熱用部材５は、半導体チップ３と半導体チップ３よりも低い受動部品４ｂとを覆いかつ半導体チップ３よりも高い受動部品４ａを覆わないように、配線基板２の上面２ａに搭載され、放熱用部材５の天井部５ｂの内面５ｃが半導体チップ３の裏面３ｂに接合材１８によって接続（接合、接着）されていたが、本実施の形態では、放熱用部材５は、半導体チップ３を覆いかつ受動部品４を覆わないように、配線基板２の上面２ａに搭載され、放熱用部材５の天井部５ｂの内面５ｃが半導体チップ３の裏面３ｂに接合材１８によって接続（接合、接着）されている。
すなわち、本実施の形態においても、上記実施の形態１と同様に、配線基板２ａの上面２ａには、高さ（最上部の高さ）ｈ１が半導体チップ３の高さ（最上部の高さ）ｈ０よりも高い受動部品４ａ（受動部品４ａの高さｈ１＞半導体チップ３の高さｈ０）を含む受動部品４が搭載され、半導体チップ３よりも高さが高い受動部品４ａは、放熱用部材５の外部の配線基板２の上面２ａに搭載され、放熱用部材５の内部の配線基板２の上面２ａには搭載されない。更に、本実施の形態では、配線基板２に搭載する受動部品４が、その高さ（最上部の高さ）ｈ２が半導体チップ３の高さ（最上部の高さ）ｈ０よりも低いような受動部品４ｂ（受動部品４ｂの高さｈ１＜半導体チップ３の高さｈ０）を含む場合には、半導体チップ３よりも高さが低い受動部品４ｂは、放熱用部材５の外部の配線基板２の上面２ａに搭載し、放熱用部材５の内部の配線基板２の上面２ａには搭載しない。従って、本実施の形態では、放熱用部材５は半導体チップ３だけを覆うことになる。他の構成については、上記実施の形態１とほぼ同様である。
また、図示は省略するけれども、本実施の形態においても上記実施の形態１と同様に、放熱用部材５の上面５ｄをマーキングエリアや吸着エリアに使用することもできる。また、本実施の形態においても上記実施の形態２と同様に、半導体チップ３の裏面３ｂに裏面電極３ｃを設け、半導体チップ３の裏面電極３ｃを導電性の接合材１８を介して導電性の放熱用部材５の内面５ｃに接続（接合、接着）することもできる。
本実施の形態においても、上記実施の形態１，２とほぼ同様の効果を得ることができる。例えば、半導体増幅素子チップのような発熱量が多い半導体チップ３を覆うが、他の電子部品（受動部品４）は覆わないように、放熱用部材５を配線基板２の上面に搭載し、半導体チップ３よりも高さが高い電子部品（受動部品４ａ）を含む半導体チップ３以外の電子部品（受動部品４）は放熱用部材５の外部の配線基板２の上面２ａに搭載しているので、半導体チップ３よりも高さが高い電子部品（受動部品４ａ）の上に放熱用部材５が配置されるこことはない。このため、半導体装置１全体の厚み（高さ）Ｔ０を薄く（低く）することができる。従って、使用する半導体装置の薄型化が特に要求される電子機器、例えば携帯電話などへの半導体装置１ｂの使用がより容易になる。また、半導体増幅素子チップのような発熱量が多い半導体チップ３の発熱を放熱用部材５を介して配線基板２へ放熱させることができるので、半導体チップ３およびそれを搭載した半導体装置１ｂの放熱特性を向上させることができ、放熱特性の向上と半導体装置（ＲＦパワーモジュール）の薄型化の両立が可能になる。また、放熱用部材５の内部に半導体チップ３以外の電子部品（受動部品４）は搭載されないので、放熱用部材５の天井部５ｂが平板状で内面５ｃが平坦であっても、放熱用部材５と受動部品４が接触することはない。このため、受動部品４と放熱用部材５との間の短絡を防止することができる。また、放熱用部材５の天井部５ｂの内面５ｃを平坦にでき、放熱用部材５を比較的単純な構造とすることができるので、放熱用部材５の加工が容易である。このため、半導体装置の製造コストを低減できる。また、半導体チップ３を金属材料などからなる放熱用部材５で覆うことで、半導体チップ３を電磁界または静電気に対してシールドすることができる。
また、本実施の形態では、半導体チップ３を覆うが他の電子部品（受動部品４）は覆わないように、放熱用部材５を配線基板２の上面２ａに搭載しているので、放熱用部材５の寸法（平面寸法、面積）を縮小することが可能になる。このため、放熱用部材５の部材コストを低減でき、半導体装置の低コスト化に有利となる。また、配線基板２の上面２ａにおける半導体チップ３および受動部品４の配置の自由度を高めることができる。また、配線基板２への放熱用部材２の取り付け（搭載）工程を簡易化できる。また、上記実施の形態１のように半導体チップ３だけでなく、半導体チップ３よりも低い受動部品４ｂも覆うように、放熱用部材５を配線基板２の上面２ａに搭載した場合は、放熱用部材５の天井部５ｂの上面（外面）５ｄの面積を比較的大きくすることができ、放熱用部材５の上面（外面）５ｄをマーキングエリアや吸着エリアとして用いることがより容易となる。
（実施の形態４）
図１６は、本発明の他の実施の形態である半導体装置１ｃの概念的な構造を示す上面図（平面図）であり、図１７は半導体装置１ｃの概念的な断面図（側面断面図）である。図１６は上記実施の形態１の図１に対応し、図１７は上記実施の形態１の図２に対応する。
図１６および図１７に示される本実施の形態の半導体装置（例えばＲＦパワーモジュールまたは高周波電力増幅装置）１ｃは、放熱用部材５の形状以外は、上記実施の形態１の半導体装置１とほぼ同様の構成を有するので、放熱用部材５以外の構成についてはここではその説明を省略する。
上記実施の形態１の半導体装置１では、放熱用部材５は配線基板２の上面２ａに接合されていたが、本実施の形態の半導体装置１ｃでは、放熱用部材５は、その一部は配線基板２の上面２ａに接合され、他の一部は配線基板２の上面２ａ外まで張り出して、配線基板２の側面２ｃ上に延在している。
図１６および図１７に示されるように、本実施の形態では、上記実施の形態１と同様に、放熱用部材５は、半導体チップ３の周囲を囲む側壁部５ａと、側壁部５ａの上部を連結し、半導体チップ３の上部を覆う天井部５ｂとを有しており、天井部５ｂの内面５ｃが半導体チップ３の裏面３ｂに接合材１８によって接続（接合、接着）されている。放熱用部材５の側壁部５ａの一部（一辺）には、上記実施の形態１と同様の接合部５ｅが設けられて配線基板２の上面２ａの基板側端子１２ａに接合材１９によって接合されているが、放熱用部材５の側壁部５ａの他の一部（一辺）は、配線基板２の上面２ａの外部に位置して配線基板２の側面２ｃ上に延在している。放熱用部材５の側壁部５ａの配線基板２の側面２ｃ上に延在している部分には凸部５ｆが設けられており、この凸部５ｆが配線基板２の側面２ｃに形成された切り欠き部（凹部）２ｄに嵌め合わされることで、固定されている。他の構成については上記実施の形態１とほぼ同様である。
また、図示は省略するけれども、本実施の形態においても上記実施の形態１と同様に、放熱用部材５の上面５ｄをマーキングエリアや吸着エリアに使用することもできる。また、上記実施の形態２と同様に、本実施の形態においても、半導体チップ３の裏面３ｂに裏面電極３ｃを設け、半導体チップ３の裏面電極３ｃを導電性の接合材１８を介して導電性の放熱用部材５の内面５ｃに接続（接合、接着）することもできる。また、上記実施の形態３と同様に、本実施の形態においても、放熱用部材５を、半導体チップ３を覆いかつ受動部品４を覆わないように、配線基板２の上面２ａに搭載することもできる。
図１８は、本実施の形態の半導体装置１ｃが実装基板３１に実装（２次実装）された状態を概念的に示す断面図であり、上記実施の形態１の図８に対応する。
半導体装置１ｃを実装基板３１に実装する際には、図１８に示されるように、配線基板２の下面２ｂの外部接続端子１２ｂが実装基板３１の実装基板電極３２に半田などの接合材３３を介して接合（接続、半田接続、実装）され、電気的に接続される。この際、放熱用部材５の側壁部５ａの配線基板２の側面２ｃ上に延在している部分と、実装基板３１の実装基板電極３２とが、半田などの接合材３３を介して接合（接続、半田接続）されるようにする。
本実施の形態においても、上記実施の形態１〜３とほぼ同様の効果を得ることができる。更に、本実施の形態では、半導体チップ３で発生した熱は、半導体チップ３の表面３ａ側から、バンプ電極１７を介して配線基板２に伝導され実装基板３１に放熱され、半導体チップ３の裏面３ｂ側から、放熱用部材５を介して配線基板２に伝導され実装基板３１に放熱されるが、放熱用部材５の一部を半田などの接合材３３を介して直接的に実装基板３１の実装基板電極３２に接合（接続、半田接続）し、半導体チップ３の裏面３ｂ側から、放熱用部材５を介して実装基板３１への放熱を促進することができる。このため、半導体チップ３およびそれを搭載した半導体装置１ｃの放熱特性をより向上でき、半導体装置１の性能をより向上することができる。また、半導体チップ３の発熱を、バンプ１７を介して放熱する経路よりも、放熱用部材５を介して放熱する経路でより多く放熱することが可能になり、バンプ１７の熱劣化を抑制でき、半導体装置の信頼性を向上することができる。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
例えば、前記実施の形態では、ＲＦパワーモジュール（高周波電力増幅装置）について説明したが、本発明は、これに限定されるものではなく、配線基板上に能動素子からなる半導体チップと、受動素子からなる受動部品とを搭載した種々の半導体装置に適用することができる。
本願において開示される発明の実施形態のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
半導体チップと受動部品とを配線基板上に搭載した半導体装置において、半導体チップをフリップチップ実装し、半導体チップを覆うような放熱用部材を配線基板に搭載して半導体チップの裏面に接続させ、半導体チップよりも高さが高い受動部品は放熱用部材の外部の配線基板上に搭載して放熱用部材の内部の配線基板上には搭載しないことにより、半導体装置の薄型化が可能になる。また、半導体装置の放熱特性を向上することができる。
また、本発明は、半導体増幅素子チップと他の電子部品とを配線基板上に搭載した半導体装置において、半導体増幅素子チップをフリップチップ実装し、半導体増幅素子チップを覆うような放熱用部材を配線基板に搭載して半導体増幅素子チップの裏面に接続させ、半導体増幅素子チップよりも高さが高い電子部品は放熱用部材の外部の配線基板上に搭載して放熱用部材の内部の配線基板上には搭載しないことにより、半導体装置の薄型化が可能になる。また、半導体装置の放熱特性を向上することができる。In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view or the like may be hatched to make the drawing easy to see.
(Embodiment 1)
A semiconductor device (electronic device) of the present embodiment will be described with reference to the drawings. In this embodiment, the semiconductor device (electronic device) is applied to a high-frequency module such as a high-frequency power amplifier module (a high-frequency power amplifier module, an RF (Radio Frequency) power module, a high-frequency power amplifier, or a power amplifier). The case will be described.
FIG. 1 is a top view (plan view) showing a conceptual structure of a semiconductor device (RF module) 1 of the present embodiment, and FIG. 2 is a conceptual cross-sectional view (side cross-sectional view) of the semiconductor device 1. is there. FIG. 3 is a top view (plan view) showing a state in which the heat radiating member 5 is seen through (omitted) in FIG. FIG. 4 is a top view (plan view) of the heat radiating member 5 used in the semiconductor device 1, and FIGS. 5 and 6 are cross-sectional views of the heat radiating member 5. FIG. 2 shows a conceptual cross-sectional structure for clarifying the height positional relationship and the like of each component of the semiconductor device 1, and for example, FIG. 3A when the heat radiating member 5 is not omitted. It almost corresponds to the cross section of line -A. 5 corresponds to a cross section taken along line BB in FIG. 4, and FIG. 6 corresponds to a cross section taken along line CC in FIG.
A semiconductor device 1 (here, an RF power module or a high frequency power amplifying device) 1 shown in FIGS. 1 to 3 is provided on a wiring board (multilayer board, multilayer wiring board, module board) 2 and wiring board 2. A semiconductor chip (semiconductor element, active element) 3 composed of mounted (mounted) active elements, a passive component (passive element, chip component) 4 composed of passive elements mounted (mounted) on the wiring board 2, and a semiconductor chip And a heat radiating member (metal cap, metal cover, heat radiating cap, heat radiating cover, heat radiating plate) 5 mounted (bonded) to the wiring board 2 so as to cover 3. The semiconductor chip 3 and the passive component 4 are electrically connected to the conductor layer (electrode, wiring, transmission line) of the wiring board 2. In addition, the semiconductor device 1 can be mounted on, for example, an external circuit board (not shown) or a mother board.
As the wiring substrate 2, for example, a multilayer substrate (multilayer wiring substrate) in which a plurality of insulator layers (dielectric layers) 11 and a plurality of conductor layers (wiring layers) are laminated and integrated can be used. In FIG. 2, four insulating layers 11 are laminated to form the wiring board 2. However, the number of laminated insulating layers 11 is not limited to this and can be variously changed. As a material for forming the insulator layer 11 of the wiring board 2, for example, alumina (aluminum oxide, Al 2 O 3 ) Etc. can be used. In this case, the wiring board 2 is a ceramic multilayer board. By forming the insulator layer 11 from a ceramic material having a higher thermal conductivity than the resin material and making the wiring board 2 a ceramic substrate (ceramic multilayer substrate), the heat dissipation characteristics of the semiconductor device 1 can be further improved. The material of the insulator layer 11 of the wiring board 2 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin can be used.
Between the upper surface (front surface, main surface, first main surface) 2a and lower surface (back surface, main surface) 2b of the wiring substrate 2 and between each insulator layer 11, a conductor layer (wiring layer, wiring pattern) for wiring formation is formed. , Conductor pattern) is formed. A board-side terminal (terminal, electrode) 12a made of a conductor is formed on the upper surface 2a of the wiring board 2 by the uppermost conductor layer of the wiring board 2, and the lowermost conductor layer of the wiring board 2 allows the wiring board 2 to External connection terminals (terminals, electrodes, module electrodes) 12b made of a conductor are formed on the lower surface 2b. A conductor layer (wiring layer, wiring pattern, conductor pattern) is also formed inside the wiring board 2, that is, between the insulator layers 11, but is not shown in FIG. 2 for the sake of simplicity. As a material for forming the conductor layer of the wiring board 2, for example, a material having good conductivity and thermal conductivity such as copper or copper alloy can be used. For example, the conductor layers (for example, the board-side terminal 12a and the external connection terminal 12b) on the upper surface 2a and the lower surface 2b of the wiring board 2 are made of nickel (Ni) plating and gold on the surface of an alloy of copper (Cu) and tungsten (W). (Au) plating can be applied in order. This gold plating has a function of preventing oxidation and erosion of the conductor layer. Moreover, the conductor layer (conductor layer between the insulator layers 11) inside (inner layer) of the wiring board 2 can be formed of, for example, an alloy of copper (Cu) and tungsten (W). Among the wiring patterns formed by the conductor layer of the wiring board 2, a wiring pattern for supplying a reference potential (for example, the reference potential supplying terminal 12 c on the lower surface 2 b of the wiring board 2) is used for forming the wiring of the insulator layer 11. A solid pattern that covers most of the surface area can be formed, and a wiring pattern for a transmission line can be formed as a strip pattern.
Each conductor layer (wiring layer) constituting the wiring board 2 is electrically connected through a conductor or a conductor film in a via hole (through hole) 13 formed in the insulator layer 11 as necessary. The conductor film in the via hole 13 is made of, for example, an alloy of copper (Cu) and tungsten (W). Accordingly, the board-side terminal 12a on the upper surface 2a of the wiring board 2 is provided on the upper surface 2a of the wiring board 2 and / or an internal wiring layer (wiring layer between the insulator layers 11), a conductor film in the via hole 13 or the like as necessary. Is electrically connected to the external connection terminal 12b on the lower surface 2b of the wiring board 2. Of the via holes 13, the via hole 13 a provided below the semiconductor chip 3 can function as a thermal via for conducting heat generated in the semiconductor element 3 to the lower surface 2 b side of the wiring substrate 2.
A plurality of passive components 4 are mounted on the upper surface 2 a of the wiring board 2. The passive component 4 includes a passive element such as a resistance element (for example, a chip resistor), a capacitance element (for example, a chip capacitor), or an inductor element (for example, a chip inductor). As the passive component 4, a chip component or the like can be used. Further, as the passive component 4, an integrated passive component (IPC: Integrated Passive Component, IPD: Integrated Passive Device) can be used. The electrode 14 of the passive component 4 is joined (mounted or connected) to the board-side terminal 12a on the upper surface 2a of the wiring board 2 by a conductive joining material (adhesive) 15 such as solder, and is electrically connected. .
The semiconductor chip 3 is composed of active elements, for example, a semiconductor amplifying element chip (high frequency power amplifying element chip). For example, the semiconductor chip 3 is a semiconductor amplification element that forms a power amplification circuit in the semiconductor device 1.
In the surface layer portion or inside of the semiconductor chip 3, for example, a heterojunction bipolar transistor mainly composed of GaAs or InP, a field effect transistor such as SiGe or Si-MISFET (Metal Insulator Semiconductor Field Effect Transistor), or GaAs is used. A semiconductor element (semiconductor amplification element) such as a HEMT (High Electron Mobility Transistor) as a main component is formed. The semiconductor chip 3 is formed by forming various semiconductor elements (semiconductor amplification elements) or semiconductor integrated circuits on a semiconductor substrate (semiconductor wafer) made of, for example, single crystal silicon, and then grinding the back surface of the semiconductor substrate as necessary. Then, the semiconductor substrate is separated into each semiconductor chip 3 by dicing or the like. A plurality of bump electrodes (projection electrodes) 17 are formed on the surface (main surface on the semiconductor element formation side) 3 a of the semiconductor chip 3. The bump electrode 17 is, for example, a solder bump. A gold bump or the like can be used as the bump electrode 17. The bump electrode 17 is electrically connected to a semiconductor element (semiconductor amplification element) or a semiconductor integrated circuit formed on the semiconductor chip 3.
FIG. 7 is a circuit block diagram showing an example of the circuit configuration of the semiconductor chip 3. FIG. 7 illustrates a circuit block of a semiconductor chip 3 for an amplifier circuit used in an RF power module that can use, for example, two frequency bands of GSM900 and DCS1800 (dual band system). In the circuit of FIG. 7, the two frequency bands (GSM and DCS) are divided into two amplifier circuits for amplification. Each amplifier circuit amplifies, for example, three stages, and one transistor 20a (for example, MISFET) is used for each stage. The amplifier circuit (transistor 20a) at each stage is controlled by the control circuit 20b. Further, the semiconductor chip 3 incorporates the amplifier circuit of FIG. 7 in one chip. Accordingly, the semiconductor device 1 is constituted by a circuit including the semiconductor chip 3 for amplification and the passive components 4 (plural).
The semiconductor chip 3 is flip-chip connected (flip chip mounted) to the upper surface 2 a of the wiring board 2. That is, the back surface (main surface opposite to the main surface on the semiconductor element formation side) 3b of the semiconductor chip 3 faces upward, and the front surface (main surface on the semiconductor element formation side) 3a is the upper surface 2a of the wiring board 2. Is mounted (mounted) on the upper surface 2 a of the wiring board 2 in a direction opposite to the wiring board 2. Therefore, the semiconductor chip 3 is face-down bonded to the upper surface 2 a of the wiring board 2. The bump electrodes 17 on the surface 3a of the semiconductor chip 3 are joined (mounted or connected) to the board-side terminals 12a on the upper surface 2a of the wiring board 2 and are electrically connected. For this reason, the semiconductor element (semiconductor amplification element) or the semiconductor integrated circuit formed on the semiconductor chip 3 is electrically connected to the substrate-side terminal 12 a on the upper surface 2 a of the wiring substrate 2 via the bump electrode 17. In order to buffer the burden on the bump electrode 17 due to the difference in thermal expansion coefficient between the semiconductor chip 3 and the wiring board 2, an underfill resin (not shown) is provided between the semiconductor chip 3 and the upper surface 2 a of the wiring board 2. ).
In the present embodiment, as described above, the semiconductor chip 3 is face-down bonded to the wiring board 2 and flip-chip mounted. Therefore, unlike the present embodiment, the semiconductor chip 3 is face-up bonded to the wiring board 2 and the substrate-side terminals 12a of the wiring board 2 and the bonding pads of the semiconductor chip 3 are connected by bonding wires. The thickness (height) of the semiconductor device 1 can be made thinner (lower) by the loop height of the bonding wire. Therefore, it is advantageous for reducing the thickness of the semiconductor device.
A heat radiating member (metal cap, metal cover, heat radiating cap, heat radiating cover, heat radiating plate) 5 is mounted (joined) on the upper surface 2 a of the wiring board 2 so as to cover the semiconductor chip 3. The back surface 3 b of the semiconductor chip 3 is connected (joined) to the inner surface of the member 5. The heat dissipating member 5 is made of a material having good (high) thermal conductivity, for example, a metal material such as copper (Cu). The heat radiating member 5 is a metal cap, for example, and can be formed by processing a metal plate. Moreover, it is more preferable if the heat radiating member 5 is formed of a material with good moldability. If the heat radiating member 5 is made of, for example, copper (Cu) or an alloy containing copper as a main component, the thermal conductivity and formability of the heat radiating member 5 can be improved, and the member cost of the heat radiating member 5 is further reduced. it can.
The heat radiating member 5 is connected to a side wall (leg part) 5a surrounding the periphery of the semiconductor chip 3 and an upper part of the side wall 5a, and covers the upper part of the semiconductor chip 3 (upper wall, top plate, roof). Part) 5b. An inner surface (lower surface, inner wall) 5 c of the ceiling part 5 b of the heat radiating member 5 is connected (bonded or bonded) to the back surface 3 b of the semiconductor chip 3 by a bonding material (adhesive material) 18. The bonding material 18 for bonding the semiconductor chip 3 and the heat dissipating member 5 is preferably made of a bonding material with good (high) thermal conductivity, for example, silver paste or solder.
At least a part (in this case, the bonding portion 5e) of the heat radiation member 5 is bonded (connected or bonded) to the board-side terminal 12a of the upper surface 2a of the wiring board 2 by a bonding material (adhesive) 19. Has been. The bonding material 19 for bonding the heat dissipating member 5 and the board-side terminal 12a on the upper surface 2a of the wiring board 2 is preferably made of a bonding material having good (high) thermal conductivity, for example, solder or silver paste. The board-side terminal 12a to which the heat dissipating member 5 is bonded via the bonding material 19 is formed on the upper surface 2a of the wiring board 2 or the inner wiring layer (wiring layer between the insulator layers 11), the conductor film in the via hole 13, or the like. Via the reference potential supply terminal 12c on the lower surface 2b of the wiring board 2.
As shown in FIGS. 1 to 6, the connecting portion is connected to the lowermost portion of the side wall portion 5 a of the heat radiating member 5 and extends (projects) therefrom in a direction substantially parallel to the upper surface 2 a of the wiring board 2. 5e is provided in at least a part of the lower portion of the side wall portion 5a of the heat radiating member 5, and the joint portion 5e of the heat radiating member 5 is joined to the board side terminal 12a on the upper surface 2a of the wiring board 2 through the joining material 19. For example, the bonding area between the heat radiation member 5 and the board-side terminal 12a on the upper surface 2a of the wiring board 2 can be increased, and the bonding strength can be increased. In addition, the side wall part 5a, the ceiling part 5b, and the junction part 5e of the heat radiating member 5 can be made into one member formed integrally, for example, the heat radiating member 5 is formed by processing a metal plate etc. be able to. Further, by adopting a structure in which the heat radiating member 5 (joining portion 5e thereof) is joined to the upper surface 2a of the wiring board 2, the mounting (joining) process of the heat radiating member 5 to the wiring board 2 becomes easy, and the semiconductor device 1 The manufacturing process is not complicated, and the manufacturing cost of the semiconductor device 1 can be reduced.
Further, marking 21 such as a product number can be performed on the upper surface (outer surface) 5d of the ceiling portion 5a of the heat radiating member 5. The marking 21 includes a product number (which may include a symbol or a symbol) of the semiconductor device 1 or a lot number (which may include a symbol or a symbol) after the heat radiation member 5 is mounted on the wiring board 2. It can be formed by printing on the upper surface (outer surface) 5d of the ceiling portion 5a of the heat dissipating member 5. In the present embodiment, as will be described later, since the heat dissipation member 5 is mounted on the wiring board 2 so as to cover the semiconductor chip 3 and the passive component 4b lower than the semiconductor chip 3, the heat dissipation member 5 The area of the upper surface 5d of the ceiling part 5b can be made relatively large, and the upper surface 5d of the heat radiation member 5 can be easily used as a marking area. Further, the upper surface 5d of the heat radiating member 5 can also be used as an adsorption area when the semiconductor device 1 is adsorbed and moved. The marking 21 can be omitted if unnecessary.
The heat generated in the semiconductor chip 3 is conducted from the front surface 3a side of the semiconductor chip 3 to the wiring substrate 2 via the bump electrode 17 and the substrate side terminal 12a, and further from the back surface 3b side of the semiconductor chip 3 to the bonding. Conduction is performed to the wiring board 2 through the material 18, the heat radiation member 5, the bonding material 19, and the board-side terminal 12 a. In particular, when the semiconductor chip 3 is a semiconductor amplifying element chip, the semiconductor chip 3 generates a large amount of heat. Therefore, if the heat dissipation characteristics of the semiconductor chip 3 are not improved, the performance of the semiconductor chip 3 and the semiconductor device 1 on which the semiconductor chip 3 is mounted deteriorates. End up. In the present embodiment, the heat dissipation path of the semiconductor chip 3 is provided not only with the heat dissipation path that radiates heat to the wiring board 2 via the bump electrodes 17 but also the heat dissipation path that radiates heat to the wiring board 2 via the heat dissipation member 5. Thereby, the heat dissipation characteristics of the semiconductor chip 3 and the semiconductor device 1 on which the semiconductor chip 3 is mounted can be improved, and the performance of the semiconductor device 1 can be improved. Further, it is possible to dissipate more heat from the semiconductor chip 3 through the path for radiating heat from the heat radiating member 5 to the wiring board 2 than through the path for radiating heat to the wiring board 2 via the bumps 17. Thermal degradation can be suppressed and the reliability of the semiconductor device can be improved.
In the present embodiment, since the semiconductor chip 3 is flip-chip mounted on the wiring substrate 2, the semiconductor chip 3 is face-up bonded to the wiring substrate 2, and the substrate-side terminal 12a of the wiring substrate 2 and the semiconductor are bonded by wire bonding. Compared to the case where the bonding pads of the chip 3 are connected, the thickness (height) T of the entire semiconductor device 1 is equal to the loop height of the bonding wires. 0 Can be made thinner (lower). Therefore, it is advantageous for reducing the thickness of the semiconductor device 1. Further, the heat generated in the semiconductor chip 3 is radiated from the front surface 3 a side of the semiconductor chip 3 to the wiring substrate 2 through the bump electrodes 17, and is wired from the back surface 3 b side of the semiconductor chip 3 through the heat radiating member 5. Since heat can be radiated to the substrate 2, it is equivalent to the case where the semiconductor chip 3 is face-up bonded to the wiring substrate 2 and the substrate side terminal 12a of the wiring substrate 2 and the bonding pad of the semiconductor chip 3 are connected by wire bonding. The above heat dissipation characteristics can be obtained.
In the present embodiment, the semiconductor chip 3 is flip-chip mounted on the wiring board 2, and the semiconductor chip 3 is connected to the board-side terminal 12 a of the wiring board 2 via the bump electrode 17. For this reason, compared with the case where the semiconductor chip 3 and the wiring board 2 are connected by wire bonding, the area of the electrode on the surface 3a of the semiconductor chip 3 and the substrate side terminal 12a of the wiring board 2 can be reduced. Accordingly, the areas of the semiconductor chip 3 and the wiring substrate 2 can be reduced, which is advantageous for downsizing the semiconductor device 1.
In the present embodiment, a via hole 13a as a thermal via is provided below the semiconductor chip 3 to assist heat dissipation of the heat generated by the semiconductor chip 3, and the semiconductor device 3 and the semiconductor device 3 are mounted on the via hole 13a. Although the heat dissipation characteristics of the semiconductor device 1 can be further improved, the heat generated by the semiconductor chip 3 can be dissipated to the wiring substrate 2 via the heat dissipation member 5, so that it is disposed below the semiconductor chip 3. The formation of the via hole 13a as a thermal via can be omitted. By omitting the via hole 13a as a thermal via disposed below the semiconductor chip 3, the wiring board 2 can be downsized (smaller in area) and the wiring board 2 can have a more complicated wiring structure.
As described above, a plurality of passive components 4 as electronic components other than the semiconductor chip 3 are mounted on the upper surface 2a of the wiring board 2. In the present embodiment, the height (maximum) of the passive components 4 is the highest. Top height) h 1 Is the height of the semiconductor chip 3 (the height at the top) h 0 Passive component 4a (height h of passive component 4a 1 > Height h of the semiconductor chip 3 0 ) Is mounted on a region 22a of the upper surface 2a of the wiring board 2 that is not covered by the heat radiating member 5 (a region outside the heat radiating member 5). 5 is not mounted on the area 22b (area inside the heat dissipation member 5) covered with the area 5. That is, the height h of the passive component 4a of the passive components 4 1 Is the height h of the semiconductor chip 3 0 Higher than the height h of the passive component 4a 1 > Height h of the semiconductor chip 3 0 The passive component 4 including the passive component 4a having a height higher than that of the semiconductor chip 3 is mounted on the upper surface 2a of the wiring board 2a. The passive component 4a having a height higher than the semiconductor chip 3 is It is mounted on the upper surface 2 a of the wiring board 2 outside the heat radiating member 5 and is not mounted on the upper surface 2 a of the wiring board 2 inside the heat radiating member 5.
Further, in the present embodiment, the height (top height) h of the passive components 4. 2 Is the height of the semiconductor chip 3 (the height at the top) h 0 Passive component 4b (height h of passive component 4b) 2 <Height h of the semiconductor chip 3 0 ) On the upper surface 2 a of the wiring board 2 that is not covered by the heat radiating member 5 (a region outside the heat radiating member 5) 22 a and the heat radiating member 5 on the upper surface 2 a of the wiring board 2. It is mounted on the covered area (area inside the heat dissipation member 5) 22b. That is, the height h of the passive component 4b of the passive components 4 2 Is the height h of the semiconductor chip 3 0 Lower than the height h of the passive component 4b 2 <Height h of the semiconductor chip 3 0 The passive component 4b having a height lower than that of the semiconductor chip 3 includes the upper surface 2a (that is, the region 22a) of the wiring substrate 2 outside the heat radiating member 5 and the upper surface of the wiring substrate 2 inside the heat radiating member 5. 2a (that is, the region 22b).
Therefore, in the present embodiment, the heat dissipation member 5 covers the semiconductor chip 3 and the passive component 4b having a height lower than that of the semiconductor chip 3, and does not cover the passive component 4a having a height higher than that of the semiconductor chip 3. As described above, the wiring board 2 is mounted (bonded) to the upper surface 2a.
In the present embodiment, the height h of the semiconductor chip 3 0 Is the height h of the top of the semiconductor chip 3 0 The height from the upper surface 2a of the wiring substrate 2 to the top of the semiconductor chip 3 when the semiconductor chip 3 is mounted (mounted) on the upper surface 2a of the wiring substrate 2 (perpendicular to the upper surface 2a of the wiring substrate 2). Direction height) h 0 Corresponding to When the semiconductor chip 3 is flip-chip mounted, the back surface 3b of the semiconductor chip 3 corresponds to the uppermost part of the semiconductor chip 3, so that the height (wiring) from the top surface 2a of the wiring substrate 2 to the back surface 3b of the semiconductor chip 3 The height h in the direction perpendicular to the upper surface 2a of the substrate 2 is the height h of the semiconductor chip 3. 0 It will correspond to. Further, the height h of the passive component 4 (4a, 4b) 1 , H 2 Is the height h of the uppermost part of the passive component 4 (4a, 4b) 1 , H 2 The height from the upper surface 2a of the wiring board 2 to the top of the passive component 4 (4a, 4b) when the passive component 4 (4a, 4b) is mounted (mounted) on the upper surface 2a of the wiring board 2 (Height in a direction perpendicular to the upper surface 2a of the wiring board 2) h 1 , H 2 Corresponding to When the passive component 4 (4a, 4b) is a chip component, the upper surface 16 of the passive component 4 (4a, 4b) corresponds to the uppermost part of the passive component 4 (4a, 4b). To the upper surface 16 of the passive component 4 (4a, 4b) (the height in the direction perpendicular to the upper surface 2a of the wiring board 2) is the height h of the passive component 4 (4a, 4b). 1 , H 2 It will correspond to.
The height of the heat dissipating member 5 is defined by the height of the electronic component (element) having the highest height among the electronic components (passive component 4 and semiconductor chip 3) inside the heat dissipating member 5. Unlike the present embodiment, it may be possible to mount (join) the heat dissipation member 5 on the upper surface 2a of the wiring board 2 so as to cover the passive component 4a higher than the semiconductor chip 3 together with the semiconductor chip 3. In this case, the height of the heat dissipating member 5 is not the semiconductor chip 3 but the height h of the passive component 4a higher than the semiconductor chip 3. 1 It will be prescribed by. Since the ceiling portion 5b of the heat radiating member 5 is disposed above the passive component 4a higher than the semiconductor chip 3, the thickness of the entire semiconductor device 1 is increased. Further, from the viewpoint of preventing short circuit, it is better not to contact the heat dissipation member 5 made of a metal material such as copper with the electrode 14 of the passive component 4, so that the passive component 4 a having a height higher than that of the semiconductor chip 3 and the heat dissipation. It is necessary to provide a gap between the semiconductor member 1 and the semiconductor device 1 as a whole. Moreover, in order to join the heat radiating member 5 to the back surface 3b of the semiconductor chip 3 without making contact with the passive component 4b, it is necessary to provide unevenness on the inner surface 5c of the heat radiating member 5, and the processing of the heat radiating member 5 is performed. It's not easy.
On the other hand, in the present embodiment, the electronic component (passive component 4b) whose height is lower than that of the semiconductor chip 3 is covered together with the semiconductor chip 3, but the electronic component (passive component 4a) whose height is higher than that of the semiconductor chip 3 is covered. ) Is mounted (joined) on the upper surface 2a of the wiring board 2 so as not to cover. An electronic component (passive component 4 a) having a height higher than that of the semiconductor chip 3 is mounted on the upper surface 2 a of the wiring substrate 2 outside the heat radiating member 5, and on the upper surface 2 a of the wiring substrate 2 inside the heat radiating member 5. Not installed. For this reason, the electronic component (element) having the highest height among the electronic components (here, the passive component 4 b and the semiconductor chip 3) inside the heat radiating member 5 is the semiconductor chip 3. H 3 Is defined by the height of the semiconductor chip 3. This is not the case where the heat dissipating member 5 is disposed on an electronic component (passive component 4a) having a height higher than that of the semiconductor chip 3. For this reason, the thickness (height) T of the entire semiconductor device 1 0 Can be made thinner (lower). For example, the thickness T of the entire semiconductor device 1 0 Can be 1 mm or less. Therefore, it becomes easier to use the semiconductor device 1 in an electronic device, for example, a mobile phone, which requires a thinner semiconductor device. For example, if the semiconductor device 1 of the present embodiment is applied to a power amplifying device mounted on a mobile phone, the effect is greater.
In the present embodiment, since the heat radiation member 5 is mounted (bonded) to the upper surface 2a of the wiring board 2 so as not to cover the electronic component (passive component 4a) having a height higher than that of the semiconductor chip 3. Even if the ceiling portion 5b of the heat radiating member 5 is flat and the inner surface 5c is flat, the electronic components other than the semiconductor chip 3 among the electronic components (semiconductor chip 3 and passive component 4b) in the heat radiating member 5 The heat radiating member 5 made of a conductor such as copper does not come into contact with the passive component 4b. For this reason, it is possible to prevent a short circuit between the electronic component (passive component 4 b) other than the semiconductor chip 3 and the heat dissipation member 5. Moreover, since the inner surface 5c of the ceiling part 5b of the heat radiating member 5 can be made flat and the heat radiating member 5 can have a relatively simple structure, the processing of the heat radiating member 5 is easy. For this reason, the manufacturing cost of the semiconductor device can be reduced. Further, since the ceiling portion 5b of the heat radiating member 5 can be formed in a flat plate shape and the upper surface 5d thereof can be flattened, the marking on the upper surface 5d of the heat radiating member 5 is facilitated. It becomes easy to use as.
In addition, the height of the heat dissipating member 5 (the height of the uppermost portion) h 3 Of the passive component 4 mounted on the upper surface 2a of the wiring board 2 (the height h of the passive component 4a in this case). 1 ) Or lower (the height h of the heat dissipating member 5) 3 ≦ Height h of passive component 4a 1 ) Is more preferable. In the present embodiment, the height h of the heat dissipating member 5 is 3 Is the height h at the top of the heat dissipating member 5 3 The height from the upper surface 2a of the wiring board 2 to the uppermost part of the heat radiating member 5 when the heat radiating member 5 is mounted (bonded) to the wiring board 2 (direction perpendicular to the upper surface 2a of the wiring board 2) Height) h 3 Corresponding to Since the upper surface (outer surface) 5d of the ceiling part 5b of the heat radiating member 5 corresponds to the uppermost part of the heat radiating member 5, the height from the upper surface 2a of the wiring board 2 to the upper surface 5d of the heat radiating member 5 (of the wiring board 2) The height in the direction perpendicular to the upper surface 2a) is the height h of the heat dissipating member 5. 3 It will correspond to.
After the semiconductor integrated circuit is formed on the semiconductor substrate (semiconductor wafer), the thickness of the semiconductor chip 3 can be reduced by grinding the back surface of the semiconductor substrate before dicing the semiconductor substrate. The thickness of the semiconductor chip 3 can be reduced to about 150 to 300 μm, and thus the height h of the semiconductor chip 3 when the semiconductor chip 3 is mounted on the wiring board 2. 0 Can be lowered. Height h of the semiconductor chip 3 0 The height h of the heat dissipating member 5 mounted on the wiring board 2 so as to cover the semiconductor chip 3 is reduced. 3 That is, the height of the passive component 4 having the highest height among the passive components 4 mounted on the upper surface 2a of the wiring board 2 (that is, the height of the passive component 4a in this case). H 1 ) Or lower (h) 3 ≦ h 1 ) So that the thickness (height) T of the entire semiconductor device 1 0 However, the thickness of the wiring board 2 and the height of the passive component 4 having the highest height (here, the height h of the passive component 4a). 1 ) And the thickness T of the entire semiconductor device 1 even if the heat dissipation member 5 is mounted on the wiring board 2. 0 The thickness (height) T of the entire semiconductor device 1 is not increased. 0 Can be made the thinnest (low). For example, the thickness T of the entire semiconductor device 1 0 Can be 1 mm or less.
In the present embodiment, the heat radiating member 5 is mounted (bonded) to the upper surface 2a of the wiring board 2 so as to cover not only the semiconductor chip 3 but also the passive component 4b having a height lower than that of the semiconductor chip 3. Therefore, the area of the upper surface 5d of the ceiling part 5b of the heat radiating member 5 can be made relatively large. For this reason, it becomes easy to use the upper surface 5d of the heat radiating member 5 as a marking area (a region where the marking 21 is performed). Further, it becomes easy to use the upper surface 5d of the heat dissipation member 5 as an adsorption area when the semiconductor device 1 is adsorbed.
Further, by covering the semiconductor chip 3 with a heat radiating member 5 made of a metal material or the like, that is, by sealing the semiconductor chip 3 in a heat radiating member 5 made of a metal material or the like, the semiconductor chip 3 is made to be electromagnetic field or static electricity. Can be shielded against. For this reason, the influence of the high frequency from the outside of the heat dissipation member 5 on the semiconductor chip 3 in the heat dissipation member 5 can be prevented by the shielding effect of the heat dissipation member 5, and the malfunction of the semiconductor chip 3 can be prevented. Further, it is possible to prevent the high frequency generated from the semiconductor chip 3 in the heat radiating member 5 from leaking to the outside of the heat radiating member 5, and it is possible to prevent malfunction or deterioration of characteristics of peripheral devices (peripheral parts) outside the semiconductor device 1.
The semiconductor chip 3 is flip-chip mounted on the wiring board 2, the heat radiating member 5 that covers the semiconductor chip 3 is mounted on the wiring board 2, and the heat radiating member is connected to the back surface 3 b of the semiconductor chip 3. The heat generated by the semiconductor chip 3 having a large amount of heat generation such as an element chip can be radiated to the wiring board 2 through the heat radiating member 5 to improve the heat radiation characteristics. Since the electronic component (passive component 4) is mounted, the thickness of the entire semiconductor device (RF power module) may be increased only by mounting the heat radiating member 5 on the wiring board 2. In this embodiment, the semiconductor chip 3 that generates a large amount of heat and needs to be improved in heat dissipation characteristics is covered, but its height is the height h of the semiconductor chip. 0 The heat dissipating member 5 is mounted (joined) on the wiring board 2 so as not to cover the higher electronic component (passive component 4a), and the electronic component (passive component 4a) higher than the semiconductor chip 3 is dissipated. The entire semiconductor device (RF power module) is thinned by mounting on the upper surface 2a of the wiring substrate 2 outside the member 5 and not mounting on the upper surface 2a of the wiring substrate 2 inside the heat dissipation member 5. Therefore, it is possible to improve both heat dissipation characteristics and reduce the thickness of the semiconductor device (RF power module).
FIG. 8 is a cross-sectional view conceptually showing a state in which the semiconductor device 1 is mounted on the mounting substrate 31 (secondary mounting).
The semiconductor device 1 having the above configuration is mounted on a mounting board (wiring board, external circuit board, motherboard) 31 as shown in FIG.
A mounting substrate electrode (terminal, electrode) 32 is formed on the upper surface of the mounting substrate 31, and the external connection terminal 12 b on the lower surface 2 b of the wiring substrate 2 of the semiconductor device 1 is soldered to the mounting substrate electrode 32 of the mounting substrate 31. These are joined (connected, soldered, mounted) via the joining material 33 and electrically connected. The reference potential supply terminal 12 c on the lower surface 2 b of the wiring substrate 2 of the semiconductor device 1 is joined (soldered) to the mounting substrate electrode 32 a for supplying the reference potential of the mounting substrate 31 via the joining material 33. A reference potential (for example, ground potential) is supplied to the reference potential supply terminal 12c.
Since the wiring substrate 2 of the semiconductor device 1 is mounted (bonded) to the mounting substrate 31 via the bonding material 33, the heat generated in the semiconductor chip 3 is connected to the wiring substrate 2 via the heat radiation member 5 and the bump electrode 17. And further conducted to the mounting substrate 31 to dissipate heat. In particular, since the reference potential supply terminal 12c on the lower surface 2b of the wiring substrate 2 of the semiconductor device 1 is joined (soldered) to the mounting substrate electrode 32a of the mounting substrate 31, the heat generated in the semiconductor chip 3 Heat is radiated from the back surface 3 b to the mounting substrate 31 through the bonding material 18, the heat radiation member 5, the bonding material 19, the board-side terminal 12 a, the conductor (conductor film) in the via hole 13, the reference potential supply terminal 12 c, and the bonding material 33. Further, heat can be radiated from the surface 3 a of the semiconductor chip 3 to the mounting substrate 31 through the bump electrode 17, the substrate-side terminal 12 a, the conductor (conductor film) in the via hole 13 a, the reference potential supply terminal 12 c and the bonding material 33. it can.
9 to 11 are cross-sectional views during a manufacturing process of the semiconductor device according to the embodiment of the present invention.
First, as shown in FIG. 9, the wiring board 2 is prepared. The wiring board 2 can be manufactured using, for example, a printing method, a sheet lamination method, a build-up method, or the like.
Next, as shown in FIG. 10, solder (bonding material 15) is printed or applied to a region (substrate-side terminal 12 a to which the passive component 4 is to be connected) where the passive component 4 on the upper surface 2 a of the wiring substrate 2 is to be mounted. To do. Then, the passive component 4 is mounted on the upper surface 2 a of the wiring substrate 2, and the semiconductor chip 3 is mounted on the upper surface 2 a of the wiring substrate 2. The passive component 4 may be mounted first on the upper surface 2a of the wiring board 2, or the semiconductor chip 3 may be mounted first. When the semiconductor chip 3 is mounted on the wiring substrate 2, the semiconductor chip 3 is provided on the front surface 3 a of the semiconductor chip 3 so that the back surface 3 b side of the semiconductor chip 3 faces upward and the front surface 3 a side faces the upper surface 2 a side of the wiring substrate 2. The solder bumps (bump electrodes 17) that are present are aligned so as to face the board-side terminals 12 a on the upper surface 2 a of the wiring board 2.
Then, by performing a solder reflow process or the like, the passive component 4 and the semiconductor chip 3 are joined to the wiring board 2 via solder (joining material 15) or solder bumps (bump electrodes 17) and electrically connected.
Next, as shown in FIG. 11, a silver paste (bonding material 19) is applied on the substrate-side terminal 12 a on which the heat radiating member 5 is to be mounted, and the silver paste (bonding material 18) is formed on the back surface 3 b of the semiconductor chip 3. ) Is applied. Then, the heat dissipation member 5 is mounted on the upper surface 2a of the wiring board 2 so as to cover the semiconductor chip 3 and the passive component 4b having a height lower than that of the semiconductor chip 3. At this time, the joining portion 5e of the heat dissipation member 5 is disposed on the substrate-side terminal 12a of the upper surface 2a of the wiring board 2 via the silver paste (joining material 19), and the inner surface 5c of the ceiling portion 5b of the semiconductor chip 3 is Then, it contacts the back surface 3b of the semiconductor chip 3 through the silver paste (bonding material 18). Then, the silver paste (bonding materials 18 and 19) is cured by heat treatment, the bonding portion 5e of the heat dissipation member 5 is bonded onto the substrate-side terminal 12a of the upper surface 2a of the wiring substrate 2, and the back surface 3b of the semiconductor chip 3 is bonded. The semiconductor chip 3 is joined to the inner surface 5c of the ceiling portion 5b. The bonding materials 18 and 19 can also be formed by solder. In this case, the solder (bonding material 15) and the solder bump (bump electrode 17) used for bonding the passive component 4 and the semiconductor chip 3 to the wiring board 2 are used. Solder having a melting point higher than the melting point is preferably used for solder (joining materials 18 and 19) for joining the heat radiation member 5 to the wiring substrate 2 and the back surface 3b of the semiconductor chip 3. As a result, during the solder reflow process (solder reflow process after mounting the heat dissipation member 5 on the wiring board 2) for joining the heat dissipation member 5 to the wiring board 2, the passive component 4 and the semiconductor chip 3 are wired. It is possible to prevent the solder (the bonding material 15 and the bump electrode 17) to be bonded to the substrate 2 from being melted.
In this way, the semiconductor device 1 as shown in FIGS. 1 to 3 can be manufactured. When manufacturing a plurality of semiconductor devices 1 from a single wiring board 2, after the heat dissipation member 5 is bonded to the wiring board 2, the wiring board 2 is divided at a predetermined position, and the semiconductor device 1 as each piece is obtained. Obtainable.
(Embodiment 2)
FIG. 12 is a cross-sectional view (side cross-sectional view) conceptually showing a state in which the semiconductor device 1a according to another embodiment of the present invention is mounted on the mounting substrate 31 (secondary mounting). This corresponds to FIG.
In the semiconductor device 1 a according to the present embodiment, a back electrode (for example, a back source electrode of MISFET) 3 c is formed on the back surface 3 b of the semiconductor chip 3, and the back electrode 3 c of the semiconductor chip 3 is radiated through the bonding material 18. It is connected (bonded or bonded) to the inner surface 5c of the member 5 for use. Since the other configuration of the semiconductor device 1a is almost the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted here.
In the semiconductor device 1a of the present embodiment, the back surface electrode 3c of the semiconductor chip 3 is connected (bonded or bonded) to the inner surface 5c of the heat dissipation member 5 via the bonding material 18, so that the bonding material 18 and the heat dissipation member 5 and the bonding material 19 are formed of a conductive material (for example, the heat dissipating member 5 is formed of a metal material, and the bonding materials 18 and 19 are formed of silver paste or solder), whereby the back surface of the semiconductor chip 3b. A reference potential (for example, ground potential) can be supplied to the electrode 3c via the heat dissipation member 5.
When the semiconductor device 1a is mounted on the mounting substrate 31 as shown in FIG. 12, the conductive bonding material 33 and the reference potential supply for the wiring substrate 2 are supplied from the mounting substrate electrode 32a for supplying the reference potential of the mounting substrate 31. The semiconductor chip 3 through the terminal 12c, the conductor (conductor film) in the via hole 13, the board-side terminal 12a of the wiring board 2, the conductive bonding material 19, the conductive heat radiation member 5, and the conductive bonding material 18. A reference potential (for example, ground potential) can be supplied to the back electrode 3c.
In the present embodiment, substantially the same effect as in the first embodiment can be obtained, and further, a reference potential (for example, ground potential) or the like is supplied to the back surface electrode 3c of the semiconductor chip 3 through the heat radiating member 5. be able to.
(Embodiment 3)
FIG. 13 is a top view (plan view) showing a conceptual structure of a semiconductor device 1b according to another embodiment of the present invention, and FIG. 14 is a conceptual sectional view (side sectional view) of the semiconductor device 1b. FIG. 15 is a top view (plan view) showing a state where the heat dissipating member 5 is seen through (omitted) in FIG. 13 corresponds to FIG. 1 of the first embodiment, FIG. 14 corresponds to FIG. 2 of the first embodiment, and FIG. 15 corresponds to FIG. 3 of the first embodiment.
A semiconductor device (for example, an RF power module or a high frequency power amplifier) 1b according to the present embodiment shown in FIGS. 13 to 15 has an arrangement of the semiconductor chip 3, the passive component 4, and the heat dissipation member 5 on the upper surface 2a of the wiring board 2a. Since the configuration is substantially the same as that of the semiconductor device 1 of the first embodiment except for the positional relationship, the description is omitted here except for the positional relationship of the semiconductor chip 3, the passive component 4, and the heat dissipating member 5. .
In the semiconductor device 1 of the first embodiment, the heat radiating member 5 covers the semiconductor chip 3 and the passive component 4b lower than the semiconductor chip 3 and does not cover the passive component 4a higher than the semiconductor chip 3. The inner surface 5c of the ceiling portion 5b of the heat dissipation member 5 mounted on the upper surface 2a of the substrate 2 is connected (bonded or bonded) to the back surface 3b of the semiconductor chip 3 by the bonding material 18, but in this embodiment, the heat dissipation The member 5 is mounted on the upper surface 2 a of the wiring substrate 2 so as to cover the semiconductor chip 3 and not the passive component 4, and the inner surface 5 c of the ceiling portion 5 b of the heat radiating member 5 is bonded to the rear surface 3 b of the semiconductor chip 3. They are connected (bonded and bonded) by the material 18.
That is, also in the present embodiment, as in the first embodiment, the height (topmost height) h is formed on the upper surface 2a of the wiring board 2a. 1 Is the height of the semiconductor chip 3 (the height at the top) h 0 Higher passive component 4a (height h of passive component 4a 1 > Height h of the semiconductor chip 3 0 The passive component 4a having a height higher than that of the semiconductor chip 3 is mounted on the upper surface 2a of the wiring board 2 outside the heat radiating member 5, and the wiring board inside the heat radiating member 5 is mounted. 2 is not mounted on the upper surface 2a. Furthermore, in the present embodiment, the passive component 4 mounted on the wiring board 2 has a height (top height) h. 2 Is the height of the semiconductor chip 3 (the height at the top) h 0 Passive component 4b (height h of passive component 4b) 1 <Height h of the semiconductor chip 3 0 ) Is mounted on the upper surface 2a of the wiring board 2 outside the heat radiating member 5, and the upper surface of the wiring board 2 inside the heat radiating member 5 is included. It is not mounted on 2a. Accordingly, in the present embodiment, the heat radiating member 5 covers only the semiconductor chip 3. Other configurations are almost the same as those in the first embodiment.
Although not shown, in the present embodiment as well, the upper surface 5d of the heat dissipation member 5 can be used as a marking area or a suction area, as in the first embodiment. Also in the present embodiment, similarly to the second embodiment, the back surface electrode 3c is provided on the back surface 3b of the semiconductor chip 3, and the back surface electrode 3c of the semiconductor chip 3 is electrically conductive through the conductive bonding material 18. It is also possible to connect (join or bond) the inner surface 5c of the heat dissipating member 5.
Also in this embodiment, substantially the same effect as in the first and second embodiments can be obtained. For example, a heat radiating member 5 is mounted on the upper surface of the wiring board 2 so as to cover the semiconductor chip 3 having a large calorific value, such as a semiconductor amplifying element chip, but not to cover other electronic components (passive components 4). Since the electronic component (passive component 4) other than the semiconductor chip 3 including the electronic component (passive component 4a) having a height higher than that of the chip 3 is mounted on the upper surface 2a of the wiring board 2 outside the heat radiating member 5, This is not the case where the heat dissipating member 5 is disposed on an electronic component (passive component 4a) having a height higher than that of the semiconductor chip 3. For this reason, the thickness (height) T of the entire semiconductor device 1 0 Can be made thinner (lower). Therefore, it becomes easier to use the semiconductor device 1b in an electronic device, for example, a mobile phone, which requires a thinner semiconductor device. In addition, since the heat generated by the semiconductor chip 3 having a large heat generation amount such as a semiconductor amplifying element chip can be radiated to the wiring board 2 through the heat radiating member 5, the heat radiation of the semiconductor chip 3 and the semiconductor device 1b on which the semiconductor chip 3 is mounted. The characteristics can be improved, and it is possible to improve both the heat dissipation characteristics and the thinning of the semiconductor device (RF power module). Further, since no electronic component (passive component 4) other than the semiconductor chip 3 is mounted inside the heat radiating member 5, even if the ceiling portion 5b of the heat radiating member 5 is flat and the inner surface 5c is flat, the heat radiating member. 5 and the passive component 4 do not contact. For this reason, the short circuit between the passive component 4 and the heat radiating member 5 can be prevented. Moreover, since the inner surface 5c of the ceiling part 5b of the heat radiating member 5 can be made flat and the heat radiating member 5 can have a relatively simple structure, the processing of the heat radiating member 5 is easy. For this reason, the manufacturing cost of the semiconductor device can be reduced. Moreover, the semiconductor chip 3 can be shielded against an electromagnetic field or static electricity by covering the semiconductor chip 3 with a heat radiating member 5 made of a metal material or the like.
In the present embodiment, the heat radiation member 5 is mounted on the upper surface 2a of the wiring board 2 so as to cover the semiconductor chip 3 but not the other electronic components (passive components 4). It becomes possible to reduce the dimension (planar dimension, area) of 5. For this reason, the member cost of the heat radiating member 5 can be reduced, which is advantageous in reducing the cost of the semiconductor device. Further, the degree of freedom of arrangement of the semiconductor chip 3 and the passive component 4 on the upper surface 2a of the wiring board 2 can be increased. In addition, the process of attaching (mounting) the heat dissipation member 2 to the wiring board 2 can be simplified. Further, when the heat radiation member 5 is mounted on the upper surface 2a of the wiring board 2 so as to cover not only the semiconductor chip 3 but also the passive component 4b lower than the semiconductor chip 3 as in the first embodiment, The area of the upper surface (outer surface) 5d of the ceiling portion 5b of the member 5 can be made relatively large, and it becomes easier to use the upper surface (outer surface) 5d of the heat radiating member 5 as a marking area or an adsorption area.
(Embodiment 4)
16 is a top view (plan view) showing a conceptual structure of a semiconductor device 1c according to another embodiment of the present invention, and FIG. 17 is a conceptual sectional view (side sectional view) of the semiconductor device 1c. It is. 16 corresponds to FIG. 1 of the first embodiment, and FIG. 17 corresponds to FIG. 2 of the first embodiment.
A semiconductor device (for example, an RF power module or a high frequency power amplifying device) 1c shown in FIGS. 16 and 17 is substantially the same as the semiconductor device 1 of the first embodiment except for the shape of the heat dissipation member 5. Therefore, the description of the configuration other than the heat radiating member 5 is omitted here.
In the semiconductor device 1 of the first embodiment, the heat dissipation member 5 is bonded to the upper surface 2a of the wiring board 2. However, in the semiconductor device 1c of the present embodiment, the heat dissipation member 5 is partially a wiring. It is joined to the upper surface 2 a of the substrate 2, and the other part extends to the outside of the upper surface 2 a of the wiring substrate 2 and extends on the side surface 2 c of the wiring substrate 2.
As shown in FIGS. 16 and 17, in the present embodiment, as in the first embodiment, the heat radiating member 5 includes a side wall 5a surrounding the periphery of the semiconductor chip 3 and an upper portion of the side wall 5a. The ceiling 5b is connected and covers the upper part of the semiconductor chip 3, and the inner surface 5c of the ceiling 5b is connected (bonded or bonded) to the back surface 3b of the semiconductor chip 3 by the bonding material 18. A part (one side) of the side wall part 5a of the heat radiating member 5 is provided with a joint part 5e similar to that of the first embodiment, and is joined to the board side terminal 12a of the upper surface 2a of the wiring board 2 by the joining material 19. However, the other part (one side) of the side wall portion 5 a of the heat radiating member 5 is located outside the upper surface 2 a of the wiring substrate 2 and extends on the side surface 2 c of the wiring substrate 2. A convex portion 5f is provided on a portion of the side wall portion 5a of the heat radiating member 5 that extends on the side surface 2c of the wiring substrate 2, and the convex portion 5f is formed on the side surface 2c of the wiring substrate 2 by a cut. It is fixed by being fitted in the notch (recessed part) 2d. Other configurations are substantially the same as those of the first embodiment.
Although not shown, in the present embodiment as well, the upper surface 5d of the heat dissipation member 5 can be used as a marking area or a suction area, as in the first embodiment. Similarly to the second embodiment, also in the present embodiment, the back surface electrode 3c is provided on the back surface 3b of the semiconductor chip 3, and the back surface electrode 3c of the semiconductor chip 3 is made conductive through the conductive bonding material 18. It is also possible to connect (join or bond) to the inner surface 5c of the heat radiating member 5. Further, similarly to the third embodiment, in this embodiment, the heat radiating member 5 may be mounted on the upper surface 2a of the wiring board 2 so as to cover the semiconductor chip 3 and not the passive component 4. it can.
FIG. 18 is a cross-sectional view conceptually showing a state in which the semiconductor device 1c of the present embodiment is mounted (secondary mounting) on the mounting substrate 31, and corresponds to FIG. 8 of the first embodiment.
When the semiconductor device 1c is mounted on the mounting board 31, the external connection terminals 12b on the lower surface 2b of the wiring board 2 apply a bonding material 33 such as solder to the mounting board electrode 32 of the mounting board 31 as shown in FIG. Are joined (connected, soldered, and mounted) and electrically connected. At this time, the portion of the side wall portion 5a of the heat radiating member 5 extending on the side surface 2c of the wiring board 2 and the mounting board electrode 32 of the mounting board 31 are bonded via a bonding material 33 such as solder ( Connection, solder connection).
Also in the present embodiment, substantially the same effect as in the first to third embodiments can be obtained. Further, in the present embodiment, the heat generated in the semiconductor chip 3 is conducted from the front surface 3 a side of the semiconductor chip 3 to the wiring substrate 2 through the bump electrodes 17 and is radiated to the mounting substrate 31, and the back surface of the semiconductor chip 3. From the side 3b, it is conducted to the wiring board 2 through the heat radiating member 5 and radiated to the mounting board 31, but a part of the heat radiating member 5 is directly attached to the mounting board 31 through the bonding material 33 such as solder. It is possible to promote heat dissipation from the back surface 3b side of the semiconductor chip 3 to the mounting substrate 31 through the heat dissipation member 5 by joining (connecting, soldering) to the mounting substrate electrode 32. For this reason, the heat dissipation characteristics of the semiconductor chip 3 and the semiconductor device 1c on which the semiconductor chip 3 is mounted can be further improved, and the performance of the semiconductor device 1 can be further improved. In addition, it is possible to dissipate more heat from the semiconductor chip 3 through the heat dissipation path via the heat dissipation member 5 than through the heat dissipation path through the bump 17, thereby suppressing thermal deterioration of the bump 17. The reliability of the semiconductor device can be improved.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
For example, in the above-described embodiment, the RF power module (high frequency power amplifier) has been described. However, the present invention is not limited to this, and includes a semiconductor chip made of active elements on a wiring board and passive elements. The present invention can be applied to various semiconductor devices mounted with passive components.
Among the embodiments of the invention disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
In a semiconductor device in which a semiconductor chip and a passive component are mounted on a wiring board, the semiconductor chip is flip-chip mounted, and a heat dissipation member that covers the semiconductor chip is mounted on the wiring board and connected to the back surface of the semiconductor chip. The passive component having a height higher than that of the chip is mounted on the wiring board outside the heat radiating member and not mounted on the wiring board inside the heat radiating member, so that the semiconductor device can be thinned. In addition, the heat dissipation characteristics of the semiconductor device can be improved.
The present invention also relates to a semiconductor device in which a semiconductor amplification element chip and other electronic components are mounted on a wiring board, wherein the semiconductor amplification element chip is flip-chip mounted, and a heat radiating member that covers the semiconductor amplification element chip is wired. Mounted on a substrate and connected to the back surface of the semiconductor amplifying element chip, and an electronic component having a height higher than that of the semiconductor amplifying element chip is mounted on the wiring board outside the heat radiating member and placed on the wiring board inside the heat radiating member. By not mounting on the semiconductor device, the semiconductor device can be thinned. In addition, the heat dissipation characteristics of the semiconductor device can be improved.

本発明は、例えば携帯電話のような移動体通信機器などに用いられる半導体装置のように、薄型化が要求される半導体装置として有用である。  The present invention is useful as a semiconductor device that is required to be thin, such as a semiconductor device used in a mobile communication device such as a mobile phone.

Claims (20)

配線基板と、
能動素子からなり、前記配線基板の第１主面上にフリップチップ実装された半導体チップと、
前記半導体チップを覆うように前記配線基板に搭載され、その内面に前記半導体チップの裏面が接続された放熱用部材と、
前記放熱用部材の外部の前記配線基板の前記第１主面上に搭載され、前記半導体チップよりも高さが高い受動部品と、
を有し、
前記放熱用部材の内部の前記配線基板の前記第１主面上には、前記半導体チップよりも高さが高い受動部品は搭載されていないことを特徴とする半導体装置。A wiring board;
A semiconductor chip comprising an active element and flip-chip mounted on the first main surface of the wiring board;
A heat dissipating member mounted on the wiring board so as to cover the semiconductor chip and having the inner surface connected to the back surface of the semiconductor chip;
A passive component mounted on the first main surface of the wiring board outside the heat dissipation member and having a height higher than that of the semiconductor chip;
Have
A passive component having a height higher than that of the semiconductor chip is not mounted on the first main surface of the wiring board inside the heat dissipation member. 請求項１記載の半導体装置において、
前記放熱用部材の内部の前記配線基板の前記第１主面上に搭載され、前記半導体チップよりも高さが低い受動部品を更に有することを特徴とする半導体装置。The semiconductor device according to claim 1,
A semiconductor device further comprising a passive component mounted on the first main surface of the wiring board inside the heat dissipation member and having a height lower than that of the semiconductor chip. 請求項１記載の半導体装置において、
前記放熱用部材の外部の前記配線基板の前記第１主面上に搭載され、前記半導体チップよりも高さが低い受動部品を更に有することを特徴とする半導体装置。The semiconductor device according to claim 1,
A semiconductor device further comprising a passive component mounted on the first main surface of the wiring board outside the heat dissipation member and having a height lower than that of the semiconductor chip. 請求項１記載の半導体装置において、
前記放熱用部材の内部の前記配線基板の前記第１主面上には、受動部品は搭載されていないことを特徴とする半導体装置。The semiconductor device according to claim 1,
A passive device is not mounted on the first main surface of the wiring board inside the heat dissipation member. 請求項１記載の半導体装置において、
前記配線基板の前記第１主面上に搭載された受動部品のうちの最も高さが高い受動部品の高さと比べて、前記放熱用部材の高さが同じか低いことを特徴とする半導体装置。The semiconductor device according to claim 1,
The heat radiation member has a height equal to or lower than that of the passive component having the highest height among the passive components mounted on the first main surface of the wiring board. . 請求項１記載の半導体装置において、
前記放熱用部材は、金属材料からなることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the heat dissipation member is made of a metal material. 請求項１記載の半導体装置において、
前記放熱用部材は、金属キャップであることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the heat dissipation member is a metal cap. 請求項１記載の半導体装置において、
前記放熱用部材は、銅を主成分とする材料からなることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the heat dissipating member is made of a material mainly composed of copper. 請求項１記載の半導体装置において、
前記半導体チップの裏面に裏面電極が形成されており、前記裏面電極が前記放熱用部材の内面に接続されていることを特徴とする半導体装置。The semiconductor device according to claim 1,
A semiconductor device, wherein a back electrode is formed on a back surface of the semiconductor chip, and the back electrode is connected to an inner surface of the heat dissipation member. 請求項９記載の半導体装置において、
前記放熱用部材は導電体材料からなり、
前記半導体チップの前記裏面電極と前記放熱用部材とは、導電性の接合材を介して接続されていることを特徴とする半導体装置。The semiconductor device according to claim 9.
The heat dissipation member is made of a conductive material,
The semiconductor device, wherein the back electrode of the semiconductor chip and the heat dissipation member are connected via a conductive bonding material. 請求項１記載の半導体装置において、
前記受動部品はチップ部品であることを特徴とする半導体装置。The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the passive component is a chip component. 請求項１記載の半導体装置において、
前記放熱用部材の上面には、マーキングが行われていることを特徴とする半導体装置。The semiconductor device according to claim 1,
A semiconductor device, wherein marking is performed on an upper surface of the heat radiating member. 請求項１記載の半導体装置において、
前記放熱用部材は、前記配線基板の前記第１主面の導体部に接合されていることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the heat radiating member is bonded to a conductor portion of the first main surface of the wiring board. 請求項１記載の半導体装置において、
前記放熱用部材の一部は、前記配線基板の側面上に延在していることを特徴とする半導体装置。The semiconductor device according to claim 1,
A part of the heat radiating member extends on a side surface of the wiring board. 請求項１記載の半導体装置において、
前記配線基板を実装する他の配線基板を更に有し、
前記放熱用部材は前記他の配線基板に電気的に接続されていることを特徴とする半導体装置。The semiconductor device according to claim 1,
Further comprising another wiring board for mounting the wiring board,
The semiconductor device according to claim 1, wherein the heat dissipating member is electrically connected to the other wiring board. 請求項１記載の半導体装置において、
前記半導体チップは半導体増幅素子チップであることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device is a semiconductor amplifying element chip. 請求項１記載の半導体装置において、
前記半導体チップの下方の前記配線基板にはサーマルビアが形成されていることを特徴とする半導体装置。The semiconductor device according to claim 1,
A semiconductor device, wherein a thermal via is formed in the wiring substrate below the semiconductor chip. 請求項１記載の半導体装置において、
前記半導体装置は携帯電話に搭載される電力増幅装置であることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device is a power amplifying device mounted on a mobile phone. 配線基板と、
前記配線基板の第１主面上にフリップチップ実装された半導体増幅素子チップと、
前記半導体増幅素子チップを覆うように前記配線基板に搭載され、その内面に前記半導体増幅素子チップの裏面が接続された放熱用部材と、
前記放熱用部材の外部の前記配線基板の前記第１主面上に搭載され、前記半導体増幅素子チップよりも高さが高い電子部品と、
を有し、
前記放熱用部材の内部の前記配線基板の前記第１主面上には、前記半導体増幅素子チップよりも高さが高い電子部品は搭載されていないことを特徴とする半導体装置。A wiring board;
A semiconductor amplifying element chip flip-chip mounted on the first main surface of the wiring board;
A heat dissipating member mounted on the wiring board so as to cover the semiconductor amplifying element chip and having the inner surface connected to the back surface of the semiconductor amplifying element chip,
An electronic component mounted on the first main surface of the wiring board outside the heat dissipation member and having a height higher than that of the semiconductor amplification element chip;
Have
An electronic component having a height higher than that of the semiconductor amplifying element chip is not mounted on the first main surface of the wiring board inside the heat dissipation member. 請求項１記載の半導体装置において、
前記電子部品は受動部品であることを特徴とする半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the electronic component is a passive component.
JP2006527634A 2004-06-29 2004-06-29 Semiconductor device Pending JPWO2006001087A1 (en)

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