JP2003197825A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2003197825A
JP2003197825A JP2001393042A JP2001393042A JP2003197825A JP 2003197825 A JP2003197825 A JP 2003197825A JP 2001393042 A JP2001393042 A JP 2001393042A JP 2001393042 A JP2001393042 A JP 2001393042A JP 2003197825 A JP2003197825 A JP 2003197825A
Authority
JP
Japan
Prior art keywords
semiconductor device
oxide particles
composite material
wiring
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001393042A
Other languages
Japanese (ja)
Inventor
Toshiaki Morita
俊章 守田
Yasutoshi Kurihara
保敏 栗原
Hironori Kodama
弘則 児玉
Mamoru Iizuka
守 飯塚
Kenji Koyama
賢治 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001393042A priority Critical patent/JP2003197825A/en
Publication of JP2003197825A publication Critical patent/JP2003197825A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Ceramic Products (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package in which mechanical and physical properties such as a coefficient of thermal expansion or heat conductivity do not change after a package is assembled, and which does not impair reliability for a long term; and its manufacturing process which realizes a simplification and a reduction in void of a solder joining part. <P>SOLUTION: A semiconductor device has a composite material including oxide particles, the oxide particles exist also in an area within 5 μm from an uppermost surface of the composite material, and a volume of the oxide particles does not shrink more than that before the semiconductor device is assembled. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は複合材料を放熱板，
配線、及びリードフレームに適用した半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device applied to wiring and a lead frame.

【０００２】[0002]

【従来の技術】電子回路を一つの半導体素子上に集積さ
せた集積回路（ＩＣ）は、その機能に応じてメモリー，
ロジック，マイクロプロセッサ等に分類される。これら
の半導体素子の集積度や演算速度は年々増加し、それに
伴い発熱量も増大している。これらの半導体素子は、外
気を遮断して故障や劣化を防止するためパッケージング
されている。半導体パッケージは、半導体素子がセラミ
ック基板にダイボンディングされ密封されているセラミ
ックパッケージ、あるいは樹脂で封止されているプラス
チックパッケージが多い。また、高信頼性，高速化に対
応するために、複数個の半導体装置を一つの基板上に搭
載して一つのモジュール化したマルチチップモジュール
（ＭＣＭ）も製造されている。2. Description of the Related Art An integrated circuit (IC) in which electronic circuits are integrated on one semiconductor element is a memory,
Classified into logic and microprocessors. The degree of integration and the operation speed of these semiconductor elements are increasing year by year, and the amount of heat generation is also increasing accordingly. These semiconductor elements are packaged in order to block outside air and prevent failures and deterioration. Many semiconductor packages are a ceramic package in which a semiconductor element is die-bonded to a ceramic substrate and sealed, or a plastic package in which a resin is sealed. Further, in order to cope with high reliability and high speed, a multi-chip module (MCM) in which a plurality of semiconductor devices are mounted on one substrate to make one module is also manufactured.

【０００３】プラスチックパッケージは、リードフレー
ムと半導体素子の端子とが金属細線（ボンディングワイ
ヤ）により接続され、これを樹脂で封止する構造になっ
ている。近年、半導体素子の高集積，高機能化に伴って
半導体素子の発熱量は増大しており、このためリードフ
レームの熱放散性を高める、あるいは熱放散のための放
熱板をパッケージに搭載する必要性が生じている。熱放
散のためには、熱伝導率が大きい銅系の材料が使用され
ているが、Ｓｉとの熱膨張率差による不具合が発生して
いる。A plastic package has a structure in which a lead frame and a terminal of a semiconductor element are connected by a fine metal wire (bonding wire), and this is sealed with resin. In recent years, the amount of heat generated by semiconductor elements has increased with the high integration and high functionality of semiconductor elements. Therefore, it is necessary to enhance the heat dissipation of the lead frame or to mount a heat dissipation plate for heat dissipation in the package. Sex has occurred. For heat dissipation, a copper-based material having a large thermal conductivity is used, but a problem occurs due to a difference in coefficient of thermal expansion with Si.

【０００４】セラミックパッケージは配線が形成された
セラミック基板上に半導体素子が搭載され、金属やセラ
ミックのキャップで密封する構造である。さらに、セラ
ミック基板には銅−モリブデンや銅−タングステンの複
合材、あるいは酸化物粒子を分散させた金属板（例えば
銅−亜酸化銅）などが接合され、放熱板として用いられ
ているけれども、それぞれの材料において熱膨張率や熱
伝導率などの機械的，物理的性質がパッケージ組立て後
も変化せず、長期信頼性を損なわないことが要求されて
いる。A ceramic package has a structure in which a semiconductor element is mounted on a ceramic substrate on which wiring is formed and sealed with a metal or ceramic cap. Further, a composite material of copper-molybdenum or copper-tungsten, or a metal plate in which oxide particles are dispersed (for example, copper-cuprous oxide) is bonded to the ceramic substrate and is used as a heat dissipation plate. It is required that the mechanical and physical properties such as the coefficient of thermal expansion and the thermal conductivity of these materials do not change even after the package is assembled and the long-term reliability is not impaired.

【０００５】一方、パワー半導体装置の一つである非絶
縁型半導体装置において、半導体素子を固定する部材は
半導体装置の電極の一つでもある。例えば、パワートラ
ンジスタを固定部材（例えば銅−亜酸化銅製複合材料）
上にＳｎ−Ｐｂ系ろう材を用いて搭載した装置では、固
定部材（ベース材）はパワートランジスタのコレクタ電
極でもある。実稼動時には数アンペア以上のコレクタ電
流が流れ、このときトランジスタチップは発熱する。こ
の発熱に起因する特性の不安定性や寿命の低下を避ける
ためは、ベース材は熱放散に優れ、かつろう付け部の信
頼性が確保できていなければならない。ろう付け部の信
頼性確保には、半導体素子と固定部材の熱膨張率の整合
が必要になってくる。On the other hand, in a non-insulating semiconductor device which is one of power semiconductor devices, a member for fixing a semiconductor element is also one of electrodes of the semiconductor device. For example, a power transistor is used as a fixing member (for example, a copper-cuprous oxide composite material).
In the device mounted with Sn—Pb type brazing material on the top, the fixing member (base material) is also the collector electrode of the power transistor. During actual operation, a collector current of several amperes or more flows, and at this time, the transistor chip generates heat. In order to avoid the instability of the characteristics and the shortening of the life due to this heat generation, the base material must have excellent heat dissipation and ensure the reliability of the brazed portion. In order to secure the reliability of the brazed portion, it is necessary to match the coefficient of thermal expansion between the semiconductor element and the fixing member.

【０００６】絶縁型半導体装置においても、半導体素子
を安全かつ安定に動作させるためには、半導体装置の動
作時に発生する熱をパッケージの外へ効率良く放散させ
る必要がある。この熱放散は、通常、発熱源である半導
体素子からこれと接着された各部材を通じて気中へ熱伝
達させることで達成される。絶縁型半導体装置ではこの
熱伝達経路中に、絶縁体，半導体素子を接着する部分等
に用いられた接着剤層、及び金属支持部材を含む。Also in the insulating semiconductor device, in order to operate the semiconductor element safely and stably, it is necessary to efficiently dissipate the heat generated during the operation of the semiconductor device to the outside of the package. This heat dissipation is usually achieved by transferring heat from a semiconductor element, which is a heat source, to the air through each member bonded thereto. In the insulated semiconductor device, the heat transfer path includes an insulator, an adhesive layer used for a portion to which the semiconductor element is bonded, and a metal supporting member.

【０００７】上記の条件をクリアするための従来技術と
して、特開平８−１１５０３号公報には、Ｓｉチップを
Ｃｕ張ＡｌＮ基板の搭載したアッセンブリを、Ｍｏから
なる支持部材にはんだ材によりろう付け一体化した半導
体電流制御装置が開示されている。本従来技術では、Ｃ
ｕ張りＡｌＮ基板はこれと熱膨張率略近似したＭｏ支持
部材（５.１ppm／℃）にはんだ付け搭載されているた
め、これら部材間のはんだ接合部は優れた信頼性を有
し、放熱性劣化の防止に有効である。As a conventional technique for satisfying the above conditions, Japanese Patent Laid-Open No. 8-111503 discloses an assembly in which a Si chip and a Cu-clad AlN substrate are mounted on a supporting member made of Mo by soldering with a solder material. There is disclosed a semiconductor current control device which is realized. In this conventional technique, C
Since the u-clad AlN substrate is mounted by soldering on a Mo support member (5.1 ppm / ° C) whose coefficient of thermal expansion is approximately similar to this, the solder joint between these members has excellent reliability and heat dissipation. It is effective in preventing deterioration.

【０００８】特公平７−２６１７４号公報には、サイリ
スタチップをアルミナ基板に搭載したアッセンブリを、
Ａｌ、またはＡｌ合金にＳｉＣセラミックス粉末を分散
させた複合材からなる支持部材に搭載した半導体モジュ
ール装置が開示されている。本従来技術では、アルミナ
基板（７.５ppm／℃）はこれと熱膨張率が略近似したＡ
ｌ／ＳｉＣ複合材支持部材(２〜１３ppm／℃）に搭載さ
れているため、これら部材間の接合部は優れた信頼性を
有し、放熱性劣化の防止に有効である。Japanese Patent Publication No. 26174/1995 discloses an assembly in which a thyristor chip is mounted on an alumina substrate.
A semiconductor module device mounted on a supporting member made of a composite material in which SiC ceramic powder is dispersed in Al or Al alloy is disclosed. In this conventional technique, the alumina substrate (7.5 ppm / ° C.) has a coefficient of thermal expansion approximately A
Since it is mounted on the 1 / SiC composite material supporting member (2 to 13 ppm / ° C.), the joint portion between these members has excellent reliability and is effective in preventing deterioration of heat dissipation.

【０００９】特開２０００−２６５２２７号公報には、
Ｃｕと第一酸化銅(Ｃｕ2Ｏ）粒子との複合材料(Ｃｕ／
Ｃｕ2Ｏ）を支持板に適用し、セラミック板との熱膨張
係数の差を少なくした構造が開示されている。この複合
材料は銅中に分散させる第一酸化銅の割合を増加させる
につれて、熱膨張係数が次第に小さくなる材料である。
例えば、銅中に第一酸化銅を５０重量％分散させると、
その熱膨張係数は約１０ppm／℃ となる。結果として、
セラミックス板と支持板接合部の熱応力を低減させるこ
とができるとしている。Japanese Patent Laid-Open No. 2000-265227 discloses that
Composite material of Cu and cuprous oxide (Cu 2 O) particles (Cu /
Cu 2 O) is applied to the support plate to reduce the difference in coefficient of thermal expansion from the ceramic plate. This composite material is a material whose coefficient of thermal expansion gradually decreases as the proportion of cuprous oxide dispersed in copper increases.
For example, when 50% by weight of cuprous oxide is dispersed in copper,
Its thermal expansion coefficient is about 10 ppm / ° C. as a result,
It is said that it is possible to reduce the thermal stress at the joint between the ceramic plate and the support plate.

【００１０】以上に挙げた半導体装置は、全て、はんだ
付け面の酸化物や有機物などのはんだ付け性を劣化させ
る因子を排除するため、還元雰囲気（例えば水素雰囲
気）中ではんだ付けを行う工程を経ていた。In order to eliminate the factors that deteriorate the solderability such as oxides and organic substances on the soldering surface, all of the above-mentioned semiconductor devices have a step of performing soldering in a reducing atmosphere (for example, hydrogen atmosphere). Had passed.

【００１１】[0011]

【発明が解決しようとする課題】以上に様に、半導体素
子を搭載した半導体装置は発生する熱を外部に放散する
ための熱伝導性に優れた放熱板が必要となる。放熱板
は、直接あるいは絶縁層を介して半導体素子と接合され
るため、熱伝導性だけでなく、熱膨張の点でも半導体素
子との整合性が要求される。同時に、半導体装置製作前
後でそれらの物性値が変化してはならない。特にベース
板や配線材が酸化物粒子で構成された複合材で構成され
るとき、従来の還元性雰囲気中のはんだ付け工程を経る
と還元作用により酸化物粒子が変質する。この結果、複
合材の熱膨張率，熱伝導率等の物性値が変化し、はんだ
付部の信頼性劣化，複合材の酸化腐食等の長期信頼性を
阻害する現象が生じることがあった。As described above, the semiconductor device having the semiconductor element mounted thereon requires the heat dissipation plate having excellent thermal conductivity to dissipate the generated heat to the outside. Since the heat dissipation plate is bonded to the semiconductor element directly or through the insulating layer, not only the thermal conductivity but also the consistency with the semiconductor element is required in terms of thermal expansion. At the same time, their physical properties should not change before and after the fabrication of semiconductor devices. In particular, when the base plate and the wiring material are composed of a composite material composed of oxide particles, the oxide particles are deteriorated by the reducing action after a conventional soldering process in a reducing atmosphere. As a result, physical properties such as thermal expansion coefficient and thermal conductivity of the composite material may change, which may cause a phenomenon such as deterioration of reliability of soldered portion and oxidative corrosion of the composite material, which impairs long-term reliability.

【００１２】このように、従来の半導体装置は、その生
産段階で信頼性劣化してしまう大きな問題点を抱えてい
た。As described above, the conventional semiconductor device has a serious problem that reliability is deteriorated at the production stage.

【００１３】本発明の目的は、パッケージ組立て後の熱
膨張率や熱伝導率などの機械的，物理的性質の変化量が
少なく、長期信頼性に優れた半導体パッケージと、その
製造プロセスを提供することにある。さらに、より簡略
化され、かつはんだ接合部の低ボイド化を実現した製造
プロセスも提供する。An object of the present invention is to provide a semiconductor package which has a small amount of change in mechanical and physical properties such as thermal expansion coefficient and thermal conductivity after assembly of the package and is excellent in long-term reliability, and a manufacturing process thereof. Especially. Further, it also provides a manufacturing process which is more simplified and realizes a lower void in the solder joint.

【００１４】[0014]

【課題を解決するための手段】本発明は、酸化物粒子を
含有した複合材料を有する半導体装置であって、かつ前
記酸化物粒子が前記複合材料の母材の最表面から５μｍ
以内の領域にも存在することを特徴とした半導体装置と
することにより達成される。The present invention is a semiconductor device having a composite material containing oxide particles, wherein the oxide particles are 5 μm from the outermost surface of the base material of the composite material.
This is achieved by providing a semiconductor device characterized in that the semiconductor device also exists in the inside region.

【００１５】本発明は、半導体素子，配線が形成された
絶縁板、及び支持板が順次積層された半導体装置であっ
て、前記絶縁板上に形成した配線と前記支持板の少なく
とも一方が酸化物粒子を含有した複合材料で形成され、
かつ前記酸化物粒子が前記複合材料の母材の最表面から
５μｍ以内にも存在することを特徴とした半導体装置と
することにより達成される。The present invention is a semiconductor device in which a semiconductor element, an insulating plate having wiring formed thereon, and a supporting plate are sequentially laminated, wherein at least one of the wiring formed on the insulating plate and the supporting plate is an oxide. Formed of a composite material containing particles,
In addition, it is achieved by providing a semiconductor device in which the oxide particles are present within 5 μm from the outermost surface of the base material of the composite material.

【００１６】本発明は、前記半導体素子と前記配線また
は前記絶縁板と前記支持板がペーストはんだ材を用いて
接合されていることを特徴とした半導体装置とすること
により達成される。The present invention can be achieved by providing a semiconductor device characterized in that the semiconductor element and the wiring or the insulating plate and the support plate are joined together by using a paste solder material.

【００１７】本発明は、前記半導体素子と前記配線また
は前記絶縁板と前記支持板が、Ｓｎ，Ａｇ，Ａｕ，Ａ
ｌ，Ｃｕ，Ｎｉ，Ｇｅ，Ｇａ，Ｉｎ，Ｐ，Ｂｉ、及びＺ
ｎの群から選択された少なくとも１元素を含む少なくと
も１種類のろう材で接合されていることを特徴とした半
導体装置とすることにより達成される。In the present invention, the semiconductor element and the wiring or the insulating plate and the support plate are made of Sn, Ag, Au, A.
l, Cu, Ni, Ge, Ga, In, P, Bi, and Z
This is achieved by providing a semiconductor device characterized by being bonded with at least one kind of brazing material containing at least one element selected from the group of n.

【００１８】また、前記酸化物粒子を含有した複合材と
しては、銅を母材とし、酸化銅粒子が分散された複合材
を用いることが好ましい。As the composite material containing the oxide particles, it is preferable to use a composite material in which copper is a base material and copper oxide particles are dispersed.

【００１９】本発明は、前記配線及び支持板の表面にＮ
ｉ，Ｓｎ，Ａｇ，Ａｕ，Ｐｔ，Ｐｄ，Ｚｎ、及びＣｕの
群から選択された少なくとも１種類の金属皮膜が施され
ていることを特徴とする半導体装置とすることにより達
成される。In the present invention, the surface of the wiring and the supporting plate is N
This is achieved by providing a semiconductor device characterized by being coated with at least one kind of metal film selected from the group consisting of i, Sn, Ag, Au, Pt, Pd, Zn, and Cu.

【００２０】本発明は、前記半導体素子，前記配線が形
成した絶縁板、及び前記支持板を順次積層した積層体を
加熱し、これらをＳｎを含む１種類のペースト状ろう材
を用いて真空雰囲気あるいは不活性雰囲気中で一括接合
したことを特徴とする半導体装置とすること、及びその
半導体製造方法を適用することにより達成される。According to the present invention, a laminated body in which the semiconductor element, the insulating plate having the wiring formed thereon, and the support plate are sequentially laminated is heated, and these are used in a vacuum atmosphere using one kind of paste-like brazing material containing Sn. Alternatively, it can be achieved by providing a semiconductor device characterized by being collectively bonded in an inert atmosphere, and by applying the semiconductor manufacturing method thereof.

【００２１】本発明は、前記絶縁板は、酸化アルミニウ
ム，窒化アルミニウム，窒化ホウ素、窒化ケイ素、及び
炭化ケイ素のいずれかよりなることを特徴とする半導体
装置とすることにより達成される。The present invention is achieved by providing a semiconductor device in which the insulating plate is made of any one of aluminum oxide, aluminum nitride, boron nitride, silicon nitride, and silicon carbide.

【００２２】本発明は、半導体素子，放熱板，配線，絶
縁材、及び支持板が順次積層された半導体装置であっ
て、前記放熱板、或いは配線が酸化物粒子を含有した複
合材料で形成され、かつ前記酸化物粒子が前記複合材料
の母材の最表面から５μｍ以内にも存在し、かつ前記複
合材料の母材の最表面から５μｍ以内の領域に存在する
酸化物粒子が積層実装前に比べて体積収縮していないこ
とを特徴とした半導体装置とすることにより達成され
る。The present invention is a semiconductor device in which a semiconductor element, a heat dissipation plate, a wiring, an insulating material, and a support plate are sequentially laminated, and the heat dissipation plate or the wiring is formed of a composite material containing oxide particles. Before the stacked mounting, the oxide particles are present within 5 μm from the outermost surface of the base material of the composite material, and are present in a region within 5 μm from the outermost surface of the base material of the composite material. This is achieved by providing a semiconductor device characterized by not having volume contraction.

【００２３】本発明は、前記半導体素子，前記配線が形
成された絶縁板、及び前記支持板をＳｎを含む１種類の
ペースト状ろう材を介して順次積層した後、真空雰囲気
あるいは不活性雰囲気中で加熱し一括接合する工程を有
することを特徴とする半導体装置の製造方法とすること
により達成される。In the present invention, the semiconductor element, the insulating plate on which the wiring is formed, and the supporting plate are sequentially laminated with one type of paste-like brazing material containing Sn, and then, in a vacuum atmosphere or an inert atmosphere. It is achieved by providing a method of manufacturing a semiconductor device, which comprises a step of heating and joining at once.

【００２４】本発明は、前記半導体素子，前記放熱板，
前記配線，前記絶縁材、及び前記支持板を順次積層した
積層体を加熱し、前記半導体素子と前記放熱板の間、或
いは前記放熱板と前記配線の間はＳｎを含む１種類のペ
ースト状ろう材を用いて真空雰囲気あるいは不活性雰囲
気中で一括接合したことを特徴とする半導体装置とする
ことにより達成され、その半導体製造方法を適用するこ
とにより達成される。According to the present invention, the semiconductor element, the heat sink,
A laminated body in which the wiring, the insulating material, and the support plate are sequentially laminated is heated, and one kind of paste brazing material containing Sn is provided between the semiconductor element and the heat dissipation plate or between the heat dissipation plate and the wiring. This is achieved by providing a semiconductor device characterized by being collectively bonded in a vacuum atmosphere or an inert atmosphere, and by applying the semiconductor manufacturing method.

【００２５】本発明は、前記半導体素子と前記放熱板の
間、或いは前記放熱板と前記配線の間はＳｎ，Ａｇ，Ａ
ｕ，Ａｌ，Ｃｕ，Ｎｉ，Ｇｅ，Ｇａ，Ｉｎ，Ｐ，Ｂｉ、
及びＺｎの群から選択された少なくとも１元素を含む少
なくとも１種類のろう材で構成されていることを特徴と
した半導体装置とすることにより達成される。According to the present invention, Sn, Ag, A is provided between the semiconductor element and the heat sink or between the heat sink and the wiring.
u, Al, Cu, Ni, Ge, Ga, In, P, Bi,
It is achieved by providing a semiconductor device characterized by comprising at least one kind of brazing material containing at least one element selected from the group consisting of Zn and Zn.

【００２６】また、前記酸化物粒子を含有した複合材と
しては、銅を母材とし、酸化銅粒子が分散された複合材
を用いることが好ましい。As the composite material containing the oxide particles, it is preferable to use a composite material in which copper is a base material and copper oxide particles are dispersed.

【００２７】本発明は、前記放熱板、あるいは前記配線
の少なくとも一方の表面には、Ｎｉ，Ｓｎ，Ａｇ，Ａ
ｕ，Ｐｔ，Ｐｄ，Ｚｎ、及びＣｕの群から選択された少
なくとも１種類の金属皮膜が施されていることを特徴と
する半導体装置とすることにより達成される。According to the present invention, Ni, Sn, Ag, A is formed on the surface of at least one of the heat dissipation plate and the wiring.
It is achieved by providing a semiconductor device characterized in that at least one kind of metal film selected from the group of u, Pt, Pd, Zn, and Cu is applied.

【００２８】本発明は、前記絶縁板は有機系材料により
なることを特徴とする半導体装置とすることにより達成
される。The present invention is achieved by providing a semiconductor device in which the insulating plate is made of an organic material.

【００２９】本発明は、前記支持板は、アルミニウム、
或いはアルミニウム合金で形成されることを特徴とした
半導体装置とすることにより達成される。In the present invention, the support plate is made of aluminum,
Alternatively, it is achieved by providing a semiconductor device characterized by being formed of an aluminum alloy.

【００３０】本発明は、半導体素子，放熱板，配線が形
成した支持絶縁板が順次積層された半導体装置であっ
て、前記放熱板が酸化物粒子を含有した複合材料で形成
され、かつ前記酸化物粒子が前記複合材料の母材の最表
面から５μｍ以内にも存在することを特徴とした半導体
装置とすることにより達成される。The present invention is a semiconductor device in which a semiconductor element, a heat radiating plate, and a supporting insulating plate on which wiring is formed are sequentially laminated, wherein the heat radiating plate is formed of a composite material containing oxide particles, and the oxidation is performed. This can be achieved by providing a semiconductor device in which the material particles are present within 5 μm from the outermost surface of the base material of the composite material.

【００３１】本発明は、前記半導体素子，前記放熱板，
前記配線が形成した支持絶縁板を順次積層した積層体を
加熱し、前記半導体素子と前記放熱板の間、或いは前記
放熱板と配線が形成した支持絶縁板の間はＳｎ，Ａｇ，
Ａｕ，Ａｌ，Ｃｕ，Ｎｉ，Ｇｅ，Ｇａ，Ｉｎ，Ｐ，Ｂ
ｉ、及びＺｎの群から選択された少なくとも１元素を含
む少なくとも１種類のろう材を用いて真空雰囲気あるい
は不活性雰囲気中で一括接合したことを特徴とする半導
体装置とすることにより達成され、その半導体製造方法
を適用することにより達成される。According to the present invention, the semiconductor element, the heat sink,
The stacked body obtained by sequentially stacking the supporting insulating plates having the wiring formed thereon is heated to cause Sn, Ag, and a gap between the semiconductor element and the heat radiating plate, or between the heat radiating plate and the supporting insulating plate having the wiring.
Au, Al, Cu, Ni, Ge, Ga, In, P, B
It is achieved by providing a semiconductor device characterized in that at least one brazing material containing at least one element selected from the group consisting of i and Zn is collectively bonded in a vacuum atmosphere or an inert atmosphere. This is achieved by applying a semiconductor manufacturing method.

【００３２】また、前記放熱板としては、銅を母材と
し、酸化銅粒子が分散された複合材を用いることが好ま
しい。As the heat dissipation plate, it is preferable to use a composite material in which copper is a base material and copper oxide particles are dispersed.

【００３３】本発明は、前記放熱板の表面には、Ｎｉ，
Ｓｎ，Ａｇ，Ａｕ，Ｐｔ，Ｐｄ，Ｚｎ、及びＣｕの群か
ら選択された少なくとも１種類の金属皮膜が施されてい
ることを特徴とする半導体装置とすることにより達成さ
れる。According to the present invention, Ni,
This is achieved by providing a semiconductor device characterized in that at least one kind of metal film selected from the group consisting of Sn, Ag, Au, Pt, Pd, Zn, and Cu is applied.

【００３４】また、前記配線が形成された支持絶縁板
は、ガラスセラミック系材料で構成されていることが好
ましい。The supporting insulating plate on which the wiring is formed is preferably made of a glass ceramic material.

【００３５】本発明は、半導体素子がリードフレーム上
に積層され、前記半導体素子と前記リードフレームは金
属細線で結線された半導体装置であって、前記リードフ
レームは酸化物粒子を含有した複合材料で形成され、か
つ前記酸化物粒子が前記複合材料の母材の最表面から５
μｍ以内にも存在することを特徴とした半導体装置とす
ることにより達成される。The present invention is a semiconductor device in which a semiconductor element is laminated on a lead frame, and the semiconductor element and the lead frame are connected by a fine metal wire, and the lead frame is a composite material containing oxide particles. And the oxide particles are formed from the outermost surface of the base material of the composite material.
This can be achieved by providing a semiconductor device characterized in that it exists within μm.

【００３６】本発明は、前記半導体素子と前記リードフ
レームを積層した積層体を、前記半導体素子と前記リー
ドフレームの間はＳｎ，Ａｇ，Ａｕ，Ａｌ，Ｃｕ，Ｎ
ｉ，Ｇｅ，Ｇａ，Ｉｎ，Ｐ，Ｂｉ、及びＺｎの群から選
択された少なくとも１元素を含む少なくとも１種類のろ
う材を用いて真空雰囲気あるいは不活性雰囲気中で加熱
し一括接合したことを特徴とする半導体装置とすること
により達成され、その半導体製造方法を適用することに
より達成される。According to the present invention, there is provided a laminated body in which the semiconductor element and the lead frame are laminated, and Sn, Ag, Au, Al, Cu, N are provided between the semiconductor element and the lead frame.
It is characterized in that at least one type of brazing material containing at least one element selected from the group of i, Ge, Ga, In, P, Bi, and Zn is used to heat and collectively bond in a vacuum atmosphere or an inert atmosphere. And a semiconductor manufacturing method applied to the semiconductor device.

【００３７】また、前記複合材料の最表面から５μｍ以
内の領域に存在する酸化物粒子が積層実装前に比べて体
積収縮していないことが好ましい。Further, it is preferable that the oxide particles present in the region within 5 μm from the outermost surface of the composite material do not undergo volumetric shrinkage as compared with those before the lamination mounting.

【００３８】[0038]

【発明の実施の形態】（実施例１）図１は本発明の実施
例の一つである絶縁型半導体装置の構造を説明する図で
ある。図１(ａ)は上面図、図１(ｂ）は図１(ａ）Ａ−
Ａ′部の断面図である。半導体素子１をセラミック絶縁
基板２上に、セラミック絶縁基板２をベース材（支持
板）３上にそれぞれろう付け搭載した後、エポキシ系樹
脂ケース４，ボンディングワイヤ５，エポキシ系樹脂ふ
た６を設け、同一ケース内にシリコーンゲル樹脂(封止
板)７を充填した。ここで、ベース材３上のセラミック
絶縁基板２はＳｎ−３ｗｔ％Ａｇ−０.５ｗｔ％Ｃｕろ
う材８(厚さ１３０μｍ）でろう付けし、セラミック絶
縁板２の銅板２ａ上には８個のＳｉからなる半導体素子
（ＭＯＳＦＥＴ素子）(寸法７mm×７mm×０.４mm)１が
Ｓｎ−３ｗｔ％Ａｇ−０.５ｗｔ％Ｃｕろう材９(厚さ１
３０μｍ）でろう付けした。Ｓｎ−３ｗｔ％Ａｇ−０.
５ｗｔ％Ｃｕろう材８及び９によるろう付けはフラック
ス含有のペーストはんだ材を用いて、１×１０のマイナ
ス３乗torrの真空下で同時に実施した。各素子１に形成
されたゲート電極，エミッタ電極等と、絶縁基板上に形
成した電極２ａ，２ｂ、エポキシ系樹脂ケース４にあら
かじめ取り付けられている端子１０間は、直径300μｍ
のＡｌ線（ボンディングワイヤ）５を用いて超音波接合
法によりワイヤボンディングした。１１は温度検出用サ
ーミスタ素子で、Ｓｎ−３ｗｔ％Ａｇ−0.5ｗｔ％Ｃｕ
はんだ（ろう材）９でろう付けされ、電極２ａ，２ｂと
端子１０との間を直径３００μｍのＡｌ線５でワイヤボ
ンディングし、外部へ連絡されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a diagram for explaining the structure of an insulating semiconductor device which is one of the embodiments of the present invention. 1 (a) is a top view, and FIG. 1 (b) is FIG.
It is sectional drawing of A'section. After mounting the semiconductor element 1 on the ceramic insulating substrate 2 and the ceramic insulating substrate 2 on the base material (support plate) 3 by brazing, an epoxy resin case 4, bonding wires 5, and an epoxy resin lid 6 are provided, Silicone gel resin (sealing plate) 7 was filled in the same case. Here, the ceramic insulating substrate 2 on the base material 3 is brazed with Sn-3 wt% Ag-0.5 wt% Cu brazing material 8 (thickness 130 μm), and eight ceramic insulating boards 2 are provided on the copper plate 2 a. A semiconductor element (MOSFET element) made of Si (size 7 mm × 7 mm × 0.4 mm) 1 is Sn-3 wt% Ag-0.5 wt% Cu brazing material 9 (thickness 1
It was brazed with 30 μm). Sn-3 wt% Ag-0.
The brazing with the 5 wt% Cu brazing materials 8 and 9 was simultaneously performed using a flux-containing paste solder material under a vacuum of 1 × 10 −3 torr. The distance between the gate electrode, the emitter electrode, etc. formed on each element 1, the electrodes 2a, 2b formed on the insulating substrate, and the terminal 10 previously attached to the epoxy resin case 4 is 300 μm.
Wire bonding was carried out by the ultrasonic bonding method using the Al wire (bonding wire) 5. 11 is a thermistor element for temperature detection, Sn-3wt% Ag-0.5wt% Cu
It is brazed with a solder (brazing material) 9, and the electrodes 2a, 2b and the terminal 10 are wire-bonded with an Al wire 5 having a diameter of 300 μm and connected to the outside.

【００３９】なお、エポキシ系樹脂ケース４とベース材
３の間はシリコーン接着樹脂（図示せず）を用いて固定
した。エポキシ系樹脂ふた６の内厚部には凹み６′、端
子１０には穴１０′がそれぞれ設けられ、絶縁型半導体
装置１０００を外部回路と接続するためのネジ（図示せ
ず）が装着されるようになっている。端子１０はあらか
じめ所定形状に打抜き、成形された銅板にＮｉめっきを
施したものであり、エポキシ系樹脂ケース４に取り付け
られている。The epoxy resin case 4 and the base material 3 were fixed with a silicone adhesive resin (not shown). The epoxy resin lid 6 is provided with a recess 6'in its inner thick portion and a hole 10 'in the terminal 10, and a screw (not shown) for connecting the insulated semiconductor device 1000 to an external circuit is mounted therein. It is like this. The terminal 10 is a copper plate that is punched into a predetermined shape in advance and is plated with Ni, and is attached to the epoxy resin case 4.

【００４０】図２は図１に示した本発明絶縁型半導体装
置のサブアッセンブリ部を示した図で、セラミック基板
と半導体素子をベース材としての複合材３にろう付け搭
載した。ベース材３の寸法は７４mm×４３mm×３mmであ
り、周辺部に取り付け穴（直径５.６mm ）３Ａが設けら
れている。ベース材はＣｕマトリックスにＣｕ2Ｏ 粒子
を分散させたＣｕ−Ｃｕ2Ｏ 複合材で構成されており、
Ｃｕ2Ｏ の濃度は５０ｗｔ％で、表面に厚さ３μｍのＮ
ｉめっきが施してある。ベース材３上にはＳｎ−３ｗｔ
％Ａｇ−０.５ｗｔ％Ｃｕ はんだ材によりセラミック絶
縁基板２を、そしてセラミック絶縁基板２上にはＳｎ−
３ｗｔ％Ａｇ−０.５ｗｔ％Ｃｕ はんだ材によりＭＯＳ
ＦＥＴ素子１がそれぞれ搭載されている。また、ベース
材３上にはセラミック絶縁基板２搭載領域に対応するよ
うにはんだレジスト膜２２が施されており、はんだ付け
時のはんだ流れ防止とセラミック絶縁基板２の位置ずれ
防止を図っている。さらに、セラミック絶縁基板２上に
は、半導体素子１の搭載領域に対応するようにはんだレ
ジスト膜２１が施されており、はんだ付け時のはんだ流
れ防止と半導体素子１の位置ずれ防止を図っている。こ
れらの位置ずれ防止を兼ねたレジスト膜２１，２２があ
るため、ペーストはんだ材を用い、かつベース板３，絶
縁基板２、及び半導体素子１を位置合わせ治具を用いず
に一度に搭載できる。なお、この絶縁型半導体装置１０
００は１００Ｖ、４００Ａ級のものである。FIG. 2 is a view showing a subassembly portion of the insulated semiconductor device of the present invention shown in FIG. 1, in which a ceramic substrate and a semiconductor element are brazed and mounted on a composite material 3 as a base material. The dimensions of the base material 3 are 74 mm × 43 mm × 3 mm, and mounting holes (diameter 5.6 mm) 3 A are provided in the peripheral portion. Base material is composed of Cu-Cu 2 O composite material obtained by dispersing Cu 2 O particles Cu matrix,
The concentration of Cu 2 O is 50 wt% and the thickness of N 3 N on the surface is
i-plated. Sn-3wt on the base material 3
% Ag-0.5 wt% Cu Solder material for the ceramic insulating substrate 2 and Sn-on the ceramic insulating substrate 2
3wt% Ag-0.5wt% Cu MOS by solder material
Each FET element 1 is mounted. Further, a solder resist film 22 is provided on the base material 3 so as to correspond to the mounting region of the ceramic insulating substrate 2, so as to prevent the solder flow at the time of soldering and the displacement of the ceramic insulating substrate 2. Further, a solder resist film 21 is provided on the ceramic insulating substrate 2 so as to correspond to the mounting region of the semiconductor element 1, so as to prevent the solder flow at the time of soldering and the displacement of the semiconductor element 1. . Since the resist films 21 and 22 also serve to prevent the positional displacement, the paste solder material can be used and the base plate 3, the insulating substrate 2, and the semiconductor element 1 can be mounted at once without using a positioning jig. The isolated semiconductor device 10
00 is 100V, 400A class.

【００４１】図３はセラミック絶縁基板の詳細を説明す
る平面及び断面図である。セラミック絶縁基板２は、寸
法５０mm×３０mm×０.６mm を有するＡｌＮ焼結体（熱
膨張率４.３ppm／℃ ，熱伝導率１６０Ｗ／ｍ.Ｋ）２０
の両面に、厚さ３００μｍのＣｕ−Ｃｕ2Ｏ 複合材料板
２ａ（ドレイン電極を兼ねる），２ｂ（ソース電極を兼
ねる），２ｃ（サーミスタ搭載用）と、厚さ２５０μｍ
のＣｕ−Ｃｕ2Ｏ 複合材料板２ｄを、Ａｇ−Ｃｕ系ろう
材（図示せず、厚さ２０μｍ）によりそれぞれ接合した
ものである。配線材にＣｕ−Ｃｕ2Ｏ 複合材を用いたの
はＡｌＮ燒結体との熱膨張率のマッチングを図り、長期
信頼性を確保するためである。なお、Ｃｕ−Ｃｕ2Ｏ 複
合材料板２ａ，２ｂ，２ｃ、及び２ｄの表面には厚さ２
μｍのＮｉめっき（図示せず）が施されている。また、
ＡｌＮ焼結体１２の代替物として窒化シリコン焼結体
（熱膨張率３.１ppm／℃ ，熱伝導率１２０Ｗ／ｍ.Ｋ）
を用いることができる。FIG. 3 is a plan view and a sectional view for explaining the details of the ceramic insulating substrate. The ceramic insulating substrate 2 is an AlN sintered body having a size of 50 mm × 30 mm × 0.6 mm (coefficient of thermal expansion 4.3 ppm / ° C., thermal conductivity 160 W / m.K) 20.
A Cu-Cu 2 O composite material plate 2 a (also serving as a drain electrode), 2 b (also serving as a source electrode), 2 c (for mounting a thermistor) and a thickness of 250 μm having a thickness of 300 μm on both surfaces of
Of Cu-Cu 2 O composite plate 2d, Ag-Cu-based brazing material (not shown, thickness 20 [mu] m) is obtained by joining each by. The reason why the Cu—Cu 2 O composite material is used for the wiring material is to match the coefficient of thermal expansion with the AlN sintered body and to secure long-term reliability. Incidentally, Cu-Cu 2 O composite plate 2a, 2b, 2c, and 2d on the surface thickness of 2
μm Ni plating (not shown) is applied. Also,
Silicon nitride sintered body as an alternative to AlN sintered body 12 (coefficient of thermal expansion 3.1 ppm / ° C, thermal conductivity 120 W / m.K)
Can be used.

【００４２】図４は本実施例絶縁型半導体装置の回路を
説明する図である。ＭＯＳＦＥＴ素子１が４個並列に配
置されたブロック１００１を２系統有し、各ブロック10
01は直列に接続され、入力端子Ａin，出力端子Ａout 等
が所定の位置から引き出された構成である。また、この
回路の稼動時における温度を検出するためのサーミスタ
１１が絶縁型半導体装置１０００内に独立して配置され
る。FIG. 4 is a diagram for explaining the circuit of the insulated semiconductor device of this embodiment. Two blocks 1001 in which four MOSFET elements 1 are arranged in parallel are provided, and each block 10
01 is connected in series, and has a configuration in which the input terminal Ain, the output terminal Aout, etc. are pulled out from predetermined positions. Further, the thermistor 11 for detecting the temperature during operation of this circuit is independently arranged in the insulating semiconductor device 1000.

【００４３】なお本実施例において、比較用として従来
例（還元雰囲気（水素）中はんだ付け）と同様の実装工
程を経た絶縁型半導体装置も作製した。ろう付部には本
実施例で用いたペーストはんだは用いることができない
ので、板製はんだを用い、位置合せ治具をもちいて搭載
した。ペーストはんだを用いることができない理由は、
大気圧以上で行うため、加熱中にペーストはんだから発
生するガスが溶融はんだ中に溜り、そこが未接合領域と
して残ってしまうからである。In this example, for comparison, an insulating semiconductor device was also manufactured through the same mounting process as the conventional example (soldering in a reducing atmosphere (hydrogen)). Since the paste solder used in this example cannot be used for the brazing portion, plate solder was used and mounted using a positioning jig. The reason why paste solder cannot be used is
Since the heating is performed at atmospheric pressure or higher, the gas generated from the paste solder during heating accumulates in the molten solder and remains there as an unbonded region.

【００４４】図５は本実施例によって作製した半導体装
置１０００の、ベース基板の断面組織を示したものであ
る。図６は従来工程で作製した半導体装置の、ベース基
板の断面組織を示したものである。図５において、複合
材の母相２０００であるＣｕの最表面、すなわちベース
基板３の表面に施されている金属皮膜２００１（Ｎｉめ
っき膜）との界面に存在する酸化物粒子２００２（Ｃｕ
2Ｏ 粒子）が、製造前の状態（図７）と変化していない
ことが確認できる。FIG. 5 shows a cross-sectional structure of the base substrate of the semiconductor device 1000 manufactured according to this embodiment. FIG. 6 shows a cross-sectional structure of a base substrate of a semiconductor device manufactured by a conventional process. In FIG. 5, oxide particles 2002 (Cu) existing on the outermost surface of Cu, which is the matrix 2000 of the composite material, that is, at the interface with the metal film 2001 (Ni plating film) applied to the surface of the base substrate 3 are formed.
It can be confirmed that the 2 O particles) have not changed from the state before production (FIG. 7).

【００４５】一方、図６において、複合材の母相２００
０であるＣｕの最表面、すなわちベース基板３の表面に
施されている金属皮膜２００１（Ｎｉめっき膜）との界
面に存在する酸化物粒子２００２（Ｃｕ2Ｏ 粒子）が、
製造前の状態（図７）と比較して体積が減少し、製造前
に存在した領域の一部が空洞化している様子が観察でき
る。このＣｕ2Ｏ 変質領域は、母相の表面にＮｉめっき
を施したにもかかわらず、母相の表面から１μｍ程度の
領域にまで及んでいる。ベース板３にＮｉめっきのよう
な表面酸化を抑える保護膜を施さなければ、酸化物粒子
の変質領域は更に深くにまで及ぶであろうことは自明で
あり、実際、Ｎｉめっきを施さなかった場合は５μｍ程
度にまで拡大していたことを確認している。On the other hand, in FIG. 6, the matrix 200 of the composite material is shown.
The oxide particles 2002 (Cu 2 O particles) existing at the outermost surface of Cu, which is 0, that is, the interface with the metal film 2001 (Ni plating film) applied to the surface of the base substrate 3,
It can be observed that the volume is reduced as compared with the state before manufacturing (FIG. 7) and a part of the region existing before manufacturing is hollow. This Cu 2 O altered region extends to a region of about 1 μm from the surface of the mother phase, even though the surface of the mother phase is plated with Ni. It is self-evident that if the base plate 3 is not provided with a protective film such as Ni plating that suppresses surface oxidation, the altered region of the oxide particles will reach deeper. In fact, when Ni plating is not applied. Has confirmed that it has expanded to about 5 μm.

【００４６】本実施例絶縁型半導体装置１０００のＭＯ
ＳＦＥＴ素子１とベース材３間の熱抵抗は０.０３０℃
／Ｗであった。この値は比較試料の熱抵抗０.０３３℃
／Ｗより若干ではあるが、低い。この理由は、Ｓｎ−３
ｗｔ％Ａｇ−０.５ｗｔ％Ｃｕはんだによるろう付けを
フラックス含有のペーストはんだ材を用いて非還元性雰
囲気（１０のマイナス３乗torrの真空）下で実施してい
るため、はんだ接合部のボイドが低減され、熱の伝達性
が向上したためである。MO of insulating semiconductor device 1000 of this embodiment
The thermal resistance between the SFET element 1 and the base material 3 is 0.030 ° C.
Was / W. This value is the thermal resistance of comparative sample 0.033 ℃
It is slightly lower than / W, but lower. The reason for this is Sn-3
Since brazing with wt% Ag-0.5 wt% Cu solder is performed in a non-reducing atmosphere (vacuum of 10 −3 torr) using a paste solder material containing flux, the voids in the solder joint are Is reduced and the heat transfer property is improved.

【００４７】図８は温度サイクル試験における絶縁型半
導体装置の熱抵抗の推移を示す図である。この試験は、
−５５〜１５０℃の温度変化を繰り返し与えるもので、
本実施例絶縁型半導体装置では熱抵抗が初期値の１.５
倍に達する温度サイクル数を寿命と定義している。本実
施例絶縁型半導体装置１０００の場合は、１０００回後
でも初期値(０.０３０℃／Ｗ）と同等の値で推移してい
る。１０００回以降で熱抵抗は微増しているけれども、
５０００回程度までは許容される０.０４５℃／Ｗ(寿
命）以下で推移している。FIG. 8 is a diagram showing changes in the thermal resistance of the insulating semiconductor device in the temperature cycle test. This test is
It gives a temperature change of -55 to 150 ℃ repeatedly,
In the insulated semiconductor device of this embodiment, the initial thermal resistance is 1.5.
The number of temperature cycles that doubles is defined as the life. In the case of the insulated semiconductor device 1000 of the present example, the value is equivalent to the initial value (0.030 ° C./W) even after 1000 times. Although the thermal resistance has slightly increased after 1000 times,
Up to about 5000 times, it has remained below the allowable level of 0.045 ° C / W (life).

【００４８】一方、比較試料の熱抵抗値は１００回程度
で増加しており、約２５０回で寿命の０.０５０℃／Ｗ
にまで増加している。この原因は、比較試料のはんだ接
合部に未接合領域、すなわちボイドが大量に残ってお
り、この部分が起点となって温度サイクル試験中にクラ
ックとなってはんだ層中に伸展していったためである。On the other hand, the thermal resistance value of the comparative sample increased after about 100 times, and at about 250 times the life was 0.050 ° C./W.
It is increasing to. This is because a large amount of unbonded areas, that is, voids, remained in the solder joints of the comparative sample, and this portion became the starting point and cracked during the temperature cycle test and extended into the solder layer. is there.

【００４９】図９は、温度サイクル数に対するはんだ接
合部の未接合領域（ボイド率）の変化を示したものであ
る。図と全く同様の傾向があることが確認でき、上述し
たことを裏付けている。FIG. 9 shows changes in the unbonded region (void ratio) of the soldered joint with respect to the number of temperature cycles. It can be confirmed that there is a tendency similar to the figure, which supports the above.

【００５０】また図１０は、本実施例と比較試料の装置
作製前と装置作製後のベース材の熱膨張率の変化を調べ
た結果を示したものである。本実施例試料では熱膨張率
の変化は全くないが、比較試料では大幅に増加してお
り、還元雰囲気下で機械的性質が変化した影響が確認で
きる。この部材の変質が温度サイクル試験でボイドが増
加していったもう一つの要因である。絶縁板上に形成し
た配線材にも同様のことが言える。実際、温度サイクル
試験２５０回後に絶縁板から剥離していた。FIG. 10 shows the results of examining the changes in the coefficient of thermal expansion of the base material of this example and the comparative sample before and after the device was manufactured. In the sample of this example, the coefficient of thermal expansion does not change at all, but in the sample of comparison, the coefficient of thermal expansion greatly increases, and it can be confirmed that the mechanical properties have changed in the reducing atmosphere. Deterioration of this member is another cause of the increase in voids in the temperature cycle test. The same applies to the wiring material formed on the insulating plate. In fact, it was peeled off from the insulating plate after 250 times of the temperature cycle test.

【００５１】纏めると、本実施例絶縁型半導体装置１０
００が優れた温度サイクル耐量を示した理由は、セラミ
ック絶縁基板とベース材の熱膨張率の整合性が装置作製
前と後で保たれていたため、−５５〜１５０℃の温度変
化を繰り返し与えてもはんだ層に作用するひずみが僅少
に抑えられることによる。In summary, the insulation type semiconductor device 10 of this embodiment.
The reason why 00 showed excellent temperature cycle resistance was that the consistency of the coefficient of thermal expansion between the ceramic insulating substrate and the base material was maintained before and after the device was manufactured. Therefore, the temperature change of −55 to 150 ° C. was repeatedly applied. This is because the strain acting on the solder layer can be suppressed to a minimum.

【００５２】（実施例２）本実施例では、樹脂絶縁構造
型半導体装置の中間金属部材として半導体装置用複合部
材を適用した例について説明する。(Embodiment 2) In this embodiment, an example in which a composite member for a semiconductor device is applied as an intermediate metal member of a resin insulating structure type semiconductor device will be described.

【００５３】図１１は本発明の実施例の絶縁型半導体装
置の一つを説明する平面図、断面図である。Ｓｉからな
るＭＯＳＦＥＴ素子１（４個、チップサイズ７mm×７mm
×０.３mm）は、サイズ８mm×８mm×０.６mmの中間金属
部材５０を介して、支持部材を兼ねるＡｌ絶縁回路基板
（絶縁層）５１上にろう材５３，５４により搭載されて
いる。中間金属板５０は、例えばＣｕ−Ｃｕ2Ｏ 複合材
よりなる。Ａｌ絶縁回路基板５１は支持板５２としての
Ａｌ板(４０mm×３０mm×１.５mm）の一方の主面にエポ
キシ樹脂絶縁層（厚さ１５０μｍ）５５を介してＣｕ配
線層（厚さ７０μｍ）５６が選択形成されている。ＭＯ
ＳＦＥＴチップ１と中間金属部材５０は組成Ｓｎ−３ｗ
ｔ％Ａｇ−０.５ｗｔ％Ｃｕ なるろう材（厚さ７０μ
ｍ）５３により、そして中間金属部材５０とＡｌ絶縁回
路基板５１は組成Ｓｎ−３ｗｔ％Ａｇ−０.５ｗｔ％Ｃ
ｕ なるろう材（厚さ７０μｍ）５４によりそれぞれろ
う付けされている。またＣｕ配線層５６間には、チップ
抵抗５７がろう材５４により固着されている。これらの
ろう付けは、ペースト状ろう材を所定部に塗布し、この
塗布部に所要部材搭載した後、１０のマイナス３乗torr
の真空中で加熱する工程で実施されている。次いで、あ
らかじめＣｕからなる端子５８を一体化したエポキシ樹
脂からなるケース５９を、Ａｌ絶縁回路基板５１にシリ
コーン樹脂接着剤（図示せず）により取り付けた。ＭＯ
ＳＦＥＴ素子のゲート，ソース、及びドレインにはそれ
ぞれＡｌ線（直径３００μｍ）６０のワイヤボンディン
グを施した。最終的にエポキシ樹脂からなるケースふた
（図示を省略）を取り付けて、半導体装置１０００を完
成した。FIG. 11 is a plan view and a sectional view for explaining one of the insulating type semiconductor devices of the embodiment of the present invention. MOSFET element 1 made of Si (4 pieces, chip size 7 mm x 7 mm
X 0.3 mm) is mounted on the Al insulating circuit board (insulating layer) 51 which also functions as a supporting member by brazing materials 53 and 54 through an intermediate metal member 50 having a size of 8 mm x 8 mm x 0.6 mm. The intermediate metal plate 50 is made of, for example, a Cu—Cu 2 O composite material. The Al insulating circuit board 51 has a Cu wiring layer (thickness 70 μm) 56 on one main surface of an Al plate (40 mm × 30 mm × 1.5 mm) as a support plate 52 with an epoxy resin insulating layer (thickness 150 μm) 55 interposed therebetween. Are selectively formed. MO
The composition of the SFET chip 1 and the intermediate metal member 50 is Sn-3w.
t% Ag-0.5 wt% Cu brazing filler metal (thickness 70 μm
m) 53, and the intermediate metal member 50 and the Al insulated circuit board 51 have a composition of Sn-3 wt% Ag-0.5 wt% C.
It is brazed by a brazing material (thickness 70 μm) 54 of u. A chip resistor 57 is fixed between the Cu wiring layers 56 by a brazing material 54. For these brazings, a paste-like brazing material is applied to a predetermined part, and the required parts are mounted on this application part, and then 10 to the third power torr.
It is carried out in the step of heating in vacuum. Next, a case 59 made of an epoxy resin in which the terminal 58 made of Cu was integrated in advance was attached to the Al insulated circuit board 51 with a silicone resin adhesive (not shown). MO
An Al wire (diameter 300 μm) 60 was wire-bonded to the gate, source and drain of the SFET element. Finally, a case lid (not shown) made of epoxy resin was attached to complete the semiconductor device 1000.

【００５４】図１２は本実施例絶縁型半導体装置の温度
サイクル試験による熱抵抗の推移を示したものである。
温度サイクル数２０００回までは、初期値と同等の熱抵
抗（約３.０℃／Ｗ ）が維持されている。熱抵抗の増大
は温度サイクル数２０００回以降で生じている。初期値
の１.５ 倍に到達したときの温度サイクル数を寿命と定
義すると、本実施例絶縁型半導体装置１０００の寿命は
約５０００回になる。以上のようにして得られた本実施
例絶縁型半導体装置１０００は量産製品として十分な信
頼性を有している。また、本実施例絶縁型半導体装置１
０００では、金属中間部材５０の熱膨張率が調整されて
おり、半導体装置作製の前と後でその値は変化していな
いことを確認している。このことはろう材層５３や５４
のいずれかが先行破壊するのを抑え、半導体装置全体と
しての寿命を長くするのに寄与する。FIG. 12 shows the transition of the thermal resistance of the insulated semiconductor device of this embodiment in the temperature cycle test.
Up to 2000 temperature cycles, the thermal resistance (about 3.0 ° C / W) equivalent to the initial value is maintained. The increase in thermal resistance occurs after the number of temperature cycles of 2000. If the number of temperature cycles when reaching the initial value 1.5 times is defined as the life, the life of the insulated semiconductor device 1000 of this embodiment is about 5000 times. The insulated semiconductor device 1000 of this embodiment obtained as described above has sufficient reliability as a mass-produced product. In addition, the insulated semiconductor device 1 of the present embodiment
000, the coefficient of thermal expansion of the metal intermediate member 50 is adjusted, and it is confirmed that the value does not change before and after the semiconductor device is manufactured. This means that the brazing material layers 53 and 54
One of the two suppresses the preceding destruction and contributes to prolonging the life of the semiconductor device as a whole.

【００５５】パワー半導体素子１はＩＧＢＴ，トランジ
スタ，サイリスタ，ダイオード，ＭＯＳＦＥＴ等、異な
る電気的機能を持つものであってよい。The power semiconductor device 1 may be an IGBT, a transistor, a thyristor, a diode, a MOSFET or the like having different electrical functions.

【００５６】（実施例３）本実施例ではセルラー電話機
等の送信部に用いる高周波電力増幅装置としての絶縁型
半導体装置について説明する。(Embodiment 3) In this embodiment, an insulation type semiconductor device as a high frequency power amplifier used in a transmitting section of a cellular telephone or the like will be described.

【００５７】本実施例絶縁型半導体装置（サイズ１０.
５mm×４mm×１.３mm）１０００は以下の構成からな
る。図１３は本実施例絶縁型半導体装置の断面模式図で
ある。ここでは、支持部材１００としての多層ガラスセ
ラミック基板(サイズ１０.５mm×４mm×０.５mm 、３層
配線，熱膨張率６.２ppm／℃，熱伝導率２.５Ｗ／ｍ.
Ｋ，曲げ強度０.２５ＧＰａ，ヤング率１１０Ｇｐａ，
誘電率５.６（１ＭＨｚ））上に、ＭＯＳＦＥＴ素子(サ
イズ２.４mm×１.８mm×０.２４mm）１，チップ抵抗
（約７ppm／℃）１０１，チップコンデンサ(約１１.５p
pm／℃）１０２を含むチップ部品が搭載されている。Ｍ
ＯＳＦＥＴ素子１と多層ガラスセラミック基板１００の
間には、例えばＣｕ−Ｃｕ2Ｏ 複合材からなる中間金属
部材１０３が装備されている。多層ガラスセラミック基
板１００の内部には厚膜内層配線層（Ａｇ−１ｗｔ％Ｐ
ｔ，厚さ１５μｍ）、多層配線間の電気的連絡のための
厚膜スルーホール導体（Ａｇ−１ｗｔ％Ｐｔ，直径１４
０μｍ）、放熱路のための厚膜サーマルビア（Ａｇ−１
ｗｔ％Ｐｔ，直径１４０μｍ）が設けられている。ま
た、多層ガラスセラミック基板１００の一方の主面上に
厚膜配線パターン（Ａｇ−１ｗｔ％Ｐｔ，厚さ１５μ
ｍ）１０４が設けられ、この厚膜配線パターン（配線
層）１０４上にはチップ抵抗１０１，チップコンデンサ
１０２を含むチップ部品が組成Ｓｎ−３ｗｔ％Ａｇ−
０.５ｗｔ％Ｃｕ からなるろう材層１０５により導電的
に固着されている。ＭＯＳＦＥＴ素子（Ｓｉ，３.５ppm
／℃）１は、多層ガラスセラミック基板１００の一方の
主面に設けた凹みの部分に中間金属部材１０３を介して
搭載される。搭載は１０のマイナス３乗の真空中で行っ
た。中間金属部材１０３のサイズは２.８mm×２.２mm×
０.２mm である。ここで、MOSFET素子１と中間金属部材
１０３を接続するろう材１０５や、中間金属部材１０３
と多層ガラスセラミック基板１００を接続するろう材１
０６は、いずれも組成Ｓｎ−３ｗｔ％Ａｇ−０.５ｗｔ
％Ｃｕ からなるペーストはんだ材である。MOSFET素子
１と厚膜配線パターン１０４の所定部間には、Ａｕから
なるボンディングワイヤ１０７がボンディング（直径３
０μｍ）されている。多層ガラスセラミック基板１００
の他方の主面には、厚膜外部電極層１０４′(Ａｇ−１
ｗｔ％Ｐｔ,厚さ１５μｍ）が設けられている。厚膜外
部電極層１０４′は多層ガラスセラミック基板１００の
内部に設けられた内部配線層やスルーホール配線を中継
して厚膜配線パターン１０４と電気的に接続されてい
る。多層ガラスセラミック基板１００の一方の主面側に
はエポキシ樹脂層（封止材）１０８が設けられ、これに
より搭載チップ部品等は封止されている。Example Insulated semiconductor device (size 10.
5 mm × 4 mm × 1.3 mm) 1000 has the following configuration. FIG. 13 is a schematic sectional view of the insulated semiconductor device of this embodiment. Here, a multilayer glass ceramic substrate (size 10.5 mm × 4 mm × 0.5 mm, three-layer wiring, thermal expansion coefficient 6.2 ppm / ° C., thermal conductivity 2.5 W / m.
K, bending strength 0.25 GPa, Young's modulus 110 Gpa,
Dielectric constant of 5.6 (1MHz), MOSFET element (size 2.4mm × 1.8mm × 0.24mm) 1, chip resistance (about 7ppm / ℃) 101, chip capacitor (about 11.5p)
pm / ° C.) 102 is mounted. M
An intermediate metal member 103 made of, for example, a Cu—Cu 2 O composite material is provided between the OSFET element 1 and the multilayer glass ceramic substrate 100. Inside the multilayer glass ceramic substrate 100, a thick film inner wiring layer (Ag-1 wt% P
t, thickness 15 μm), a thick film through-hole conductor (Ag-1 wt% Pt, diameter 14) for electrical communication between multilayer wirings.
0 μm), thick film thermal via for heat dissipation path (Ag-1
wt% Pt, diameter 140 μm). In addition, a thick film wiring pattern (Ag-1 wt% Pt, thickness 15 μm) is formed on one main surface of the multilayer glass ceramic substrate 100.
m) 104 is provided, and on this thick film wiring pattern (wiring layer) 104, a chip component including a chip resistor 101 and a chip capacitor 102 has a composition of Sn-3 wt% Ag-.
It is electrically conductively fixed by the brazing material layer 105 made of 0.5 wt% Cu. MOSFET device (Si, 3.5ppm
/ ° C.) 1 is mounted on the concave portion provided on one main surface of the multilayer glass ceramic substrate 100 via the intermediate metal member 103. The mounting was performed in a vacuum of 10 −3. The size of the intermediate metal member 103 is 2.8 mm x 2.2 mm x
It is 0.2 mm. Here, the brazing material 105 connecting the MOSFET element 1 and the intermediate metal member 103, and the intermediate metal member 103.
1 for connecting the multi-layer glass ceramic substrate 100 with
No. 06 has a composition of Sn-3 wt% Ag-0.5 wt.
It is a paste solder material made of Cu. A bonding wire 107 made of Au is bonded (diameter 3) between the MOSFET element 1 and a predetermined portion of the thick film wiring pattern 104.
0 μm). Multilayer glass ceramic substrate 100
Of the thick film external electrode layer 104 '(Ag-1
wt% Pt, thickness 15 μm). The thick film external electrode layer 104 ′ is electrically connected to the thick film wiring pattern 104 by relaying the internal wiring layer and the through hole wiring provided inside the multilayer glass ceramic substrate 100. An epoxy resin layer (sealing material) 108 is provided on one main surface side of the multilayer glass ceramic substrate 100, and the mounted chip components and the like are sealed by this.

【００５８】図１４は本実施例絶縁型半導体装置を適用
した携帯電話の回路ブロック図である。入力音声信号は
混声器２００で発信器２０１からの高周波信号に変換さ
れ、電力増幅器である絶縁型半導体装置１０００，アン
テナ共用器２０２を通してアンテナから電波として発射
される。送信電力は結合器によってモニタされ、電力増
幅器である絶縁型半導体装置１０００への制御信号よっ
て一定に保たれている。この携帯電話には８００〜１０
００ＭＨｚ帯の電波が使用されている。FIG. 14 is a circuit block diagram of a mobile phone to which the insulated semiconductor device of this embodiment is applied. The input voice signal is converted into a high frequency signal from the oscillator 201 by the voice mixer 200, and is emitted as a radio wave from the antenna through the insulating semiconductor device 1000, which is a power amplifier, and the antenna duplexer 202. The transmission power is monitored by the coupler and kept constant by the control signal to the isolated semiconductor device 1000, which is a power amplifier. 800-10 for this cell phone
Radio waves in the 00 MHz band are used.

【００５９】（実施例４）本発明ではミニモールド型ト
ランジスタ用のリードフレームとして複合材を適用した
非絶縁型半導体装置につて説明する。(Embodiment 4) In the present invention, a non-insulating semiconductor device to which a composite material is applied as a lead frame for a mini mold type transistor will be described.

【００６０】図１５は本実施例ミニモールド型非絶縁型
半導体装置の断面模式図である。半導体素子１としての
ＳＩからなるトランジスタ素子（サイズ１mm×１mm×
０.３mm）は、例えばＣｕ−Ｃｕ2Ｏ 複合材からなるリ
ードフレーム(厚さ０.３mm）６００にＳｎ−５ｗｔ％Ｓ
ｂ合金からなるろう材６０１により搭載されている。搭
載時は１０のマイナス３乗torrの真空下で行った。トラ
ンジスタ素子１のコレクタはろう材６０１により搭載さ
れた側に配置されている。エミッタ及びベースはろう付
けされた側と反対側に設けられ、トランジスタ素子１か
ら引出されたＡｌ細線（ボンディングワイヤ）６０２に
よりリードフレーム６００に連絡されている。また、ト
ランジスタ素子１の搭載とＡｌ細線６０２の配線が施さ
れた主要部は、トランスファモールドによってエポキシ
樹脂６０３で覆われている。リードフレーム６００はエ
ポキシ樹脂（封止材）６０３によるモールドが完了した
段階で切り離され、それぞれ独立した端子としての機能
が付与される。FIG. 15 is a schematic sectional view of the mini-mold type non-insulating semiconductor device of this embodiment. Transistor element made of SI as semiconductor element 1 (size 1 mm x 1 mm x
0.3 mm) is, for example, Sn-5 wt% S in a lead frame (thickness: 0.3 mm) 600 made of a Cu—Cu 2 O composite material.
It is mounted by a brazing material 601 made of b alloy. The mounting was performed under a vacuum of 10 −3 torr. The collector of the transistor element 1 is arranged on the side mounted with the brazing material 601. The emitter and the base are provided on the opposite side to the brazed side, and are connected to the lead frame 600 by an Al thin wire (bonding wire) 602 drawn from the transistor element 1. The main part on which the transistor element 1 is mounted and the Al thin wire 602 is provided is covered with an epoxy resin 603 by transfer molding. The lead frame 600 is cut off at the stage when the molding with the epoxy resin (sealing material) 603 is completed, and the function as an independent terminal is given to each.

【００６１】本実施例非絶縁型半導体装置１０００は温
度サイクル試験（−５５〜１５０℃，２０００回）後に
電流増幅率３０を示した。この値は試験前の初期電流増
幅率とほぼ同等である。また、この試験によってはトラ
ンジスタ素子１とリードフレーム６００間の剥離やろう
材６０１のクラックは観察されなかった。トランジスタ
素子１をリードフレーム６００に搭載する前と後で、リ
ードフレーム６００の熱膨張率の変化が無い。The non-insulated semiconductor device 1000 of this example showed a current amplification factor of 30 after the temperature cycle test (−55 to 150 ° C., 2000 times). This value is almost the same as the initial current amplification factor before the test. Further, in this test, peeling between the transistor element 1 and the lead frame 600 and cracks in the brazing material 601 were not observed. There is no change in the coefficient of thermal expansion of the lead frame 600 before and after mounting the transistor element 1 on the lead frame 600.

【００６２】上記温度サイクル試験を施した試料は、引
き続いて８５℃，８５％ＲＨの条件の下で高温高湿試験
（１０００ｈ）に供された。試験後のエミッタ−コレク
タ間の漏れ電流を測定したところ、０.１μＡ(ａｔ３０
Ｖ）と初期値とほぼ同等の値を示した。このことは、高
温高湿試験に先立って実施された温度サイクル試験にお
いても、はんだ接合部に異常が生じていないことを意味
する。The sample subjected to the temperature cycle test was subsequently subjected to a high temperature and high humidity test (1000 h) under the conditions of 85 ° C. and 85% RH. The leakage current between the emitter and collector after the test was measured and found to be 0.1 μA (at 30
V) and a value almost equal to the initial value. This means that there is no abnormality in the solder joint even in the temperature cycle test performed prior to the high temperature and high humidity test.

【００６３】以上までに、本発明の実施例について説明
した。本発明における半導体装置１０００は、実施例記
載の範囲に限定されるものではない。The embodiments of the present invention have been described above. The semiconductor device 1000 according to the present invention is not limited to the range described in the embodiments.

【００６４】[0064]

【発明の効果】本発明によれば、接合部にボイドがなく
高い接合強度を有し、熱膨張率や熱伝導率などの機械
的，物理的性質がパッケージ組立て後も変化せず、長期
信頼性を損なうことのない半導体パッケージと、その製
造プロセスを提供することができる。さらに、より簡略
化され、かつはんだ接合部の低ボイド化を実現した製造
プロセスも実現できる。EFFECTS OF THE INVENTION According to the present invention, there are no voids in the joint and high joint strength, and mechanical and physical properties such as thermal expansion coefficient and thermal conductivity do not change even after package assembly, and long-term reliability It is possible to provide a semiconductor package that does not impair the property and a manufacturing process thereof. Further, it is possible to realize a manufacturing process which is more simplified and has a reduced void in the solder joint.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例の一つである絶縁型半導体装置
の構造を詳細に説明する図である。FIG. 1 is a diagram illustrating in detail a structure of an insulating semiconductor device which is one of embodiments of the present invention.

【図２】図１に示した本発明絶縁型半導体装置のサブア
ッセンブリ部を示した図である。FIG. 2 is a view showing a sub-assembly portion of the insulating semiconductor device of the present invention shown in FIG.

【図３】セラミック絶縁基板の詳細を説明する平面及び
断面図である。3A and 3B are a plan view and a cross-sectional view illustrating details of a ceramic insulating substrate.

【図４】本実施例絶縁型半導体装置の回路を説明する図
である。FIG. 4 is a diagram illustrating a circuit of the insulated semiconductor device according to the present embodiment.

【図５】本実施例によって作製した半導体装置の、ベー
ス基板の断面組織を示したものである。FIG. 5 shows a cross-sectional structure of a base substrate of a semiconductor device manufactured according to this example.

【図６】母相であるＣｕの最表面に施されているＮｉめ
っき膜との界面に存在するＣｕ2Ｏ 粒子の状態を示した
図である。FIG. 6 is a diagram showing a state of Cu 2 O particles existing at an interface with a Ni plating film formed on the outermost surface of Cu as a mother phase.

【図７】製造前Ｎｉめっき膜との界面に存在するＣｕ2
Ｏ 粒子の状態である。FIG. 7: Cu 2 existing at the interface with the Ni plating film before production
This is the state of O 2 particles.

【図８】温度サイクル試験における絶縁型半導体装置の
熱抵抗の推移を示す図である。FIG. 8 is a diagram showing a transition of thermal resistance of an insulating semiconductor device in a temperature cycle test.

【図９】温度サイクル数に対するはんだ接合部の未接合
領域（ボイド率）の変化を示したものである。FIG. 9 is a graph showing a change in an unbonded region (void ratio) of a soldered joint with respect to the number of temperature cycles.

【図１０】比較試料の装置作製前と装置作製後のベース
材の熱膨張率の変化を調べた結果を示したものである。FIG. 10 shows the results of examining changes in the coefficient of thermal expansion of a base material of a comparative sample before and after manufacturing the device.

【図１１】本発明の実施例の絶縁型半導体装置の一つを
説明する平面図，断面図である。11A and 11B are a plan view and a cross-sectional view illustrating one of the insulated semiconductor devices of the embodiments of the present invention.

【図１２】本実施例絶縁型半導体装置の温度サイクル試
験による熱抵抗の推移を示したものである。FIG. 12 is a graph showing changes in thermal resistance of the insulated semiconductor device of the present example due to a temperature cycle test.

【図１３】本実施例絶縁型半導体装置の断面模式図であ
る。FIG. 13 is a schematic cross-sectional view of an insulated semiconductor device of this embodiment.

【図１４】本実施例絶縁型半導体装置を適用した携帯電
話の回路ブロック図である。FIG. 14 is a circuit block diagram of a mobile phone to which the insulated semiconductor device of this embodiment is applied.

【図１５】本実施例ミニモールド型非絶縁型半導体装置
の断面模式図である。FIG. 15 is a schematic sectional view of a mini-mold type non-insulating semiconductor device of the present embodiment.

【符号の説明】[Explanation of symbols]

１…半導体素子、２…絶縁基板、３，５２，１００…支
持板、４，５９…ケース、５，６０，１０７，６０２…
ボンディングワイヤ、６…ふた、７，１０８，６０３…
封止材、８，９，５３，５４，１０５,１０６,６０１…
ろう材、１０…端子、１１…サーミスタ、２１，２２…
レジスト、１００…支持部材、１０００…半導体装置、
５０，１０３…放熱板（中間金属部材）、５１，５５…
絶縁層、５６，１０４…配線層、５７，１０１…チップ
抵抗、５８…端子、１０２…チップコンデンサ、２００
…混声器、２０１…発信器、６００…リードフレーム、
２０００…複合材の母相、２００１…金属皮膜、２００
２…酸化物粒子。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Insulating substrate, 3, 52, 100 ... Support plate, 4, 59 ... Case, 5, 60, 107, 602 ...
Bonding wire, 6 ... Lid, 7, 108, 603 ...
Sealing material, 8, 9, 53, 54, 105, 106, 601 ...
Brazing material, 10 ... Terminal, 11 ... Thermistor 21,22 ...
Resist, 100 ... Support member, 1000 ... Semiconductor device,
50, 103 ... Heat sink (intermediate metal member), 51, 55 ...
Insulating layers, 56, 104 ... Wiring layers, 57, 101 ... Chip resistors, 58 ... Terminals, 102 ... Chip capacitors, 200
… Mixer, 201… Transmitter, 600… Leadframe,
2000 ... matrix of composite material, 2001 ... metal film, 200
2 ... Oxide particles.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 児玉 弘則 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 飯塚 守 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 (72)発明者 小山 賢治 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 Ｆターム(参考） 4G026 BA03 BA14 BA16 BA17 BA18 BB22 BF13 BH08 5F036 AA01 BA23 BB08 BC06 BC22 BD13    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hironori Kodama             7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture             Inside the Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Mamoru Iizuka             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Kenji Koyama             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 4G026 BA03 BA14 BA16 BA17 BA18                       BB22 BF13 BH08                 5F036 AA01 BA23 BB08 BC06 BC22                       BD13

Claims (24)

【特許請求の範囲】[Claims] 【請求項１】酸化物粒子を含有した複合材料を有する半
導体装置であって、前記酸化物粒子が前記複合材料の母
材の最表面から５μｍ以内の領域にも存在することを特
徴とする半導体装置。1. A semiconductor device having a composite material containing oxide particles, wherein the oxide particles are present in a region within 5 μm from the outermost surface of a base material of the composite material. apparatus. 【請求項２】半導体素子，配線が形成された絶縁板、及
び支持板が順次積層された半導体装置であって、前記配
線または前記支持板の少なくとも一方が酸化物粒子を含
有した複合材料で形成され、かつ前記酸化物粒子が前記
複合材料の母材の最表面から５μｍ以内にも存在するこ
とを特徴とする半導体装置。2. A semiconductor device in which a semiconductor element, an insulating plate having wiring formed thereon, and a supporting plate are sequentially laminated, and at least one of the wiring and the supporting plate is made of a composite material containing oxide particles. And the oxide particles are also present within 5 μm from the outermost surface of the base material of the composite material. 【請求項３】請求項１または２に記載の半導体装置にお
いて、前記複合材料の最表面から５μｍ以内の領域に存
在する酸化物粒子が積層実装前に比べて体積収縮してい
ないことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the oxide particles existing in a region within 5 μm from the outermost surface of the composite material do not shrink in volume as compared with those before stacking mounting. Semiconductor device. 【請求項４】請求項２に記載の半導体装置において、前
記半導体素子と前記配線または前記絶縁板と前記支持板
がペーストはんだ材を用いて接合されていることを特徴
とする半導体装置。4. The semiconductor device according to claim 2, wherein the semiconductor element and the wiring or the insulating plate and the support plate are bonded together by using a paste solder material. 【請求項５】請求項２に記載の半導体装置において、前
記半導体素子と前記配線または前記絶縁板と前記支持板
が、Ｓｎ，Ａｇ，Ａｕ，Ａｌ，Ｃｕ，Ｎｉ，Ｇｅ，Ｇ
ａ，Ｉｎ，Ｐ，Ｂｉ、及びＺｎの群から選択された少な
くとも１元素を含む少なくとも１種類のろう材で接合さ
れていることを特徴とする半導体装置。5. The semiconductor device according to claim 2, wherein the semiconductor element and the wiring or the insulating plate and the supporting plate are made of Sn, Ag, Au, Al, Cu, Ni, Ge, G.
A semiconductor device, wherein the semiconductor device is joined with at least one brazing material containing at least one element selected from the group consisting of a, In, P, Bi, and Zn. 【請求項６】請求項２に記載の半導体装置において、前
記酸化物粒子を含有した複合材料は、銅を母材とし、酸
化銅粒子が分散された複合材料であることを特徴とした
半導体装置。6. The semiconductor device according to claim 2, wherein the composite material containing the oxide particles is a composite material containing copper as a base material and copper oxide particles dispersed therein. . 【請求項７】請求項２に記載の半導体装置において、前
記配線及び支持板の表面にＮｉ，Ｓｎ，Ａｇ，Ａｕ，Ｐ
ｔ，Ｐｄ，Ｚｎ、及びＣｕの群から選択された少なくと
も１種類の金属皮膜が施されていることを特徴とする半
導体装置。7. The semiconductor device according to claim 2, wherein Ni, Sn, Ag, Au, P are formed on the surfaces of the wiring and the support plate.
A semiconductor device having at least one kind of metal film selected from the group consisting of t, Pd, Zn, and Cu. 【請求項８】請求項２に記載の半導体装置において、前
記絶縁板は、酸化アルミニウム，窒化アルミニウム，窒
化ホウ素，窒化ケイ素、及び炭化ケイ素のいずれかより
なることを特徴とする半導体装置。8. The semiconductor device according to claim 2, wherein the insulating plate is made of any one of aluminum oxide, aluminum nitride, boron nitride, silicon nitride, and silicon carbide. 【請求項９】半導体素子，配線が形成された絶縁板、及
び支持板が順次積層された半導体装置の製造方法であっ
て、前記半導体素子、前記配線が形成された絶縁板、及
び前記支持板をＳｎを含む１種類のペースト状ろう材を
介して順次積層した後、真空雰囲気あるいは不活性雰囲
気中で加熱し一括接合する工程を有することを特徴とす
る半導体装置の製造方法。9. A method of manufacturing a semiconductor device in which a semiconductor element, an insulating plate having wiring formed thereon, and a supporting plate are sequentially laminated, wherein the semiconductor element, the insulating plate having wiring formed thereon, and the supporting plate. A method for manufacturing a semiconductor device, which comprises a step of sequentially laminating the above with a type of paste-like brazing material containing Sn and then heating and bonding them together in a vacuum atmosphere or an inert atmosphere. 【請求項１０】半導体素子，放熱板，配線，絶縁材、及
び支持板が順次積層された半導体装置であって、前記放
熱板または配線が酸化物粒子を含有した複合材料で形成
され、かつ前記酸化物粒子が前記複合材料の母材の最表
面から５μｍ以内にも存在することを特徴とした半導体
装置。10. A semiconductor device in which a semiconductor element, a heat dissipation plate, a wiring, an insulating material, and a support plate are sequentially laminated, wherein the heat dissipation plate or the wiring is formed of a composite material containing oxide particles, and A semiconductor device, wherein oxide particles are present within 5 μm from the outermost surface of the base material of the composite material. 【請求項１１】請求項１０に記載の半導体装置におい
て、前記半導体素子と前記放熱板の間、或いは前記放熱
板と前記配線の間はＳｎを含む１種類のペーストはんだ
材で構成されていることを特徴とする半導体装置。11. The semiconductor device according to claim 10, wherein one kind of paste solder material containing Sn is formed between the semiconductor element and the heat sink or between the heat sink and the wiring. Semiconductor device. 【請求項１２】請求項１０に記載の半導体装置におい
て、前記半導体素子と前記放熱板の間、或いは前記放熱
板と前記配線の間はＳｎ，Ａｇ，Ａｕ，Ａｌ，Ｃｕ，Ｎ
ｉ，Ｇｅ，Ｇａ，Ｉｎ，Ｐ，Ｂｉ、及びＺｎの群から選
択された少なくとも１元素を含む少なくとも１種類のろ
う材で構成されていることを特徴とする半導体装置。12. The semiconductor device according to claim 10, wherein Sn, Ag, Au, Al, Cu, N is provided between the semiconductor element and the heat sink or between the heat sink and the wiring.
A semiconductor device comprising at least one type of brazing material containing at least one element selected from the group of i, Ge, Ga, In, P, Bi, and Zn. 【請求項１３】請求項１０に記載の半導体装置におい
て、前記酸化物粒子を含有した複合材料は、銅を母材と
し、酸化銅粒子が分散された複合材料であることを特徴
とした半導体装置。13. The semiconductor device according to claim 10, wherein the composite material containing the oxide particles is a composite material containing copper as a base material and copper oxide particles dispersed therein. . 【請求項１４】請求項１０に記載の半導体装置におい
て、前記放熱板または前記配線の少なくとも一方の表面
に、Ｎｉ，Ｓｎ，Ａｇ，Ａｕ，Ｐｔ，Ｐｄ，Ｚｎ、及び
Ｃｕの群から選択された少なくとも１種類の金属皮膜が
施されていることを特徴とする半導体装置。14. The semiconductor device according to claim 10, wherein at least one surface of the heat dissipation plate or the wiring is selected from the group of Ni, Sn, Ag, Au, Pt, Pd, Zn, and Cu. A semiconductor device having at least one kind of metal coating. 【請求項１５】請求項１０に記載の半導体装置におい
て、前記絶縁板は、有機系材料よりなることを特徴とす
る半導体装置。15. The semiconductor device according to claim 10, wherein the insulating plate is made of an organic material. 【請求項１６】請求項１０に記載の半導体装置におい
て、前記支持板は、アルミニウムまたはアルミニウム合
金で形成されることを特徴とした半導体装置。16. The semiconductor device according to claim 10, wherein the support plate is made of aluminum or an aluminum alloy. 【請求項１７】半導体素子，放熱板，配線が形成した支
持絶縁板が順次積層された半導体装置であって、前記放
熱板が酸化物粒子を含有した複合材料で形成され、前記
酸化物粒子が前記複合材料の母材の最表面から５μｍ以
内にも存在することを特徴とした半導体装置。17. A semiconductor device in which a semiconductor element, a heat dissipation plate, and a supporting insulating plate on which wirings are formed are sequentially laminated, wherein the heat dissipation plate is formed of a composite material containing oxide particles, and the oxide particles are A semiconductor device characterized by being present within 5 μm from the outermost surface of the base material of the composite material. 【請求項１８】請求項１７に記載の半導体装置におい
て、前記半導体素子と前記放熱板の間、或いは前記放熱
板と配線が形成した支持絶縁板の間はＳｎ，Ａｇ，Ａ
ｕ，Ａｌ，Ｃｕ，Ｎｉ，Ｇｅ，Ｇａ，Ｉｎ，Ｐ，Ｂｉ、
及びＺｎの群から選択された少なくとも１元素を含む少
なくとも１種類のろう材を用いて接合されていることを
特徴とする半導体装置。18. The semiconductor device according to claim 17, wherein Sn, Ag, and A are provided between the semiconductor element and the heat dissipation plate or between the heat dissipation plate and a support insulating plate on which wiring is formed.
u, Al, Cu, Ni, Ge, Ga, In, P, Bi,
And a semiconductor device that is bonded using at least one type of brazing material containing at least one element selected from the group consisting of Zn and Zn. 【請求項１９】請求項１７に記載の半導体装置におい
て、前記放熱板は、銅を母材とし、酸化銅粒子が分散さ
れた複合材料であることを特徴とした半導体装置。19. The semiconductor device according to claim 17, wherein the heat dissipation plate is a composite material containing copper as a base material and copper oxide particles dispersed therein. 【請求項２０】請求項１７に記載の半導体装置におい
て、前記放熱板の表面に、Ｎｉ，Ｓｎ，Ａｇ，Ａｕ，Ｐ
ｔ，Ｐｄ，Ｚｎ、及びＣｕの群から選択された少なくと
も１種類の金属皮膜が施されていることを特徴とする半
導体装置。20. The semiconductor device according to claim 17, wherein Ni, Sn, Ag, Au, P is formed on the surface of the heat dissipation plate.
A semiconductor device having at least one kind of metal film selected from the group consisting of t, Pd, Zn, and Cu. 【請求項２１】請求項１７に記載の半導体装置におい
て、前記配線が形成した支持絶縁板は、ガラスセラミッ
ク系材料で構成されていることを特徴とする半導体装
置。21. The semiconductor device according to claim 17, wherein the supporting insulating plate on which the wiring is formed is made of a glass ceramic material. 【請求項２２】半導体素子がリードフレーム上に積層さ
れ、前記半導体素子と前記リードフレームとが金属細線
で結線された半導体装置であって、前記リードフレーム
は酸化物粒子を含有した複合材料で形成され、前記酸化
物粒子が前記複合材料の母材の最表面から５μｍ以内に
も存在することを特徴とした半導体装置。22. A semiconductor device in which a semiconductor element is laminated on a lead frame, and the semiconductor element and the lead frame are connected by a fine metal wire, wherein the lead frame is made of a composite material containing oxide particles. And the oxide particles are present within 5 μm from the outermost surface of the base material of the composite material. 【請求項２３】請求項２２に記載の半導体装置におい
て、前記半導体素子と前記リードフレームの間はＳｎ，
Ａｇ，Ａｕ，Ａｌ，Ｃｕ，Ｎｉ，Ｇｅ，Ｇａ，Ｉｎ，
Ｐ，Ｂｉ、及びＺｎの群から選択された少なくとも１元
素を含む少なくとも１種類のろう材を用いて接合されて
いることを特徴とする半導体装置。23. The semiconductor device according to claim 22, wherein Sn is provided between the semiconductor element and the lead frame.
Ag, Au, Al, Cu, Ni, Ge, Ga, In,
A semiconductor device, which is bonded using at least one kind of brazing material containing at least one element selected from the group of P, Bi, and Zn. 【請求項２４】請求項２２に記載の半導体装置におい
て、前記放熱板は、銅を母材とし、酸化銅粒子が分散さ
れた複合材料であることを特徴とした半導体装置。24. The semiconductor device according to claim 22, wherein the heat dissipation plate is a composite material containing copper as a base material and copper oxide particles dispersed therein.
JP2001393042A 2001-12-26 2001-12-26 Semiconductor device and its manufacturing method Pending JP2003197825A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007299789A (en) * 2006-04-27 2007-11-15 Allied Material Corp Thermal dissipation substrate and manufacturing method thereof
WO2012144070A1 (en) * 2011-04-22 2012-10-26 三菱電機株式会社 Semiconductor device
JP2021015858A (en) * 2019-07-10 2021-02-12 株式会社デンソー Electronic device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007299789A (en) * 2006-04-27 2007-11-15 Allied Material Corp Thermal dissipation substrate and manufacturing method thereof
US8092914B2 (en) 2006-04-27 2012-01-10 A.L.M.T. Corp. Heat sink substrate and production method for the same
WO2012144070A1 (en) * 2011-04-22 2012-10-26 三菱電機株式会社 Semiconductor device
JP2021015858A (en) * 2019-07-10 2021-02-12 株式会社デンソー Electronic device
US11538733B2 (en) 2019-07-10 2022-12-27 Denso Corporation Electronic device
JP7255397B2 (en) 2019-07-10 2023-04-11 株式会社デンソー electronic device

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