WO1999044204A3 - Speicherzellenanordnung und entsprechendes herstellungsverfahren - Google Patents

Speicherzellenanordnung und entsprechendes herstellungsverfahren Download PDF

Info

Publication number
WO1999044204A3
WO1999044204A3 PCT/DE1999/000517 DE9900517W WO9944204A3 WO 1999044204 A3 WO1999044204 A3 WO 1999044204A3 DE 9900517 W DE9900517 W DE 9900517W WO 9944204 A3 WO9944204 A3 WO 9944204A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
semiconductor substrate
trench
memory cell
cell arrangement
Prior art date
Application number
PCT/DE1999/000517
Other languages
English (en)
French (fr)
Other versions
WO1999044204A2 (de
Inventor
Ulrich Zimmermann
Thomas Boehm
Manfred Hain
Armin Kohlhase
Yoichi Otani
Andreas Rusch
Alexander Trueby
Original Assignee
Siemens Ag
Ulrich Zimmermann
Thomas Boehm
Manfred Hain
Armin Kohlhase
Yoichi Otani
Andreas Rusch
Alexander Trueby
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Ulrich Zimmermann, Thomas Boehm, Manfred Hain, Armin Kohlhase, Yoichi Otani, Andreas Rusch, Alexander Trueby filed Critical Siemens Ag
Priority to EP99916757A priority Critical patent/EP1060474A2/de
Priority to JP2000533875A priority patent/JP2002505516A/ja
Publication of WO1999044204A2 publication Critical patent/WO1999044204A2/de
Publication of WO1999044204A3 publication Critical patent/WO1999044204A3/de
Priority to US09/645,763 priority patent/US6472696B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/40—ROM only having the source region and drain region on different levels, e.g. vertical channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Abstract

Die vorliegende Erfindung schafft eine Speicherzellenanordnung mit einer Vielzahl von in einem Halbleitersubstrat (10) vorgesehenen Speicherzellen (S) mit in Längsrichtung in der Hauptfläche des Halbleitersubstrats (10) parallel verlaufenden Bitleitungsgräben (1a-1d), in deren Böden jeweils ein erstes leitendes Gebiet (15a-15d) vorgesehen ist, in deren Kronen jeweils ein zweites leitendes Gebiet (20a-20e) vom gleichen Leitungstyp wie das erste leitende Gebiet vorgesehen ist und in deren Wänden jeweils ein dazwischenliegendes Kanalgebiet vorgesehen ist, und in Querrichtung entlang der Hauptfläche des Halbleitersubstrats (10) durch bestimmte Bitleitungsgräben (1a, 1c, 1d) verlaufende Wortleitungen (2a-2c) zur Ansteuerung von dort vorgesehenen Transistoren. In die Grabenwände der Bitleitungsgräben (1a-1d), welche zwischen den Wortleitungen (2a-2c) liegen, ist ein zusätzlicher Dotierstoff eingebracht, um dort die entsprechende Transistor-Einsatzspannung zur Unterdrückung von Leckströmen zu erhöhen.
PCT/DE1999/000517 1998-02-25 1999-02-25 Speicherzellenanordnung und entsprechendes herstellungsverfahren WO1999044204A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP99916757A EP1060474A2 (de) 1998-02-25 1999-02-25 Speicherzellenanordnung und entsprechendes herstellungsverfahren
JP2000533875A JP2002505516A (ja) 1998-02-25 1999-02-25 メモリセル装置及び相応の製造方法
US09/645,763 US6472696B1 (en) 1998-02-25 2000-08-25 Memory cell configuration and corresponding production process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19807920.6 1998-02-25
DE19807920A DE19807920A1 (de) 1998-02-25 1998-02-25 Speicherzellenanordnung und entsprechendes Herstellungsverfahren

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/645,763 Continuation US6472696B1 (en) 1998-02-25 2000-08-25 Memory cell configuration and corresponding production process

Publications (2)

Publication Number Publication Date
WO1999044204A2 WO1999044204A2 (de) 1999-09-02
WO1999044204A3 true WO1999044204A3 (de) 1999-10-14

Family

ID=7858873

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000517 WO1999044204A2 (de) 1998-02-25 1999-02-25 Speicherzellenanordnung und entsprechendes herstellungsverfahren

Country Status (6)

Country Link
US (1) US6472696B1 (de)
EP (1) EP1060474A2 (de)
JP (1) JP2002505516A (de)
KR (1) KR100604180B1 (de)
DE (1) DE19807920A1 (de)
WO (1) WO1999044204A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004063025B4 (de) * 2004-07-27 2010-07-29 Hynix Semiconductor Inc., Icheon Speicherbauelement und Verfahren zur Herstellung desselben
KR100771871B1 (ko) * 2006-05-24 2007-11-01 삼성전자주식회사 수직 채널 트랜지스터를 구비한 반도체 소자
KR101052871B1 (ko) * 2008-05-07 2011-07-29 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4214923A1 (de) * 1991-05-31 1992-12-03 Mitsubishi Electric Corp Masken-rom-einrichtung und verfahren zu deren herstellung
JPH05343680A (ja) * 1992-06-10 1993-12-24 Kawasaki Steel Corp 半導体装置の製造方法
US5448090A (en) * 1994-08-03 1995-09-05 International Business Machines Corporation Structure for reducing parasitic leakage in a memory array with merged isolation and node trench construction
DE19514834C1 (de) * 1995-04-21 1997-01-09 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226071A (ja) * 1990-05-16 1992-08-14 Ricoh Co Ltd 半導体メモリ装置
DE19510042C2 (de) * 1995-03-20 1997-01-23 Siemens Ag Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung
DE19609678C2 (de) * 1996-03-12 2003-04-17 Infineon Technologies Ag Speicherzellenanordnung mit streifenförmigen, parallel verlaufenden Gräben und vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
DE19732871C2 (de) * 1997-07-30 1999-05-27 Siemens Ag Festwert-Speicherzellenanordnung, Ätzmaske für deren Programmierung und Verfahren zu deren Herstellung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4214923A1 (de) * 1991-05-31 1992-12-03 Mitsubishi Electric Corp Masken-rom-einrichtung und verfahren zu deren herstellung
JPH05343680A (ja) * 1992-06-10 1993-12-24 Kawasaki Steel Corp 半導体装置の製造方法
US5448090A (en) * 1994-08-03 1995-09-05 International Business Machines Corporation Structure for reducing parasitic leakage in a memory array with merged isolation and node trench construction
DE19514834C1 (de) * 1995-04-21 1997-01-09 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 018, no. 174 (E - 1530) 24 March 1994 (1994-03-24) *

Also Published As

Publication number Publication date
EP1060474A2 (de) 2000-12-20
JP2002505516A (ja) 2002-02-19
DE19807920A1 (de) 1999-09-02
US6472696B1 (en) 2002-10-29
KR20010041278A (ko) 2001-05-15
KR100604180B1 (ko) 2006-07-25
WO1999044204A2 (de) 1999-09-02

Similar Documents

Publication Publication Date Title
CN100359695C (zh) 无电容单一晶体管动态随机存取存储器单元及制造方法
US6586798B1 (en) High voltage MOS-gated power device
CN1158711C (zh) 存储器单元
EP1166363B1 (de) Graben-dmos-transistorstruktur mit pfad mit niedrigem widerstand zu einem drainkontakt auf einer oberen oberfläche
Maeda et al. A Vertical/spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond
US20030151112A1 (en) Semiconductor device having one of patterned SOI and SON structure
TW357435B (en) 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
GB2364171B (en) Column transistor in semiconductor device
US4972371A (en) Semiconductor memory device
CN1213857A (zh) 减小器件制备中的氧化应力
US6310800B1 (en) Non-volatile semiconductor memory device and method for driving the same
KR970018605A (ko) 다이나믹 이득 메모리셀을 가진 dram 셀 어레이
KR940020574A (ko) 반도체 기억장치(semiconductor memory device)
KR100327348B1 (en) Semiconductor capable of decreasing junction leakage current and narrow width effect and fabricating method thereof
TW363270B (en) Buried bit line DRAM cell and manufacturing method thereof
US4942554A (en) Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same
KR960019727A (ko) 반도체 메모리장치 및 그 제조방법
WO1999044204A3 (de) Speicherzellenanordnung und entsprechendes herstellungsverfahren
US7524715B2 (en) Memory cell transistor having different source/drain junction profiles connected to DC node and BC node and manufacturing method thereof
TW200605351A (en) Memory device and method for fabricating the same
US6750509B2 (en) DRAM cell configuration and method for fabricating the DRAM cell configuration
TW360954B (en) Read-only memory structure and method of fabricating the same
US5241495A (en) Semiconductor memory
TW349265B (en) Method to produce a memory-cell arrangement
JP2682411B2 (ja) 半導体記憶装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): BR CN IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A3

Designated state(s): BR CN IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1020007009376

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 1999916757

Country of ref document: EP

Ref document number: 09645763

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1999916757

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020007009376

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1020007009376

Country of ref document: KR