WO1999038213A1 - Dispositif memoire et procede de fabrication correspondant, et circuit integre et procede de fabrication correspondant - Google Patents
Dispositif memoire et procede de fabrication correspondant, et circuit integre et procede de fabrication correspondant Download PDFInfo
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- WO1999038213A1 WO1999038213A1 PCT/JP1999/000313 JP9900313W WO9938213A1 WO 1999038213 A1 WO1999038213 A1 WO 1999038213A1 JP 9900313 W JP9900313 W JP 9900313W WO 9938213 A1 WO9938213 A1 WO 9938213A1
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- insulating film
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Definitions
- the present invention relates to a memory element and a method of manufacturing the same, and an integrated circuit and a method of manufacturing a semiconductor device.
- the present invention relates to a memory element for retaining information by accumulating charges transferred from a conduction region in an accumulation region, a method for manufacturing the same, and an integrated circuit and a method for manufacturing a semiconductor device in which the memory elements are integrated.
- the present invention relates to a memory element in which a storage region is composed of a plurality of fine particles (quantum dots) and a method of manufacturing the same, and a method of manufacturing an integrated circuit and a semiconductor device.
- a storage region is formed via an insulating film on a conductive region formed on the surface of a single crystal silicon substrate, and the storage region is formed in the storage region.
- the information is retained by storing the transition charge by tunneling from the conduction region to the insulation film.
- this accumulation region is formed of a continuous semiconductor film having a two-dimensional spread.
- a thermally oxidized silicon thermal oxide film is used as an insulating film between the conductive region and the storage region in order to retain the charge stored in the storage region for a long time. Was used.
- This thermal oxide film is formed by raising the temperature of the single-crystal silicon substrate to a high temperature of 800 to 100 ° C. in an oxygen atmosphere.
- the silicon substrate does not deform or melt at such a temperature.
- the thermal oxide film formed on the single crystal silicon substrate has extremely excellent insulating properties, charges are stably retained without leaking from the two-dimensionally continuous accumulation region.
- the substrate temperature must be raised to 800 to 100 ° C. I got it.
- the substrate is made of glass or plastic (plastic) instead of single crystal silicon, such high temperature heat treatment is not possible.
- the deformation temperature of a glass substrate is 500 ° C. The temperature is at most 200, even when formed by a refractory material. C. Therefore, when the substrate is formed of glass or plastic, the insulating film between the conductive region and the storage region must be formed at a low temperature of 500 ° C. or less.
- the conduction region on the oxide film is a polycrystalline silicon, there are irregularities on the surface I do. Due to the unevenness of the polycrystalline silicon, electric field concentration occurs in the insulating film thereon, and the electric charge in the two-dimensionally continuous accumulation region leaks from that location. Disclosure of the invention
- the present invention has been made in view of such a problem, and an object of the present invention is to be able to manufacture information on a glass or plastic substrate at a low temperature and to retain information for a long time.
- An object of the present invention is to provide a memory element and a method for manufacturing the same, and a method for manufacturing an integrated circuit and a semiconductor device.
- a memory element includes a conductive region formed of a semiconductor, a first impurity region provided adjacent to the conductive region, and a first impurity region separated from the first impurity region and adjacent to the conductive region.
- a second impurity region provided, a plurality of dispersed fine particles, and a storage region for storing charges transitioned from the conduction region; and a charge provided between the storage region and the conduction region is capable of transition.
- Another memory element includes a conductive region made of a semiconductor, a first impurity region provided adjacent to the conductive region, and a first impurity region separated from the first impurity region and adjacent to the conductive region.
- a second impurity region provided, a plurality of dispersed fine particles, and a storage region for storing charges transitioned from the conduction region; and a charge provided between the storage region and the conduction region.
- a tunnel insulating film capable of transition a control electrode for controlling a charge amount of the storage region and a conductivity of the conduction region, respectively, and a control insulating film provided between the control electrode and the storage region.
- the number of fine particles in the accumulation area is 5 or more.
- Still another memory element includes a conductive region formed of a semiconductor, a first impurity region provided adjacent to the conductive region, and a first impurity region separated from the first impurity region and adjacent to the conductive region.
- a second impurity region provided as a semiconductor, a storage region including a plurality of dispersed fine particles, and storing a charge transitioned from the conductive region; and a charge provided between the storage region and the conductive region.
- a control electrode for controlling the amount of charge in the storage region and the conductivity of the memory conduction region, respectively, and a control insulation provided between the control electrode and the storage region.
- the conductive region is formed by a polycrystalline silicon film having a surface roughness of at least 0.11 ⁇ 1 and not more than 100 nm, and the number of fine particles in the storage region is reduced by the crystal in the conductive region. It is configured to have more than the number of grains It is.
- An integrated circuit includes a plurality of memory elements, each memory element having a conduction region formed of a semiconductor, a source region provided adjacent to the conduction region, and being separated from the source region; A drain region provided adjacent to the conductive region, a storage region including a plurality of dispersed fine particles, and storing the charge transitioned from the conductive region; and a storage region provided between the storage region and the conductive region.
- a tunnel insulating film capable of transitioning charges; a control electrode for controlling a charge amount of the storage region and a conductivity of the conduction region; and a control insulating film provided between the control electrode and the storage region.
- the surface density of the fine particles in the storage region is larger than the surface density of the structural holes (pinholes) generated in the tunnel insulating film, and the control electrode of each memory element has a work electrode. And a source / drain path of each memory element is connected between the bit line and the source line.
- a method of manufacturing a memory element includes the steps of: forming a conductive region made of a semiconductor film on a base portion made of an insulator; forming a tunnel insulating film on the conductive region; Forming a storage region comprising a plurality of fine particles dispersed in a region, and having a surface density of the fine particles larger than a surface density of a structural hole (pinhole) of the tunnel insulating film; Forming a control electrode on the control insulating film; forming a control electrode on the control insulating film; separating the control electrode from the first impurity region and the first impurity region adjacent to the conductive region; Forming a second impurity region adjacent to the region.
- Another method for manufacturing a memory element according to the present invention includes a step of forming a conductive region made of a semiconductor film on a base portion made of an insulator; a step of forming a tunnel insulating film on the conductive region; A step of forming an accumulation region composed of five or more fine particles dispersed on the insulating film, a step of forming a control insulating film on the accumulation region, and a step of controlling on the control insulating film
- the method includes a step of forming an electrode, and a step of forming a first impurity region adjacent to the conductive region and a second impurity region separated from the first impurity region and adjacent to the conductive region.
- a conductive region formed of a polycrystalline silicon film having a surface roughness of 0.1111 to 100 nm is formed on a base portion made of an insulator.
- Still another method of manufacturing a memory element according to the present invention includes the steps of: forming a control electrode on a base portion made of an insulator; forming a control insulating film on the control electrode; Forming a storage region on the film, the storage region being composed of a plurality of dispersed fine particles, and having a surface density of the fine particles greater than a surface density of structural holes (pinholes) of the tunnel insulating film; Forming a tunnel insulating film on the semiconductor substrate; forming a conductive region made of a semiconductor on the tunnel insulating film; Forming a first impurity region and a second impurity region separated from the first impurity region and adjacent to the conductive region.
- Still another method of manufacturing a memory element according to the present invention includes the steps of: forming a control electrode on a base portion made of an insulator; forming a control insulating film on the control electrode; Forming a storage region consisting of five or more fine particles dispersed on the film, forming a tunnel insulating film on the storage region, and forming a conductive region made of semiconductor on the tunnel insulating film. Forming the first impurity region and the first impurity region adjacent to the conductive region, and forming a second impurity region adjacent to the conductive region.
- Still another method of manufacturing a memory element according to the present invention includes the steps of: forming a control electrode on a base portion made of an insulator; forming a control insulating film on the control electrode; Forming a storage region composed of a plurality of dispersed fine particles on the film, forming a tunnel insulating film on the storage region, and forming a conductive region composed of a semiconductor on the tunnel insulating film And forming a first impurity region adjacent to the conductive region and a second impurity region adjacent to the conductive region, the first impurity region being separated from the first impurity region and the first impurity region. It is formed of a polycrystalline silicon film having a surface roughness of 0.1 nm or more and 100 nm or less, and the number of fine particles in the accumulation region is larger than the number of crystal grains in the conduction region.
- a method of manufacturing a semiconductor device includes, after forming a semiconductor film on a substrate, forming a film for forming a storage region having a non-stoichiometric composition containing an excessive amount of a semiconductor element on the semiconductor film; Performing a heat treatment to disperse semiconductor fine particles in the accumulation region forming film to form an accumulation region.
- the “non-stoichiometric composition” refers to a composition having a component ratio deviating from the stoichiometric composition, and in the present invention, the component ratio is set so as to include a semiconductor in excess as compared with the case of the stoichiometric composition. Is off.
- the fine particles forming the accumulation region are fine particles having a size in the range of l nm to l On m, and examples thereof include silicon (Si) and germanium (Ge).
- the areal density of the fine particles in the storage region is larger than the areal density of the structural holes (pinholes) generated in the tunnel insulating film.
- the number of particles in the accumulation region is larger than the number of crystal grains in the conduction region, charges accumulated in some particles leak due to defects such as pinholes in the tunnel insulating film.
- the charge accumulated in the fine particles formed in the region where no defect exists does not leak. Therefore, information is accumulated for a long time.
- a heat treatment such as energy beam irradiation is performed on the film for forming a storage region having a non-stoichiometric composition containing an excessive amount of semiconductor, thereby forming The semiconductor particles are dispersed therein, forming an accumulation region.
- FIG. 1 is a cross-sectional view illustrating a configuration of a memory element according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view illustrating a configuration of a memory element according to a second embodiment of the present invention.
- FIG. 3 is a circuit diagram for explaining an example of a first integration method of a memory element of the present invention.
- FIG. 4 is a circuit diagram for explaining another example of the first integration method of the memory element of the present invention.
- FIG. 5 is a circuit diagram for explaining a second integration method of the memory element of the present invention.
- 6A and 6B are a cross-sectional view and a plan view for explaining the first method for manufacturing the memory element according to the first embodiment.
- 7A and 7B are a cross-sectional view and a plan view for explaining a step following the steps in FIGS. 6A and 6B.
- 8A and 8B are a cross-sectional view and a plan view for explaining a step following the steps in FIGS. 7A and 7B.
- 9A and 9B are a cross-sectional view and a plan view for explaining a step following the steps in FIGS. 8A and 8B.
- FIG. 10A and FIG. 10B are a cross-sectional view and a plan view for explaining a step following FIG. 9A and FIG. 9B.
- FIGS. 11A and 11B are a cross-sectional view and a plan view for explaining a second method for manufacturing the memory element according to the first embodiment of the present invention.
- FIG. 12A and FIG. 12B are a cross-sectional view and a plan view for explaining a step following FIG. 11A and FIG. 11B.
- FIG. 13A and FIG. 13B are a cross-sectional view and a plan view for explaining a step following FIG. 12A and FIG. 12B.
- FIG. 14A and FIG. 14B are a cross-sectional view and a plan view for explaining a step following FIG. 13A and FIG. 13B.
- FIG. 15 is a characteristic diagram showing a relationship between a gate voltage and a drain current of the memory element according to the first embodiment.
- FIG. 16A and FIG. 16B are a cross-sectional view and a plan view for explaining the third manufacturing method of the memory element according to the first embodiment.
- FIG. 17A and FIG. 17B are a cross-sectional view and a plan view for explaining a step following FIG. 16A and FIG. 16B.
- FIG. 18A and FIG. 18B are a cross-sectional view and a plan view for explaining a step following FIG. 17A and FIG. 17B.
- FIG. 19A and FIG. 19B are a cross-sectional view and a plan view for explaining a step following FIG. 18A and FIG. 18B.
- FIG. 20A and FIG. 20B are a cross-sectional view and a plan view for explaining a step following FIG. 19A and FIG. 19B.
- FIG. 21A and FIG. 21B are a cross-sectional view and a plan view for explaining a manufacturing process of the memory element according to the second embodiment of the present invention.
- FIG. 22A and FIG. 22B are a cross-sectional view and a plan view for explaining a step following FIG. 21A and FIG. 21B.
- Figures 23A and 23B illustrate the steps following Figure 22A and Figure 22B. It is sectional drawing and a top view for clarity.
- FIG. 24A and FIG. 24B are a cross-sectional view and a plan view for explaining a step following FIG. 23A and FIG. 23B.
- FIG. 25A and FIG. 25B are a cross-sectional view and a plan view for explaining a step following FIG. 24A and FIG. 24B.
- FIG. 26 is a plan view showing the configuration of a memory device according to the third embodiment of the present invention.
- FIG. 27 is a plan view of FIG. It is sectional drawing along the? Line.
- FIG. 28 is a sectional view of the memory device according to the fourth embodiment of the present invention.
- FIG. 29 is a plan view illustrating a configuration of a memory device according to a fifth embodiment of the present invention.
- FIG. 30 is a cross-sectional view of FIG. 29 taken along the line —.
- FIG. 31 is a cross-sectional view of a memory device including an element having a bottom gate structure.
- FIG. 32 is a plan view illustrating a configuration of a memory device according to a sixth embodiment of the present invention.
- FIG. 33 is a cross-sectional view taken along line 1-1 of FIG.
- FIG. 34 is a cross-sectional view of a memory device including an element having a bottom gate structure.
- FIG. 35 is a cross-sectional view for explaining a manufacturing step of the memory device according to the seventh embodiment of the present invention.
- FIG. 36 is a cross-sectional view for explaining a step following FIG. 35.
- FIG. 37 is a cross-sectional view for explaining a step following FIG.
- FIG. 38 is a cross-sectional view for explaining a step following FIG. 37.
- FIG. 39 is a cross-sectional view for explaining a step following FIG.
- FIG. 40 is a cross-sectional view for explaining a manufacturing step of the memory device according to the eighth embodiment of the present invention.
- FIG. 41 is a cross-sectional view for explaining a step following FIG. 40.
- FIG. 42 is a cross-sectional view for explaining a step following FIG. 41.
- FIG. 43 is a cross-sectional view for explaining a step following FIG. 42.
- FIG. 44 is a cross-sectional view for explaining a step following FIG. 43.
- FIG. 45 is a cross-sectional view for explaining a step following FIG.
- FIG. 46 is a cross-sectional view for explaining a manufacturing step of the memory device according to the ninth embodiment of the present invention.
- FIG. 47 is a cross-sectional view for explaining a step following FIG. 46.
- FIG. 48 is a cross-sectional view for explaining a step following FIG. 47.
- FIG. 49 is a cross-sectional view for explaining a step following FIG. 48.
- FIG. 50 is a cross-sectional view for explaining a step following FIG. 49.
- FIG. 51 is a cross-sectional view for explaining a step following FIG. 50.
- FIG. 52 is a cross-sectional view for explaining a step following FIG. 51.
- FIG. 53A to FIG. 53C are cross-sectional views for each step for explaining an experimental example of the present invention.
- FIG. 54 is an SEM photograph for explaining the formation state of silicon dots (particles).
- FIG. 55A to FIG. 55D are cross-sectional views for each step for explaining the manufacturing process of the silicon dot memory.
- FIG. 56A and FIG. 56B are cross-sectional views for each step following FIG. 55D.
- FIG. 1 shows a basic configuration of a memory device according to a first embodiment of the present invention.
- a case where electrons are used as charges will be described as an example.
- holes are used as charges, the signs of potentials may be reversed.
- the memory element according to the present embodiment includes a conductive region 13 c on a buffer layer 12 formed on a substrate 11 made of a non-silicon material such as quartz, glass, plastic, or the like. It has a configuration including a first impurity region 13a and a second impurity region 13b formed adjacent to both sides of 13c, respectively.
- Buffer layer 1 2 is constituted by an insulating film such as S i 0 2 or S i 3 N 4.
- the first impurity region 13a, the second impurity region 13b, and the conduction region 13c are each formed of, for example, a polycrystalline silicon layer 13 having a thickness of about several tens nm.
- the first impurity region 13 a and the second impurity region 13 b are respectively formed in the polycrystalline silicon layer 13 by, for example, a group V element such as phosphorus (P) or n-type impurity as an n-type impurity. It is composed by adding a group III element such as boron (B) as a type impurity.
- the first impurity region 13a, the second impurity region 13b, and the conduction region 13c may be semiconductors (non-single-crystal semiconductors) other than a single-crystal semiconductor.
- An insulating film 14 is provided at a position directly above the conduction region 13c.
- the insulating film 14 is composed of a tunnel insulating film 14a and a control insulating film 14b laminated on the tunnel insulating film 14a. These tunnel insulating film 1 4 a and the control insulating film 1 4 b is formed by a respective S i 0 2, S i 3 N 4 or S i N k O i (k , 1 ⁇ 0). Between the tunnel insulating film 14a and the control insulating film 14b, an accumulation region 15 for holding electric charges (here, electrons) is provided.
- the thickness of the tunnel insulating film 14a is large (for example, less than 5 nm) such that electrons can transit through the tunnel insulating film 14a to the accumulation region 15 by the quantum mechanical tunnel effect.
- the accumulation region 15 is composed of a plurality of fine particles (quantum dots) 15a arranged discretely.
- the particles 1 5 a is, S i y G e y ( 0 ⁇ y ⁇ 1), S i F e 2, II one VI, semiconductor particles such as group III-V compound, A u, S b, S n , etc.
- the number (area density) of the fine particles 15a is determined by a tunnel in the manufacturing process.
- the surface density of the structural holes (pinholes) generated in the insulating film 14a is larger than the specific density, specifically, five or more.
- control electrode 16 is formed on the insulating film 14, that is, at a position opposite to the conduction region 13 c with the storage region 15 as the center.
- the control electrode 16 is made of, for example, a metal such as aluminum (A 1) or a low-resistance polycrystalline silicon layer doped with impurities.
- the thickness of the control insulating film 14 b between the control electrode 16 and the storage region 15 is such that electrons cannot transition through the control insulating film 14 b due to the quantum mechanical tunneling effect. (For example, 50 nm or more).
- the second impurity region 13b is made the same as the first impurity region 13a.
- a potential (0 V) or a potential higher than the second impurity region 13 a eg, 10 V
- the potential of the first impurity region 13 a is applied to the control electrode 16.
- a high potential for example, 20 V
- the charge (electrons) in the conduction region 13c transitions through the tunnel insulating film 14a between the conduction region and the storage region by quantum mechanical tunneling.
- the particles are accumulated in the dispersed fine particles 15 a in the accumulation region 15. As a result, information is written.
- the second impurity region 13b has the same potential as the first impurity region 13a (0 V) or a potential lower than the first impurity region 13a (eg, ⁇ 10 V) is applied to the control electrode 16 as well as the potential of the first impurity region 13a.
- a low potential for example, ⁇ 20 V
- the charges (holes) in the conduction region 13 c transit through the tunnel insulating film 14 a between the conduction region and the storage region by quantum mechanical tunnel effect.
- the particles are accumulated in the plurality of fine particles 15a dispersed in the accumulation region 15.
- information is written.
- the information written in this way sets the potentials of all the electrodes to the same potential or Is held in a floating state.
- the accumulation region 15 is composed of five or more dispersed fine particles 15a, the structural defect existing in the tunnel insulating film 14a causes Even if the charges accumulated in some of the fine particles 15a leak, the charges accumulated in the fine particles 15a formed in the region where no defect exists in the tunnel insulating film 14a do not leak. Therefore, in the present embodiment, the information stored in the storage area 15 is held for a long time. This is because the surface roughness of the polycrystalline silicon layer 13 is in the range of 0.111111 or more and 10 Onm or less, and the number of fine particles 15a in the accumulation region 15 is smaller than that of the conduction region 1. The same applies to the case where the number is larger than the number of crystal grains in 3c.
- the tunnel insulating film can be formed by a low-temperature process, and an inexpensive material such as glass or plastic can be used as the substrate.
- the written information indicates that the second impurity region 13 b is the first impurity region 13 a
- a potential for example, ⁇ 20 V
- the potential held in the storage region 15 is maintained.
- the charge (electrons) transitions through the tunnel insulating film 14a between the conduction region and the storage region, is pulled out to the conduction region 13c, and is erased.
- the second impurity region 13b has the same potential as the first impurity region 13a.
- a potential for example, 20 V
- the charges (holes) retained in the fine particles 15a of the storage region 15 transition through the tunnel insulating film 14a between the conduction region and the storage region and are drawn out to the conduction region 13c. The information will be erased.
- the written information is read out by measuring the conductivity or the current value of the conductive region 13c with respect to the potential of the control electrode 16 to detect the change in the amount of charge in the storage region 15 and reading it out.
- FIG. 2 shows a configuration of a memory device according to a second embodiment of the present invention.
- the memory element 2 0, for example, on the substrate 2 1 of quartz, S i 0 2 or S i 3 N 4 or the like made of an insulating film buffer layer 2 2 through the control electrode (control electrode) 2 It has six.
- the insulating film 24 is composed of a control insulating film 24b and a tunnel insulating film 24a laminated on the control insulating film 24b. Between the tunnel insulating film 24a and the control insulating film 24b, a storage region 25 made up of a plurality of discretely arranged fine particles 25a is provided. On the insulating film 24, a conductive region 23c and a first impurity region 23a and a second impurity region 2 provided adjacent to both sides of the conductive region 23a, respectively. 3b is provided. These first impurity region 23 a, second impurity region 23 b and conduction region 23 c are formed in polycrystalline silicon layer 23.
- the memory device of this embodiment has the other configuration and operation (information writing method) except that the memory device of the first embodiment is a so-called top gate type while a memory device of the first embodiment is a bottom gate type. And the erasing method, and the information holding method and the reading method) and the effects are substantially the same as those of the first embodiment, and the description thereof is omitted.
- FIG. 3 and FIG. 4 are circuit diagrams for explaining a first integration method of the memory element.
- a gate electrode of each memory element is connected to a ground line
- a source-drain path is connected between a bit line and a source line
- a plurality of these memory elements are arranged in parallel. Is what you do.
- FIG. 5 shows a circuit configuration when the above-mentioned memory element is similarly integrated by the second method.
- a gate electrode of each memory element is connected to a word line, and a source-drain path is connected between a bit line and a source line, respectively, and a plurality of these memory elements are arranged in series. The operation of the memory device integrated by these methods will be described later.
- FIG. B shows a plan view
- FIG. A shows a cross-sectional view taken along line ⁇ - ⁇ of FIG.
- a CVD (Chemical Vapor Deposition) method is applied on an insulating substrate, for example, a substrate 11 made of quartz, glass, plastic, or the like.
- a buffer layer 12 composed of, for example, an Si 3 N 4 layer or an SiO 2 layer having a thickness of about 100 nm is formed by a sputtering method.
- the substrate temperature is set to 600 to 700 ° C.
- a polycrystalline silicon layer 13 having a thickness of about several 10 nm is formed by, for example, a CVD method or a sputtering method, and then the elements are separated by etching. I do.
- a defect composed of a hole (pinhole) 10 usually occurs in the polycrystalline silicon layer 13.
- the substrate surface is oxidized by exposing the substrate surface to an oxygen ionized gas generated by a thermal oxidation method or by introducing oxygen into an AC electromagnetic field.
- the surface of the polycrystalline silicon layer 13 (conductive region Ch i) is oxidized by a thickness of about 10 nm to form a tunnel insulating film 14a.
- a large number of holes (pinholes) are generated in the tunnel insulating film 14a due to the holes 10 in the polycrystalline silicon layer 13 as described above.
- a gas containing a silicon atom such as SiH 4 (silane) and Si 2 H 6 (disilane) and N 20 (nitrous oxide), O 2 (oxygen) by chemical vapor deposition using a gas containing oxygen atoms, or N 2 0, 0 2
- the control insulating film 14b having a thickness of about 100 nm is formed by sputtering silicon in an ionized gas atmosphere of a gas containing oxygen atoms.
- the conduction region 13 c (polycrystalline silicon layer 1) on the control insulating film 14 b is made of polycrystalline silicon or a metal such as A 1 (aluminum), Cu (copper), or W (tungsten).
- a control electrode (gate electrode) 16 is formed at a position opposite to the above. Then, using the control electrode 16 as a mask, RIE (Reactive Ion) using a mixed gas of CF 4 (carbon tetrafluoride) and H 2 (hydrogen) up to the surface of the conduction region (polycrystalline silicon layer 13). Selective etching of the control insulating film 14b was performed by etching (reactive ion etching).
- Ion implantation involves ion implantation of group V atoms, such as phosphorus (P) atoms, if the conduction charge is converted into electrons, and group III atoms, such as boron (B) atoms, if the conduction charge is converted into holes.
- group V atoms such as phosphorus (P) atoms
- group III atoms such as boron (B) atoms
- ionized gas containing a mule group V atoms Do for conduction charges in electronic, for example an ionized gas of PH 3, ionized gas containing if group III atoms to the conducting charge to the hole, for example, ionization of B 2 H 6
- the first impurity region 13a and the second impurity region 13b can be formed by irradiating the polycrystalline silicon layer 13 with a gas using the control electrode 16 as a mask. Thereafter, the element is heated using an electric furnace or an excimer laser to activate the implanted impurities. Thereafter, although not shown, for example, the surface of the memory element thus formed is formed on the surface of the memory element thus formed by a CVD method or a sputtering method. i 3 N 4 or to form a coercive Mamorumaku consisting S i 0 2.
- FIG. B shows a plan view
- FIG. A shows a cross-sectional view taken along line 5--B of FIG.
- the buffer layer 12 composed of, for example, a Si 3 N 4 layer or a SiO 2 layer having a thickness of about 100 nm is formed by CVD or sputtering. Subsequently, the amorphous silicon layer 13 'having a film thickness of about 10 nm is reduced by plasma CVD (Plasma Enhanced Chemical Vapor Deposition; PEC VD) or sputtering to such an extent that the substrate 11 is not deformed. After forming at a temperature, element isolation is performed by etching. Next, as shown in FIGS.
- the surface of the amorphous silicon layer 13 ' is oxidized by the plasma oxidation method, and the film thickness of 10 forming a tunnel insulating film 1 4 a of 3 10 31 layers of 11111 (X twice as), then Ri by the X e C 1 excimer laser to irradiate 1 5 0-3 about 0 Om J / cm 2 Then, the amorphous silicon layer 13 ′ is crystallized to form a polycrystalline silicon layer 13. This and can, excess silicon is deposited in S i O sigma, the accumulation area 1 5 consisting of a large number of fine particles 1 5 a is formed.
- a gas containing a silicon atom such as silane or disilane and a germanium atom such as germane are used.
- the accumulation region 15 may be formed so that the coverage is less than 1 by a chemical vapor deposition method using a gas containing the material or a sputtering method using silicon, germanium, or a metal as a material.
- a chemical vapor deposition method using a gas containing silicon atoms such as silane and disilane and a gas containing oxygen atoms such as N 20 and O 2 a control insulating film 14b having a thickness of about 100 nm is formed by sputtering silicon in an ionized gas atmosphere of a gas containing an oxygen atom such as N 20 or O 2 .
- a control electrode 1 is formed of polycrystalline silicon or a metal such as A1, Cu, W, etc., at a position on the control insulating film 14b opposite to the conductive region 13c of the polycrystalline silicon layer 13c.
- the control insulating film 14 b is selectively etched by RIE using a mixed gas of CF 4 and H 2 up to the surface of the conduction region (polycrystalline silicon layer 13). .
- ion implantation is performed using the control electrode 16 as a mask, and the first impurity region 13 a and the like are formed in the polycrystalline silicon layer 13. Yo And a second impurity region 13b.
- ion implantation is performed using a group V atom such as a phosphorus (P) atom if the conductive charge is an electron, and a group III atom such as boron (B) if the conductive charge is a hole. Atoms are ion-implanted.
- ionized gas containing if if group V atoms to the heat conductive charge in electronic for example an ionized gas of PH 3, ionized gas containing if if the group III atoms to the conducting charge to the hole, for example, electrodeposition of B 2 H 6
- the first impurity region 13a and the second impurity region 13b can also be formed by irradiating the polycrystalline silicon layer 13 with the separated gas using the control electrode 16 as a mask. Then, the element is heated using an electric furnace or an excimer laser to activate the implanted impurities. Thereafter, although not shown, for example, CVD or sputtering ring method, S i 3 N 4 or the surface of the thus memory element formed to form a protective film made of S i 0 2.
- FIG. 15 shows the gate voltage-drain current characteristics (memory effect) of the memory device manufactured according to the above embodiment.
- the drain voltage is 5 V.
- a Si Oo. 5 layer is formed by a PE CVD method, and then irradiated with a Xe C 1 excimer laser having an energy density of 26 OmJZcm 2 to form a Si 0.
- a storage region consisting of a dot is formed.
- phosphorus (P) ions are implanted by plasma irradiation of PH 3 to form a first impurity region and a second impurity region. Annealing was performed using a 1 excimer laser (21 Om J / cm 2 ) to activate the implanted impurities.
- FIG. B shows a plan view
- FIG. A shows a cross-sectional view taken along line 7 of FIG.
- a Si 3 N 4 layer having a thickness of about 100 nm is formed on a substrate 11 made of quartz or the like by CVD or sputtering. or by forming a buffer layer 1 2 consisting of S i 0 2 layers.
- an amorphous silicon layer having a thickness of about 10 nm doped with an n-type or p-type impurity by PEC VD or sputtering is heated to a temperature at which the substrate 11 is not deformed.
- the amorphous silicon layer is selectively removed by etching to form a first impurity region 13a and a second impurity region 13b.
- the surface of the polycrystalline silicon layer 13 was oxidized by a plasma oxidation method, and a film thickness of 310] 1-layer tunnel insulating film to form a 1 4 a consisting of (X rather 2), then, X e C 1 excimer irradiation 1 5 0 ⁇ 3 0 OmJ / cm 2 about an tHE.
- X e C 1 excimer irradiation 1 5 0 ⁇ 3 0 OmJ / cm 2 about an tHE.
- excess silicon in S i 0 ⁇ is deposited, and an accumulation region 15 composed of many fine particles 15 a is formed.
- the silane a gas that contains a gel Maniumu atoms such as gas and germane containing silicon atoms such as disilane as a raw material chemical
- the accumulation region 15 having a coverage of less than 1 may be formed by a vapor deposition method or a sputtering method using silicon, germanium, or a metal as a raw material.
- a control electrode is formed at a position facing the conduction region 13 c (polycrystalline silicon layer 13) on the control insulating film 14 b by using polycrystalline silicon or a metal such as A 1, Cu, or W.
- the control insulating film 14 b is selectively etched by RIE using a mixed gas of CF 4 and H 2 up to the surface of the conduction region (polycrystalline silicon layer 13). .
- the element is heated using an electric furnace or an excimer laser to activate the injected impurities.
- a protective film consisting of S ia N 4 or S i 0 2 on the surface of the memory element formed as described above.
- FIG. B shows a plan view
- FIG. A shows a cross-sectional view taken along line f-B of FIG.
- a substrate 21 made of quartz, glass or plastic is formed on a substrate 21 made of quartz, glass or plastic by a CVD or sputtering method, for example, with a film thickness of about 100 nm.
- the buffer layer 22 composed of the i 3 N 4 layer, the S i 0 2 layer, or the S i N k 0, (k, 1 ⁇ 0) layer is formed.
- a metal film made of W (tungsten), Ta (tantalum), Mo (molybdenum), or the like is formed by, for example, an electron beam evaporation method, and the control electrode 26 is formed by patterning. .
- control insulating film 24 b composed of a SiO 2 layer having a thickness of about 100 nm was formed by the CVD method or the sputtering method.
- a 10-nm thick tunnel insulating film 24a composed of a Si0, (x ⁇ 2) layer and a 10-nm-thick amorphous silicon layer 23 'with no impurity added are formed in this order.
- the polycrystalline silicon layer 23 and the tunnel insulating film 24a are selectively removed by, for example, RIE to perform element isolation. Do.
- the polycrystalline silicon layer on the 2 3, photoresists in a region facing the control electrode 2 6 or S i 0 2 consists mask Form 2 7
- ion implantation is performed using the mask 27 to form a first impurity region 23 a and a second impurity region 23 b in the polycrystalline silicon layer 23.
- a group V atom for example, a phosphorus (P) atom if the conduction charge is converted into an electron
- a group III for example, boron (B) atom if the conduction charge is converted into a hole.
- ionized gas containing if if group V atoms to conduction charges in electronic ionized gas of PH 3
- an ionized gas containing the group III atoms if the conducting charge to the hole for example, ionization of B 2 H e
- the first impurity region 23a and the second impurity region 23b can be formed by irradiating the polycrystalline silicon layer 23 with a gas using the mask 27. Thereafter, the element is heated using an electric furnace or an excimer laser to activate the implanted impurities. Thereafter, although not shown, for example, CVD or sputtering method to form a protective film made of S i 3 N 4 or S i 0 2 on the surface of the memory element formed in this way.
- FIGS. 26 and 27 show a configuration example of a memory device in which the top-gate type memory element shown in the first or second embodiment is integrated.
- FIG. 26 is a plan view of an example in which the circuit diagram shown in FIG. 3 is applied to an actual device
- FIG. 27 is a diagram of FIG. Each cross-sectional view is shown along a line.
- the source lines S i, S 2 , the bit lines B i, B 2 , and the word lines Wi, W 2 are each a polycrystalline silicon layer into which a metal such as Al, Cu or the like has been implanted. Is formed. Although only a 2 ⁇ 2 memory array is shown here, it goes without saying that in general, nxm (n, m> 1). This is the same in the following embodiments.
- the first method of memory device integration is as shown in FIG. 3 or FIG.
- the control electrodes (G) of the memory elements are connected to word lines, W 2 , and the source-drain paths are connected between bit lines and source lines. .
- Writing, erasing, holding, and reading of information from / to each memory element is performed, as described above, using the source, bit, and word lines in the first impurity region, gate region, and second impurity region of each memory element. What is necessary is just to apply an electric potential.
- the second method of memory device integration is to connect the control electrode of the memory device to a word line, and connect the source-drain paths between the bit line and the source line, respectively.
- FIG. 28 shows a configuration example of a memory device in which bottom-gate type memory elements according to a fourth embodiment of the present invention are integrated.
- the plan configuration is the same as that of FIG. 26, and FIG. 28 also corresponds to the cross-sectional configuration along the line 17 in FIG.
- the method of fabricating each element is as described above, and the detailed description is omitted because it can be easily diverted even when integrated.
- FIG. 29 and FIG. 30 show configuration examples of a memory device using a top gate type memory element according to the fifth embodiment of the present invention.
- FIG. 29 is a plan view of an example in which the circuit diagram shown in FIG. 3 is applied to an actual device
- FIG. 30 is a cross-sectional view taken along the line —- ⁇ in FIG. .
- the source line, S 2 , bit line, B 2 , word line, W 2 are formed of a polycrystalline silicon layer into which a metal such as A 1 or Cu or an impurity is implanted.
- FIG. 31 shows an example in which the bottom gate type memory element according to the second embodiment is integrated.
- 0 V is applied to the word lines to W n — excluding the source line S m and the word line W n
- the potential V P is applied to the word line W n (for example, 10 0 V)
- a potential V d (for example, 5 V) is applied to the bit line B m .
- a potential of V P / 2 is applied to the source line S i and the bit line B i (i ⁇ m) so that information in other memory elements around the memory element C nm is not erroneously erased.
- the potentials of all electrodes are set to the same potential or a floating state.
- FIGS. 32 and 33 show a configuration example of a memory device using a top gate type memory element according to the sixth embodiment of the present invention.
- FIG. 32 is a plan view of an example in which the circuit diagram shown in FIG. 5 is applied to an actual device
- FIG. 33 is a cross-sectional view taken along line 11 of FIG. .
- the source line Si, bit line B, Wa one word line W, W 2, W 3, W 4, ⁇ , W n is a metal, such as A 1, C u or impurity injection, Formed by the polycrystalline silicon layer.
- FIG. 34 shows an example in which the bottom-gate type memory element according to the second embodiment is integrated. As in FIG. 33, along the line 1-1 in FIG. Corresponding to the cross-sectional view.
- the memory device M nm when writing information, all source lines while the 0 V, the potential V P (e.g. 1 0 V) to the word line W m, the word line W m except for word lines V P / 2 (e.g., 5 V), 0 V to the bit line B n, a memory element connected one lead wire Wa other than bit line B n ⁇ ⁇ "> the gate one me V / 2 (for example, 5 V) is applied to the bit line of the memory element array including the memory cell.
- V P e.g. 1 0 V
- V P / 2 e.g., 5 V
- peripheral circuits such as a control circuit are simultaneously manufactured together with the memory element according to the first embodiment (FIG. 1) on the same substrate. The method will be described.
- a substrate made of quartz, glass, plastic, etc.
- a Si 3 N 4 and SiO 2 layer having a thickness of about 100 nm as a buffer layer 12 by CVD or sputtering
- a thickness of about 10 nm is formed on the surface of the buffer layer 12.
- element isolation is performed by etching.
- the film thickness number 1 0 nm S i O ⁇ (x ⁇ 2) layer is formed. Then, X e C 1 excimer irradiation 1 50 ⁇ 3 0 0mJZcm 2 about an THE. As a result, as shown in FIG. 36, the amorphous silicon layer 13 ′ is crystallized into a polycrystalline silicon layer 13, and excess silicon in S i 0 x is precipitated, and a large number of An accumulation region 15 composed of the fine particles 15a is formed.
- control insulating film 14b having a thickness of about 100 nm is formed by sputtering silicon in an ionized gas atmosphere of a gas containing atoms.
- a control electrode 16 (G m , G) is formed on the control insulating film 14 b with a polycrystalline silicon layer or a metal such as A 1, Cu, W, and the like.
- (G m , G) as a mask, the surface of the polycrystalline silicon layer 13 is etched by RIE using a mixed gas of CF 4 and H 2 .
- ionized gas containing group V atoms such as PH 3 Irradiate ionized gas containing group III atoms such as B 2 He to form the first impurity region 13 a (S m , S) and the second impurity region 13 b (D m , D) I do.
- the device is heated using an electric furnace or an excimer laser to activate the implanted impurities.
- FIGS. 40 to 45 a description will be given of a method for simultaneously manufacturing a peripheral circuit together with the memory element according to the second embodiment (FIG. 2) on the same substrate.
- the substrate 2 1 such as quartz, CVD method, or by a spa Ttaringu method, for example, S ia N 4 and consisting of S i 0 2 film thickness 1 00 nm Bas Ffa layer
- a film of tungsten, tantalum, molybdenum, or the like is formed by electron beam evaporation or sputtering, and is patterned to form the control electrodes 26 (G m , G).
- the thickness A few lO nm0SiC (x2) layers 27 are formed.
- the memory element side (left side in the figure) is covered with a photo resist film 28, and the surrounding area is subjected to RIE using SF 8 or a mixed gas of CF 4 and H 2.
- the SiO 2 layer 27 formed on the circuit side (right side in the figure) is selectively removed. After that, the photoresist film 28 is removed.
- the amorphous silicon layer 2 3 ′ is crystallized and converted into the polycrystalline silicon layer 23, and at the same time, the accumulation region 25 composed of a large number of fine particles 25 a is formed. Next, etching for element isolation is performed. Subsequently, as shown in FIG. 45, the control electrode 26 on the polycrystalline silicon layer 23
- a mask 29 is formed of a photoresist film or a SiO 2 film in a region corresponding to (G m , G). Then, using a mask 29, if the conduction charge is to be an electron, a group V ion such as phosphorus is implanted, and if the conduction charge is to be a hole, a group III ion such as boron is implanted. Region 23 a (S m , S) and second impurity region 23 b
- the first impurity region 23a ( Sm , S) and the second impurity region 23b ( Dm , D) may be formed by irradiating ionized gas. After that, the device is heated using an electric furnace or an excimer laser to activate the implanted impurities. Then, after forming the wiring required, by a CVD method or spa Ttaringu method, a protective film made of S ia N 4, S i 0 2 on the surface of the memory device
- the surface of the cleaned silicon single crystal substrate 31 is selectively oxidized by a LOCOS (Local Oxidation of Silicon) method to form a field oxide film 32 for element isolation. Then, a gate oxide film 33 is formed by a thermal oxidation method.
- LOCOS Local Oxidation of Silicon
- a control electrode 34 made of a polycrystalline silicon layer or a metal such as A1, W, Cu is formed by a CVD method or a sputtering method. Ion implantation is performed using the control electrode 34 as a mask to form n-type LDD lightly doped drain (Drain) regions 35a and 35b. Subsequently, after a gate side wall (side wall) 34a made of, for example, SiO 2 is formed on the side wall of the control electrode 34, ion implantation is performed using the gate side wall 34a and the control electrode 34 as a mask. Then, an n ++ type source region 36a and a drain region 36b are formed.
- An interlayer insulating film 37 is formed by using O 2 , S i (0C 2 H 5 ) 4 (TE 0 S), or SOG (Spin On Glass). After that, the surface of the interlayer insulating film 37 is flattened by CMP (Chemical and Mechanical Polishing). After that, a memory element is formed in the same manner as described above. That is, as shown in FIG. 49, a tunnel insulating film 14a is formed on the interlayer insulating film 37, and a storage region 15 including a large number of fine particles 15a is formed thereon. Next, as shown in FIG.
- a control insulating film 14b is formed, and a control electrode 16 (G m ) is formed on the control insulating film 14b.
- the first An impurity region 13a ( Sm ) and a second impurity region 13b ( Dm ) are formed.
- the wiring required by a CVD method or a sputtering method to form a protective film on the surface of the memory device consisting of S i 3 N 4, S i 0 2 ( not shown).
- FIG. 52 shows an example in which the memory element of the above embodiment has a laminated structure (here, a two-layer structure). That is, on the semiconductor substrate 4 1, after forming the buffer layer 42 made of S i 3 N 4, S i 0 2, to produce a memory device according to the above embodiment, then, using the C VD or sputtering Te to form S i 0 2 and S i (0C 2 H 5) 4 (T EOS) and the like or SO G (Spin On Glass) by an interlayer insulating film 4 3,.
- a laminated structure here, a two-layer structure
- S i 0 2 film 52 having a film thickness of 2 0 0 nm by PEC VD method on the glass substrate 5 1.
- a plastic substrate such as polyether sulfone (PES) —polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET), or silicon substrate or the like may be used.
- PES polyether sulfone
- PMMA polymethyl methacrylate
- PET polyethylene terephthalate
- silicon substrate or the like silicon substrate or the like.
- a 30 nm thick Si film 53 was formed on the SiO 2 film 52 by PEC VD method.
- the Si film 53 may be in an amorphous state or a microcrystalline state.
- a laser beam having a pulse width of 10 to 50 nsec and 28 OmJ / cm 2 is formed on the surface of the glass substrate 51 on which the SiO x film 54 is formed. 15 were irradiated.
- Excimer lasers such as KrF (resonance wavelength 248 nm), ArF (resonance wavelength 193 nm), and XeC1 (resonance wavelength 308 nm) can be used as the laser.
- an XeC1 excimer laser was used.
- S i Ox film 54 is decomposed into S i 0 2 and S i stoichiometry. In other words, a state in which fine particles 5 b are formed of S i in S i 0 2 film 54 a.
- the size of the fine particles 54b ranges from 1 nm to 1 m.
- Fig. 54 shows the result of a scanning electron microscope (SEM) photograph after the irradiation of the energy beam. It can be seen that white bright dots are dotted in the black area. Furthermore, micro-AE S; by (Auger Electron Spe ctroscopy O one di We electron spectroscopy), the results of examining the differences between S i 0 2 and possible dark areas and diffusion was S i and possible bright areas, dark It was found that Si was concentrated in an area brighter than the area. On the Si film 53 thus formed on the glass substrate 51, a Si Ox film 54 containing excess Si is formed. Subsequently, the laser beam 55 Irradiation and heat treatment resulted in formation of an accumulation region composed of a large number of fine particles 54b.
- SEM scanning electron microscope
- a SiO 2 film 62 having a thickness of 200 nm was formed on a glass substrate 61 by PE CVD.
- an Si film 63 for a memory channel having a thickness of 30 nm was formed on the SiO 2 film 62.
- the S i 0 2 film 64 having a thickness of 1 nm ⁇ 1 0 nm was formed by PECVD, on the S i 0 2 film 64, the flow rate 2 0 SCCM of S i H was form form the S i Ox (x twice as) film 6 5 S i over the PEC VD method using 4 gas and the flow rate 2 0 SCCM N 2 0 gas.
- the surface of the glass substrate 61 on which the SiO 2 film 65 was formed was irradiated with an excimer laser beam 66 of 28 OmJ / cm 2 as shown in FIG. 55B.
- S i O x film 6 5 As shown in 5 5 C diagram, S i 0 2 film 65 a Toko of S i 0 2 film 65 S dispersed in a Decomposed into fine particles 65b of i.
- the SiO 2 film 65 a in which the fine particles 65 b are dispersed serves as a floating gate.
- S i 0 2 film 6 7 After forming the fine particles 6 5 b, as shown in 5 5 D view, on S i 0 2 film 6 5 a, form S i 0 2 film 6 7 having a thickness of 1 00 nm by PE CVD method did. Subsequently, the formation of the S i 0 2 film control gate one DOO 68 consisting of thickness 1 0 01 ⁇ 1 Ding a (tantalum) on the 6 7. That is, a tantalum film is formed on the SiO 2 film 67 by, for example, a sputtering method, and then a gate pattern photo resist film is formed on the indium film, and the photoresist film is formed.
- the tantalum film was etched as a mask, and the control gate 68 was formed by removing the photoresist film.
- 5 6 A diagram, for example, by plasma etching using a mixed gas containing CF 4 and H 2, the control gate Ichito 6 8 as a mask, S i 0 2 Film 6 7 were sequentially selectively removed S i 0 2 film 6 5 a and S i 0 2 film 6 4 containing fine particles 6 5 b.
- n-type impurities phosphorus (P)
- P phosphorus
- the first impurity region 63 b and the second impurity region 63 c are formed in a self-alignment manner on both sides of the conduction region 63 a below the control gate 68.
- the substrate surface was irradiated with an excimer laser beam (wavelength: 308 nm) to activate the impurities in the first impurity region 63b and the second impurity region 63c.
- a Si 3 N 4 film 69 as a protective film is formed on the substrate surface by, for example, the PECVD method, and the source and the gate are formed on the Si 3 N 4 film 69.
- aluminum (A 1) is deposited by, for example, a sputtering method, and then patterned to form a source electrode 70 a, a gate electrode 70 b, and the like. Drain electrodes 70c were formed respectively.
- a non-volatile memory element having a floating gate (accumulation area) containing Si fine particles could be manufactured.
- the current flows between the first impurity region 63b and the second impurity region 63c, and the conduction region 6b is connected to the gate electrode 70b.
- a large positive bias is applied to 3a, electrons tunneling through the insulating film accumulate in the Si dot 65b, resulting in a change in the IV characteristics.
- a negative bias is applied to the gate electrode 60b, electrons accumulated in the Si dot 65b are tunneled through the insulating film and released to the conduction region 63a, and as a result, the original I-V Return to properties.
- Si dots 65b in the gate insulating film By forming the Si dots 65b in the gate insulating film in this manner, charges can be accumulated or released to have a memory effect.
- This structure has the same effect as a so-called flash memory having a continuous Si floating gate, but since it is a dot-shaped floating gate, the charges accumulated in each dot leak and dissipate. A memory device with a small ratio and good holding power is obtained.
- the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments.
- the present invention is suitable for manufacturing a silicon dot memory.
- the device can be applied to the manufacture of various other devices as long as the device uses silicon fine particles (dots).
- dots silicon fine particles
- a silicon substrate is used as the substrate, it can be applied to a flash memory having a floating gate.
- a dot made of another semiconductor may be formed.
- other Group IV elements G e germanium
- S i F e 2 can have use of S i F e 2
- S i G e as group IV compound semiconductor may, furthermore, II- VI group compound semiconductor or III-V group
- a dot of a compound semiconductor or a dot of a metal Au, Sb, Sn may be formed.
- Zn 0 doped with Se is irradiated with laser to form a ZnSe dot.
- Te tellurium
- an example of the dot formation using a group III-V compound semiconductor is to irradiate a laser beam to Si Nx (or a stacked structure of Si 3 N 4 / Ga N / Sia N 4 ) to which Ga is added.
- Example of forming GaN dots in i 3 N 4 Further, irradiating a laser to the stacked structure of AlGaAsZInAs An example of forming a dot is given.
- the storage region is constituted by a large number of dispersed fine particles (dots), and the surface density of the fine particles in the storage region is reduced. Structural holes in the tunnel insulating film
- the number of fine particles in the accumulation region should be 5 or more, or the conduction region should have a surface roughness of 0.1 nm or more and 100 nm or less.
- the number of fine particles in the accumulation region is greater than the number of crystal grains in the conduction region. Can be manufactured. In addition, even if defects such as pinholes occur in the tunnel insulating film and the charges accumulated in some of the fine particles leak, the charges accumulated in the fine particles formed in the region where no defect exists may leak. There is no. Therefore, keeping the information for a long time Can be.
- the film for forming a storage region having a non-stoichiometric composition containing an excessive amount of semiconductor is subjected to a heat treatment such as energy beam irradiation.
- a heat treatment such as energy beam irradiation.
- An accumulation region composed of a large number of dispersed fine particles can be easily formed on a glass or plastic substrate.
- the memory element according to the present invention can manufacture a tunnel insulating film on a glass or plastic substrate at a low temperature and can hold information for a long time, It is suitable for use in storage devices and data processing devices.
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
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Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/381,987 US6285055B1 (en) | 1998-01-26 | 1999-01-26 | Memory device and method of manufacturing the same, and integrated circuit and method of manufacturing semiconductor device |
KR1019997008723A KR100638772B1 (ko) | 1998-01-26 | 1999-01-26 | 메모리 소자 및 그 제조 방법, 및 집적 회로 및 반도체 장치의 제조 방법 |
EP99901180A EP0971416A4 (en) | 1998-01-26 | 1999-01-26 | MEMORY DEVICE AND CORRESPONDING MANUFACTURING METHOD, AND INTEGRATED CIRCUIT AND CORRESPONDING MANUFACTURING METHOD |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10/27747 | 1998-01-26 | ||
JP2774798 | 1998-01-26 | ||
JP10/321377 | 1998-10-28 | ||
JP32137798A JP4538693B2 (ja) | 1998-01-26 | 1998-10-28 | メモリ素子およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
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WO1999038213A1 true WO1999038213A1 (fr) | 1999-07-29 |
Family
ID=26365719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1999/000313 WO1999038213A1 (fr) | 1998-01-26 | 1999-01-26 | Dispositif memoire et procede de fabrication correspondant, et circuit integre et procede de fabrication correspondant |
Country Status (6)
Country | Link |
---|---|
US (1) | US6285055B1 (ja) |
EP (1) | EP0971416A4 (ja) |
JP (1) | JP4538693B2 (ja) |
KR (1) | KR100638772B1 (ja) |
CN (2) | CN1169225C (ja) |
WO (1) | WO1999038213A1 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
CN1256793A (zh) | 2000-06-14 |
KR20010005655A (ko) | 2001-01-15 |
EP0971416A4 (en) | 2000-08-09 |
JP4538693B2 (ja) | 2010-09-08 |
CN1542976A (zh) | 2004-11-03 |
US6285055B1 (en) | 2001-09-04 |
EP0971416A1 (en) | 2000-01-12 |
KR100638772B1 (ko) | 2006-10-27 |
CN1309087C (zh) | 2007-04-04 |
CN1169225C (zh) | 2004-09-29 |
JPH11274420A (ja) | 1999-10-08 |
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