WO1998025271A1 - Dispositif comprenant un circuit integre a semi-conducteur - Google Patents

Dispositif comprenant un circuit integre a semi-conducteur Download PDF

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Publication number
WO1998025271A1
WO1998025271A1 PCT/JP1996/003548 JP9603548W WO9825271A1 WO 1998025271 A1 WO1998025271 A1 WO 1998025271A1 JP 9603548 W JP9603548 W JP 9603548W WO 9825271 A1 WO9825271 A1 WO 9825271A1
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WO
WIPO (PCT)
Prior art keywords
dram
chip
integrated circuit
semiconductor integrated
circuit device
Prior art date
Application number
PCT/JP1996/003548
Other languages
English (en)
Japanese (ja)
Inventor
Koki Noguchi
Satoshi Michishita
Masashi Horiguchi
Masaharu Kubo
Toshio Miyamoto
Asao Nishimura
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/003548 priority Critical patent/WO1998025271A1/fr
Priority to AU10402/97A priority patent/AU1040297A/en
Priority to TW086100683A priority patent/TW329047B/zh
Publication of WO1998025271A1 publication Critical patent/WO1998025271A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Definitions

  • the present invention relates to a semiconductor integrated circuit device in which a plurality of types of semiconductor chips are housed in a single package so that signals can be input and output to and from each other from an MCM (Multi Chip Module) approach.
  • Microcomputer including Processing Unit), programmable non-volatile memory such as flash memory, and logic LSI such as DRAM (Dynamic Random Access Memory; A / I (Application Specific Integrated Circuit))
  • the present invention relates to technology that is effective when applied to semiconductor integrated circuit devices that have been implemented.
  • the present inventor has realized the realization of a D RAVI ⁇ SIMM (Single In-line memory Module) approach and a flash memory ⁇ DRAM microcomputer on chip with high customer needs in system-on-chip semiconductor integrated circuit devices. Rather than making a microcomputer, flash memory, DRAM, AS IC, etc. all in one chip, multiple types of semiconductor chips can be housed in a single package and a signal can be input / output to / from each other from a practical approach The technology to be considered was considered. The following is the technology studied by the present inventors, and the outline is as follows.
  • a p-type impurity (boron) is ion-implanted into the main surface of the semiconductor substrate 100 to form a p-type well 10].
  • the LOCOS A field oxide film 102 is formed by a method.
  • the element formed at the left end of the figure is the MOS FET that forms the DRAM memory cell, and the element that is formed to the right is the MOS FET that forms the memory cell of the flash memory and a part of the peripheral circuit of the flash memory.
  • the high-voltage MOS FET that composes it, and the element formed at the right end is the MO SFET that composes a logic LSI such as a micro computer or AS IC.
  • an actual LSI is mainly composed of an n-channel MOS FET and a p-channel MOS FET, but for simplicity of description, only a region where an n-channel MOS FET is formed is illustrated.
  • a tunnel oxide film 103 of the flash memory is formed.
  • the thickness of the tunnel oxide film 103 is about 8 to 13 nm.
  • the polycrystalline silicon film deposited by the CVD method on the semiconductor substrate 100 is patterned to form (part of) the floating gate 104 of the flash memory.
  • a second gate insulating film (ONO film) 105 having a film thickness of about 10 to 30 nra, in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked, is formed thereon.
  • a gate oxide film 106 of a high breakdown voltage MOSFET is formed in the peripheral circuit region of the flash memory.
  • the gate oxide film 106 is formed to have a thickness (10 to 30 nm) larger than that of the other gate oxide films in order to increase the breakdown voltage.
  • a gate oxide film 107 of the MOS FET forming the logic LSI and a gate oxide film 130 of the MOS FET forming the memory cell of the DRAM are formed.
  • the thickness of the gate oxide film 107 is about 4 to 10 nm, and the thickness of the gate oxide film 130 is about 8 to 15 nm.
  • the polycrystalline silicon film deposited by the CVD method on the semiconductor substrate] .00 is patterned to form the gate electrode (lead line) of the DRAM memory cell.
  • Control gate 1 09, high pressure MO SFET After forming the gate electrode 110 and the gate electrode 111 of the MOS FET constituting the logic LSI at the same time, as shown in FIG. 85, the flash memory (partially formed) floating gate 104 is buttered. To form a floating gate 104.
  • n-type impurities (phosphorus and arsenic) are ion-implanted into a part of the memory cell region of the flash memory to form an n ⁇ type semiconductor region 112 of the flash memory.
  • n-type impurities (phosphorus and arsenic) are ion-implanted into a part of the memory cell area of the flash memory, the peripheral circuit area, and the logic LSI formation area, and the n-type semiconductor area 11 3, 113, n-type semiconductor regions 113, 113 of high-voltage MOS FETs, and n-type semiconductor regions 113, 113 of MOS FETs constituting logic LSI are simultaneously formed.
  • the gate electrode (word line) 108 of the DRAM memory cell the gate 109 of the flash memory, the gate electrode 110 of the high-voltage M ⁇ SFET, and the logic LS
  • a side wall spacer 114 is formed on the side wall of the gate electrode 111 of the MOSFET constituting I.
  • an n-type impurity (phosphorous or arsenic) is ion-implanted into a part of the memory cell area of the flash memory, the peripheral circuit area, and the logic LSI formation area, thereby forming the n + type of the flash memory.
  • One of the source and drain regions of the flash memory and the source and drain regions of the high-voltage MOSFET, and the drain and source regions of the M ⁇ S FET that constitutes the logic LSI have an LDD (Lightly Doped Drain) structure. ,:.
  • connection holes are formed on both sides of the gate electrode (lead line) of the DRAM by etching the silicon oxide film 116 deposited on the semiconductor substrate 100 by the CVD method. Then, after connecting holes are formed above the n-type semiconductor region 112 of the flash memory, plugs 117 of a polycrystalline silicon film are formed inside these connecting holes. On both sides of the DRAM gate electrode, n-type semiconductor regions 118 are formed by impurities diffused from the polycrystalline silicon film. Then, on the silicon oxide film 1 1 6 The polycrystalline silicon film deposited by the CVD method is patterned to form bit lines BL for DRAM and bit lines BL for flash memory.
  • the polycrystalline silicon film deposited on the silicon oxide film 119 was patterned. Then, the lower electrode 120 of the DRAM capacitor is formed.
  • the tantalum oxide film (or silicon nitride film) and the polycrystalline silicon film deposited on the semiconductor substrate 100 are patterned to form a capacitor insulating film of a capacitor of DRAVI.
  • an upper electrode 122 and a silicon oxide film 123 on the semiconductor substrate 100 by the CVD method as shown in FIG. 93 an A1 film deposited on the silicon oxide film 123 is formed.
  • patterning is performed to form the first layer metal wirings 124.
  • a silicon oxide film 125 is deposited on the semiconductor substrate 100 by a CVD method, and then the silicon oxide film 125 is formed.
  • the A 1 film deposited on the substrate is patterned to form a second-layer metal wiring 126.
  • the gate oxide of the MOS FET in the DRAM section needs to be somewhat thicker than the gate oxide of the MOS FET in the logic section in consideration of the withstand voltage.
  • the gout oxide film of the high breakdown voltage MO SFET of the flash memory to which a high breakdown voltage is applied needs to be further thickened in order to secure a sufficient breakdown voltage.
  • a high-temperature heat treatment (a heat treatment for stabilizing the tantalum oxide film or a high-temperature nitridation treatment for forming a silicon nitride film) is required when forming the capacitor. It is necessary to set the gate length of the logic part slightly longer. However, if the gate length of the logic part is increased, the high-speed performance of the mouth is sacrificed. (3) The elevation of the DRAM part on the semiconductor chip is higher than that of the logic part, and a step is created between the two parts, which adversely affects the wiring formation.
  • a third object of the present invention is to reduce the number of external connection terminals in a circuit structure by a functional block configuration in a package structure in which two types of semiconductor chips of a CPU, a flash memory, and a DRAM are packaged.
  • Another object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the mounting area by integrating two types of semiconductor chips into one package and enabling the cost of a microcomputer system to be reduced.
  • external logic circuits such as ASICs are embedded in each semiconductor chip, and when DRAM is used as synchronous DRAM, the number of external connection pins can be further increased because the external connection pins can be shared.
  • An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing cost and reducing cost.
  • Another object of the present invention is to provide the above-described semiconductor integrated circuit device at a low cost.
  • a so-called micro-computer with a flash memory mounted with a CPU and a flash memory for example, a so-called micro-computer with a flash memory mounted with a CPU and a flash memory.
  • a semiconductor chip called a data chip a semiconductor chip called a DRAM on-chip logic equipped with a DRAM and a logic circuit such as an ASIC.
  • Operation measures between the microcomputer with memory and the DRAM on-chip logic are indispensable. In other words, measures must be taken for the data transfer speed between the CPU operation of the microcomputer with flash memory and the access operation to the DRAM of the DRAM on-chip logic, and the access operation to the DRAM from the logic circuit inside the DRAM on-chip logic. Required.
  • the first method is to return a wait signal to the CPU when the logic circuit is operating.
  • the memory between the microcomputer with flash memory and the DRAM on-chip logic must be communicated as asynchronous memory, one clock cycle cannot be transferred. Since this cannot be done, data transfer is a two-cycle cycle.
  • the present inventor has focused on the fact that it is preferable that the CPU of a microcomputer with a flash memory control the time itself, and considers the self-refresh of the DRAM as viewed from the CPU of a computer with a microphone with a flash memory.
  • the self-refresh operation of the DRAM is enabled by making effective use of the period, and during this self-refresh period, the logic inside the DRAM on-chip logic is It was conceived that by enabling access to the DRAM from the memory circuit, it was possible to achieve high-speed data transfer between the microcomputer with flash memory and the DRAM on-chip logic.
  • One object of the present invention is to make effective use of the DRAM's senoref refresh period viewed from the outside by eliminating the need for weight control in a semiconductor chip equipped with a DRAM and a logic circuit such as an ASIC. It is an object of the present invention to provide a semiconductor integrated circuit device capable of performing an access operation to a DRAM from a logic circuit during the self-refresh period and realizing a high-speed data transfer between an external device and a semiconductor chip.
  • weight control is not required.
  • a semiconductor integrated circuit device which enables a logic circuit to access a DRAM during a DRAM self-refresh period as viewed from a CPU, thereby realizing high-speed data transfer between semiconductor chips. It is in.
  • a semiconductor integrated circuit device which does not require weight control for exchanging weight signals and can control processing timing itself from the CPU, thereby facilitating program creation. It is in.
  • a semiconductor chip equipped with a DRAM and a logic circuit and a semiconductor chip equipped with a CPU and a flash memory can be directly connected to enable high-speed operation. It is an object of the present invention to provide a semiconductor integrated circuit device that can achieve the above.
  • one semiconductor integrated circuit device of the present invention has at least a CPU and a flash memory.
  • the plurality of second semiconductor chips are housed in the same package so that signals can be input / output to each other, and the plurality of connection terminals of the first semiconductor chip and the one or more second semiconductor chips And a plurality of external connection terminals respectively connected to the plurality of connection terminals.
  • one semiconductor integrated circuit device of the present invention is the semiconductor integrated circuit device, wherein at least a DRAM and a logic circuit are formed on one or a plurality of second semiconductor chips.
  • At least a DRAM and a mouthpiece circuit are formed on the first semiconductor chip.
  • the semiconductor integrated circuit device includes a plurality of connection terminals of the first semiconductor chip and a plurality of connection terminals of the one or more second semiconductor chips, among the plurality of external connection terminals.
  • the same commonly assigned external connection terminal is an address terminal, a data input / output terminal, a power supply terminal, and a ground.
  • a terminal, an address strobe terminal, a write enable terminal, an output enable terminal, and an interrupt terminal, and the same external connection terminal commonly assigned is standardized in a bus specification.
  • the DRAM is a synchronous DRAM, and a clock terminal of the first semiconductor chip and a clock terminal of the one or more second semiconductor chips are the same as the plurality of external connection terminals.
  • the DRAM is commonly assigned to the external connection terminals, and the DRAM is a synchronous DRAM or an EDO-DRAM.
  • the circuit with a functional block configuration is also used. Reduces the number of external connection terminals, reduces the mounting area by integrating two types of semiconductor chips into one package, and reduces the cost of microcomputer systems It can be.
  • each chip incorporates a logic circuit such as an ASIC, and if the DRAM is a synchronous DR AVI, the number of external connection terminals can be further increased because the external connection terminals can be shared. And cost can be reduced.
  • One semiconductor integrated circuit device of the present invention includes a semiconductor chip on which at least a DRAM and a magic circuit are formed, and the logic circuit controls at least an access operation of a write operation / read operation for the DRAM.
  • control means capable of executing a refresh operation Z access operation, and processing of data stored in the DRAM are performed.
  • One semiconductor integrated circuit device of the present invention includes a first semiconductor chip on which at least a CPU and a flash memory are formed, and one or more first semiconductor chips on which at least a DRAM and a logic circuit are formed.
  • the first semiconductor chip and the one or more second semiconductor chips are housed in the same package so that signals can be input and output to and from each other.
  • a plurality of external connection terminals respectively connected to a plurality of connection terminals of the first semiconductor chip and a plurality of connection terminals of the one or more second semiconductor chips;
  • the logic circuit of the semiconductor chip controls at least the write operation and the read operation of the DRAM, the access operation of the read operation, and the refresh operation during the self-refresh operation of the DRAM.
  • a control means capable of executing an access operation, and processes data stored in the DRAM, and outputs a write request Z read request to the control means when processing the data stored in the DRAM. And processing means.
  • control means executes the DRAM as a memory function during a normal access operation, and executes a refresh operation Z access operation according to a request from the processing means during a self-refresh operation.
  • the execution of the refresh operation Z access operation at the time of the self-refresh operation is performed by a write request of the processing unit,
  • the access operation is repeated according to the read request, and the refresh operation is performed during a period between the write operation and the read operation.
  • the control means may include an access period for executing a normal write operation and a read operation for the DR AVI based on an externally input address strobe signal, and a self-refresh permission output to the processing means.
  • a self-refresh period for executing a refresh operation z access operation with a write request signal Z read response signal in response to the signal as an input is set.
  • the self refresh period is a write access period in which a write operation is performed with a write request signal from the processing unit as an input, and a read access period in which a read operation is performed with a read request signal from the processing unit as an input.
  • a refresh period for performing a refresh operation in a period excluding the write access period and the read access period.
  • a data width of an internal data bus of the semiconductor chip is wider than a data width of a data input / output terminal of an external connection terminal of the semiconductor chip.
  • the interface of the semiconductor chip is standardized to the interface specification of the semiconductor chip having only the DRAM.
  • the DRAM is a sink mouth eggplant DRAM, EDO-DRAM.
  • a package structure in which two types of semiconductor chips, a semiconductor chip with a DRAM and a logic circuit, and a semiconductor chip with a CPU and a flash memory, are packaged is also viewed from the CPU. Since access to the DRAM can be performed from the magic circuit during the DRAM self-refresh period, high-speed data transfer between semiconductor chips can be realized. Furthermore, since there is no need for wait control to exchange wait signals, the timing of processing itself can be controlled from the CPU.In other words, the timing of processing itself can be known in the CPU program, so program creation can be performed. Can be easier.
  • a semiconductor chip equipped with a DRAM and a logic circuit can be directly connected to a semiconductor chip equipped with a CPU and a flash memory to enable high-speed operation. Can be.
  • FIGS. 1 to 6 are schematic configuration diagrams showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIGS. 7 to 14 constitute a semiconductor integrated circuit device according to an embodiment of the present invention.
  • Functional block diagram showing an internal configuration example of a semiconductor chip and explanatory diagram showing a terminal function example FIGS. 15 to 18 are explanatory diagrams showing a list of terminal function examples of a semiconductor chip, and FIGS. 19 and 20 show semiconductors.
  • Connection diagram showing an example of chip connection Fig. 21 is a schematic configuration diagram schematically showing an example of the internal functions of a semiconductor chip
  • Fig. 22 is a configuration diagram showing a detailed example of a DRAM access control unit
  • Fig. 23 is an internal diagram.
  • FIG. 21 is a schematic configuration diagram schematically showing an example of the internal functions of a semiconductor chip
  • Fig. 22 is a configuration diagram showing a detailed example of a DRAM access control unit
  • Fig. 23 is an internal diagram.
  • FIG. 24 is an explanatory diagram showing an example of a transition state of an operation mode by a control signal generation circuit.
  • FIG. 24 is an operation timing diagram showing a control example of a DRAM access control unit for DRAM
  • FIG. 25 is an embodiment of the present invention.
  • Overall perspective view of the package Figure 26 is a cross-sectional view of this package, Figure 27, Figure 28 is a plan view showing a pattern of leads formed on one surface of the tape carrier, and FIGS. 29 to 37 are cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIGS. 38 to 66 are cross-sectional views showing another method of manufacturing the semiconductor integrated circuit device.
  • FIGS. 67 to 69 are plan views showing patterns of leads formed on one surface of the tape carrier.
  • FIGS. 73 to 77 are function blocks showing an example of a system configuration using the semiconductor integrated circuit device of the present embodiment.
  • Figures, 78 to 94 show the microcomputer, flash memory, DRAM, and ASI studied by the inventor.
  • the semiconductor integrated circuit device is, for example, an LSI package having a stacked structure in which a plurality of types of semiconductor chips are connected to each other so that signals can be input and output, and an example of the configuration is shown in FIG.
  • a chip MF first semiconductor chip
  • a microcomputer equipped with a so-called flash memory, in which a microcomputer M including a CPU, a memory and peripheral circuits, and a flash memory F are mounted; a DRAMD and an AS.
  • DRAM-on-chip logic chip AD second semiconductor chip
  • a logic circuit A such as an IC
  • connection terminal between each chip MF and chip AD is They are connected to each other via a bus inside the package, and to external connection terminals that enable connection with the outside.
  • the flash memory F is a programmable non-volatile memory, which is one of the LSI memories, and is a memory in which writing or erasing is performed by applying a high voltage to a memory cell.
  • DRAMD is a type of LSI memory that needs to supply a control (refresh) signal for repeated data reproduction in order to retain the data contents.
  • AS ICs are application-specific ICs or dedicated ICs. Unlike general-purpose LSIs that are sold in the general market, such as large-capacity memory LSIs and microprocessor LSIs, they are developed for specific devices. It is an LSI to sell.
  • a chip MF first semiconductor chip on which a microcomputer M including a CPU, a memory, a peripheral circuit, and the like and a flash memory F are mounted; It consists of a chip D (second semiconductor chip) on which only the DR AMD is mounted, and has a configuration in which the logic circuit A such as an AS IC is removed from the second semiconductor chip in the configuration example of Fig. 1. .
  • a microcomputer M including a CPU, a memory, and peripheral circuits, a flash memory F, and a logic circuit A are mounted. It consists of a chip MFA (first semiconductor chip) called a chip logic microcomputer and a chip D (second semiconductor chip) on which only DRAMD is mounted.
  • the first semiconductor chip is equipped with a logic circuit A such as an AS IC.
  • a chip MF A and a chip AD are configured, and as a modified example of FIG. 2, as shown in FIG.
  • a configuration example such as a configuration including a chip MFA and a plurality of chips D as shown in FIG. .
  • the chip AD and the chip D are directly connected to the chip MF and the chip MFA according to the general-purpose DRAM interface specification, and the DRAM is used as an extended memory in each semiconductor integrated circuit device. Furthermore, the logic circuit A such as the ASIC of the chip AD can control the access to the DRAM inside the chip AD independently of the access control by the CPU of the chip MF and the chip MFA.
  • FIGS. 15 to 18 show a list of examples of the terminal functions of the chip MF.
  • FIG. 7 and 8 show examples of the 144-pin chip MF
  • FIG. 7 is a functional block diagram showing an example of the internal configuration
  • FIG. 8 is an explanatory diagram showing an example of the terminal functions.
  • Fig. 9, Fig. 10 Shows an example of the pin 112 of the chip MF
  • FIG. 9 is a functional block diagram showing an example of the internal configuration
  • FIG. 10 is an explanatory diagram showing an example of the terminal function.
  • the difference between the 144-pin chip MF and the 112-pin chip MF is that the external terminals for data input and output correspond to D0 to D31 corresponding to the data width of 32 bits and 16 bits, respectively. The only difference is D0 to D15.
  • a 144-pin chip MF will be mainly described.
  • the 144-pin chip MF is formed with at least a microcomputer and a flash memory, and has a circuit configuration having a general control and processing function of the semiconductor integrated circuit device and a programmable memory function capable of electrically erasing all at once.
  • the processor CPU flash memory Flash, random access memory / cache memory RAM / Cache, data transfer controller DTC, direct memory access controller DMAC, and Controller BSC, user break controller UBC, interrupt controller INTC, serial communication interface SCI, multifunction timer pulse unit MTU, conveyor match timer CMT, A / D converter A / D, watchdog timer WDT, phase And the like have been constructed from the look-the true-flop circuit PLL.
  • the CPU is, for example, a central processing unit having an instruction set of the RISC type. Since this CPU basically operates in one instruction and one cycle, the instruction execution speed is dramatically improved, and the internal 32-bit configuration enhances the data processing capability.
  • the features of this CPU include a general-purpose register machine (16 general-purpose registers, 16 x 32 bits, 3 control registers, 3 x 32 bits, and 4 system registers, 4 x 32 bits), RISC compatible instruction set (Improved code efficiency due to fixed instruction length of 16 bits, load store architecture (basic operation is executed between registers), adoption of delayed branch instructions to reduce turbulence in bipline at branching, C language oriented instruction set)
  • the instruction execution time is 1 instruction Z 1 cycle (35 nsZ instruction at 28 MHz operation), the address space is 4 GB in architecture, and 2 to 4 cycles of 32 X 32 ⁇ 64 multiplication are executed by built-in multiplier , 32 X 32 + 64- ⁇ 64 multiply-accumulate operations are executed in 2 to 4 cycles, and
  • the flash memory F 1 ash is a circuit that incorporates, for example, a 64K-byte or 128-byte electrically erasable programmable memory. This F1ash is connected to the CPU, DMAC, and DTC via a 32-bit data bus, for example. The CPU, DMAC, and DTC can access the F1ash in 8, 16 or 32 bits wide. This F 1 ash data can always be accessed in one state.
  • the random access memory / cache memory RAMZC a che is a memory composed of, for example, a 4 KB random access memory and a 1 KB cache memory Ca che.
  • the features of this cache are instruction code and PC relative readout, data caching, line length is 4 bytes (1 long word is 2 instruction lengths), cache tag is 256 entries, direct map method, built-in RO / RAM
  • the built-in I / O area is not subject to caching and is also used as built-in RAM.
  • various functions are provided, such as using 2 KB of the built-in RAM as an address array and data array.
  • the data transfer controller DTC is a circuit that can be activated by an interrupt or software to perform data transfer.
  • the features of this DTC are that data can be transferred independently of the CPU by a peripheral I / O interrupt request, a transfer mode can be set for each interrupt source (transfer mode is set in memory), and one activation Depending on the cause, multiple data transfers are possible, a variety of transfer modes (Normal mode / Repeat mode, Z block transfer mode) can be selected, and the transfer unit can be set to byte Z word Z launder word.
  • Requests the interrupt that activated the DTC to the CPU can generate an interrupt to the CPU after one data transfer is completed, can generate an interrupt to the CPU after all specified data transfers are completed), and can start transfer by software And various other functions.
  • the address space can be specified as 32 bits for both the transfer source address and the transfer destination address, and the transfer target device is used for data transfer to the internal memory such as the flash memory F1ash, RAMZCache, external memory, and internal peripheral circuits. A transfer is performed.
  • the direct memory access controller DMAC is composed of, for example, four channels and has an external device with DACK (transfer request acceptance signal), an external memory, and a memory controller.
  • This circuit can perform high-speed data transfer between external devices and built-in peripheral circuits (excluding DMAC, BSC and UBC) instead of the CPU. Using this DMAC can reduce the load on the CPU and increase the operating efficiency of the chip MF.
  • the features of this DVIAC are: cycle stealing transfer, dual address mode transfer support, direct transfer mode Z indirect The transfer mode can be switched (only channel 3).
  • This direct transfer mode transfers data at the source address to the destination address, and the indirect transfer mode uses the data at the source address as the address. Is a function to transfer the data in the destination to the destination address.
  • Various functions such as interrupt requests are provided.
  • the bus state controller BSC is a circuit that separates an address space, outputs control signals corresponding to various memories, and the like. This makes it possible to directly connect DRAM, SRAM, ROM, etc. to the chip MF without external circuits.
  • the features of this BSC are that it supports memory access during external expansion (32-bit external data bus), divides the address space into 5 areas (SRAM space X 4 areas, DRAM space XI area), and each area
  • the bus size (8 16/32 bits), number of cycles, output of chip select signal corresponding to each area, output of DRAM bar RAS and bar CAS signal when accessing DRAM space, RAS precharge time Securing device Any characteristics that can generate p cycles can be set, DRAM burst access function (supports high-speed access mode of DRAM), DRAM refresh function (programmable refresh interval, and CAS RAS refresh RAS refresh) Self-refresh), wait cycles can be inserted by external wait signals, and address data
  • the scan I ZO device various functions such as access is provided.
  • the user break controller UBC is a circuit that provides functions that facilitate user program debugging.
  • a break condition is set in this UBC, user breaks occur according to the contents of the bus cycle by the CPU or DMAC and DTC.
  • a work interrupt is generated.
  • this function it is possible to easily create a sophisticated self-monitoring debugger, and easily debug a program with the chip MF alone without using a large-scale in-circuit emulator. I have. What are the features of this UBC? 1_ ⁇ 0 ⁇ 1 generates an interrupt when it generates a bus cycle under a set condition, and it is easy to build an on-chip debugger.Furthermore, break conditions include address, CPU cycle, or D MAZ DTC cycle.
  • Instruction fetch or data access, read or write, and operand size (longword, word, byte) can be set.
  • operand size longword, word, byte
  • a user break interrupt is generated, and a user-created user break interrupt is generated.
  • Exception routines can be executed.
  • the interrupt controller INTC is a circuit that determines the priority of an interrupt factor and controls an interrupt request to the processor CPU.
  • This INTC has a register for setting the priority of each interrupt, so that interrupt requests can be processed according to the priority set by the user.
  • the INTC features nine external interrupt pins, 43 internal interrupt sources, 16 levels of priority, a noise canceller function that indicates the status of the NMI pin, and an interrupt function. Can be output to the outside to notify the external bus master that an internal peripheral circuit interrupt has occurred while the chip MF has released the bus right, so that the bus right can be requested. .
  • the serial communication interface SCI has, for example, two independent channels, and these two channels have the same function.
  • This SCI is a circuit that can perform serial communication in two modes: start-stop synchronous communication and clock synchronous communication. C. It also has a serial communication function between multiple processors (multiprocessor communication function).
  • the features of this SCI are: Asynchronous / clock synchronous mode can be selected for each channel, transmission and reception can be performed simultaneously (full-duplex), a dedicated volume generator is built-in, Various functions such as communication functions are provided.
  • Multi-function timer pulse unit MTU is, for example, 1 of 6 channels. This is a circuit composed of a 6-bit timer.
  • the features of this MTU include: 16 types of waveform output or 16 types of input / output processing of 16 types of pulses based on 5 channels of 16-bit timer, 16 input / output conveyor registers and inputs Input capture register, total number of 16 independent comparators, selectable from 8 types of counter input clocks, input capture function, pulse output mode , Synchronization function of multiple power counters, Complementary PWM output mode (Outputs non-uniform waveforms for 6-phase inverter control, dead time automatic setting, PWM duty arbitrarily set to 0 to 100% Possible, output OFF function), reset synchronous PWM mode (3-phase output of positive and negative phase PWM waveforms of arbitrary duty), phase counting mode (2-phase encoder counting process), etc.
  • Various functions are provided.
  • the compare match timer CMT is composed of, for example, two channels, a 16-bit free running counter, one compare register, and the like, and has a function of generating an interrupt request at the compare match.
  • the AZ D converter A / D is a 10-bit x 8 channel, which enables conversion by an external trigger, and has two built-in sample and hold functions, enabling simultaneous sampling of two channels. I have.
  • the watchdog timer WDT is a one-channel timer that can monitor the system. This WDT outputs an overflow signal to the outside if the CPU overflows without correctly rewriting the counter value due to system runaway or the like. At the same time, an internal reset signal of the chip MF can be generated. When not used as a WDT, it can be used as an interval timer. When used as an interval timer, an interval timer interrupt is generated each time the counter overflows. WDT is also used when exiting standby mode.
  • the internal reset signal can be generated by setting a register. The type of reset can be selected from power-on reset and manual reset. C. The feature of this WDT is that it switches between the dog dog timer / interval timer. It is possible to provide functions such as temporary counting overflow, internal reset, external signal or interrupt generation. ing.
  • the phase-look loop circuit PLL is a circuit that incorporates, for example, a clock oscillator and operates as a PLL circuit for clock doubling.
  • these internal circuits are connected to each other by an internal address bus BUSAI and upper and lower internal data buses BUSD I as shown in FIG.
  • the internal circuit and the external connection terminal I / O are connected by the peripheral address bus BUS AO, the peripheral data bus BUSD ⁇ , and the control signal line SL.
  • the internal address bus BU SAI has a bus width of 24 bits, a processor CPL; flash memory F1ash, random access memory / cache memory RAM / Cache, data transfer controller DTC, and direct memory access controller. Connected between DMA C and bus state controller BSC.
  • the internal data bus BUS DI consists of a high-order 16-bit bus and a low-order 16-bit bus, each of which is a processor CPU, flash memory F1ash, random access memory Z cache memory RA-VIZCache, data transformer Connected to the DTC, direct memory access controller DMAC, and bus state controller BSC, and supports a 32-bit data width with the upper 16-bit bus and the lower 16-bit bus. You can do it.
  • the peripheral address bus BUS AO has a bus width of 24 bits, and includes a bus state controller BSC, an interrupt controller I NTC, a serial communication interface SCI, a manorechi function timer timer MTU, a compare match timer CMT, and a watchdog. Connected between each internal circuit of timer WDT and external connection terminal I / ⁇ .
  • Peripheral data bus BUSDO has a bus width of 16 bits, bus state controller BSC, interrupt controller I NTC, serial communication interface SCI, manolech function timer, vaneless unit MTU, compare match timer Internal circuits of CMT and watchdog timer WDT And the external connection terminal I.
  • the control signal line SL is composed of the data transfer controller DTC, direct memory access controller DMAC, bus state controller BSC, use break controller UBC, interrupt controller INTC, serial communication interface SCI, and multifunction timer pulse unit.
  • the internal circuits of the MTU, compare match timer CMT, and A / D converter AZD are connected to each other, and between these internal circuits and the external connection terminal IZO.
  • each external connection terminal I / O is as shown in the list of terminal function examples corresponding to the classification, symbols, input / output, and names, as shown in Fig. 15 to Fig. 18.
  • the 1 and 2 bin chip MFs are assigned functions as shown in Fig. 1 ⁇ , and have 74 input / output terminals and 8 input terminals.
  • FIG. 11 is a functional block diagram showing an example of the internal configuration of the chip AD
  • FIG. 12 is an explanatory diagram showing an example of the terminal functions.
  • the chip AD shows an example of 144 pins.
  • This chip AD has a DRAM and an AS IC, and has a circuit configuration having a memory function that can be written / read at any time and a processing function by a logic circuit.
  • FIG. Circuit VS multiple DRAM banks Bank, main amplifier MA, data transfer circuit DT, digital signal processing circuit DSP, row address buffer RAB, column address buffer CAB, control logic / timing generation circuit CRZTG .
  • the DRAM is a simple dynamic random access memory DR AVI that can be written and read at any time that requires a memory retention operation, a synchronous sink-gate eggplant DRAM (SDRAM) using a clock, and the data output time can be extended Extended data out DRAM (EDO-DRAM).
  • SDRAM synchronous sink-gate eggplant DRAM
  • EEO-DRAM Extended data out DRAM
  • the power supply circuit VS is a circuit that receives the voltage of the power supply V cc and the ground V ss from the outside and supplies necessary power to a plurality of DRAM banks Bank and a main amplifier MA.
  • Each of the plurality of DRAM banks Bank can operate independently.
  • the memory includes, for example, a memory cell, a word decoder, a column decoder, a sense amplifier, and a timing generator.
  • the capacity of these D RAM bank B ank is 256 k bits per bank c.
  • the main amplifier MA is a circuit that performs data input / output between the plurality of DRAM banks B ank and the external connection terminals DO to D31. For example, between each DRAM punk B ank, there are 128 global data lines and many global data lines through which data is exchanged.
  • the data transfer circuit DT switches a data transfer pattern between a DRAM consisting of a DRAM bank B ank and a main amplifier MA and a digital signal processing circuit DSP in real time. For example, it is possible to select one of the adjacent data or clear the data
  • Digital signal processing circuit DSP is a circuit that executes processing of digital signals such as images and sounds.For example, in the case of image processing, processing to remove hidden surfaces by Z comparison, processing to give transparency by ⁇ blending, etc. Execute. Further, c and outputs the data from the serial output port SD0 ⁇ SD 23 to the output device such as a display.
  • This digital signal processing circuit DSP and a data transfer circuit DT is controlled by a control signal C 0 to C 27.
  • the address buffer RAB and the column address buffer CAB are circuits that take in address signals from the external address signal input terminals AO to A10, generate internal address signals, and supply them to the respective DRAM banks B ank.
  • the column address is fetched at the timing of CASL, CASH, CASHL, and CASH at the RAS timing row address.
  • Control logic / timing generation circuit CR / TG is a circuit that generates various timing signals required for the operation of DRAVI.
  • CS is the chip select signal
  • RAS is the row address strobe signal
  • CAS L is the row address strobe signal
  • bar CASH is the column address strobe signals
  • RD bar WR is the read / write signal (high). Level indicates read, low level indicates write).
  • the four column address strobe signals are used to enable byte control (read / write control for each byte). Bottom byte D0 to D7, bar CASH is second lowest byte D8 to D15, bar CAS HL is third lowest byte D16 to D23, bar CAS HH Are for the highest bytes D24 to D31.
  • a plurality of DRAM banks Bank, the row address buffer RAB, and the column address buffer CAB are connected to each other by the internal address bus BUSAI, and further, the row address buffer RAB and the column are connected.
  • the address buffer CAB and the external connection terminal I / O are connected by the peripheral address bus BUS AO, and the main amplifier MA and the external connection terminal I / ⁇ are connected by the peripheral data bus BUSDO.
  • the data transfer circuit DT and the digital signal processing circuit DSP are connected to each other by an address bus and an internal data bus BUS I.
  • the data transfer circuit DT, the digital signal processing circuit DSP and the external connection terminal IZO are connected to each other. They are connected by a peripheral bus BUSO for data and control signals.
  • chip AD as external connection terminals, as shown in Fig. 12, power supply Vcc, ground Vss voltage terminals Vcc, Vss, address terminals A0 to A10, data input / output terminals D0 to D3 1, Chip select pin bar CS, row address strobe pin bar RAS, column address strobe pin bar CAS L, bar CASH, bar CASH L, double CASHH, read / write pin RD / bar WR, clock pin CK: Serial data output terminals SD0 to SD23 and AS IC control signal terminals C0 to C27 are provided.
  • FIG. 13 is a functional block diagram showing an example of the internal configuration of the chip D
  • FIG. 14 is an explanatory diagram showing an example of the terminal functions. Note that chip D shows an example of 50 pins.
  • This chip D has a circuit configuration having only a DRAM and a memory function that can be written and read at any time.
  • a power supply circuit VS a plurality of DRAM banks Bank, amplifier MA, the row address buffer RAB, a column address buffer CAB, control logic Z timing generator CR ZTG is constructed c. from
  • This chip D has a circuit configuration of only the DRAM in which the logic circuit of the data transfer circuit DT and the digital signal processing circuit DSP of the chip AD shown in FIG. Therefore, the internal circuit constituting the chip D is the same as the internal circuit of the chip AD, and the functional description is omitted here.
  • the semiconductor integrated circuit device configured by combining the chip MF and the chip MFA with one or more chips AD and the chip D has one feature of the present invention.
  • Signal terminals common to the connection terminal of the chip MF or the chip MFA and the connection terminal of the chip AD or the chip D are commonly assigned to the same external connection terminal.
  • the connection terminals commonly assigned to the same external connection terminal will be described in detail.
  • FIG. 19 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 7 and 8 and the two 50-pin chips D shown in FIGS. 13 and 14. Note that FIG. 19 shows only the connection between the signal terminal common to the connection terminals of the chip MF and the connection terminal of the chip D and the external connection terminal.
  • the connection terminal which is a terminal, is also connected to the external connection terminal.
  • the address terminals A 0 to A 11 of the chip MF are connected to the address terminals A 0 to A 11 of the two chips D.
  • the data input / output terminals D0 to D31 of the chip MF are divided and connected to the data input / output terminals DQ0 to DQ15 of each chip D. And are connected to the same external connection terminals D0 to D31.
  • the power supply terminal V cc and the ground terminal V ss of the chip MF are connected to the power terminal V cc and the ground terminal V ss of the respective chip D, and also connected to the same external connection terminal V cc and V ss, respectively. I have. Since these voltage terminals are actually assigned to a plurality of terminals such as a chip MF, a chip D, and an external connection terminal, each is connected by the same terminal. Furthermore, according to the control signal, the low address stove terminal bar RAS of the chip MF is connected to the two chips D in common and connected to the external connection terminal bar RAS, and the column address of the chip MF is connected.
  • the trobe terminal bar CAS L and bar CAS H are connected to the column address strobe terminal bar LCAS and bar UCAS of one chip D, and are connected to the external connection terminal bar CASL and bar CASH and the chip MP
  • Column address strobe terminal bar CASHL and bar CASHH are connected to column address strobe terminal bar LCAS and bar UCAS of the other chip D, and are also connected to external connection terminal bar CASH L and bar CAS HH. .
  • the chip MF read Z write terminal RD / bar WR is connected to the two chip D write enable terminals WE in common and connected to the external connection terminal RD / bar WR, and the chip MF chip select terminal
  • the bus CS 3 is commonly connected to the output enable terminal bar OE of the two chips D and is also connected to the external connection terminal bar CS 3.
  • connection terminals of the chip D are common to the connection terminals of the chip MF and are connected to the same external connection terminals.
  • connection terminals that are independent signal terminals only in the chip MF. Therefore, external connection terminals connected to the independent connection terminals are also included. It is provided so that it can be connected to the outside.
  • FIG. 20 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 7 and 8 and the 144-pin chip AD shown in FIGS. 11 and 12. Note that FIG. 20 also shows only the connection between the signal terminal common to the connection terminal of the chip MF and the connection terminal of the chip AD and the external connection terminal as in FIG. However, actually, the connection terminal, which is a signal terminal independent of only the chip MF and the chip AD, is also connected to the external connection terminal.
  • the address terminals A0 to A10 of the chip MF are connected to the address terminals A0 to A10 of the chip AD and are the same.
  • data input / output terminals D0 to D31 of chip MF are connected to data input / output terminals D0 to D31 of chip AD. And are connected to the same external connection terminals DO to D31.
  • the power supply terminal V cc: and the ground terminal V ss of the chip MF are connected to the power supply terminal V cc and the ground terminal V ss of the chip AD, respectively, and are also connected to the same external connection terminals V cc and V ss, respectively. Note that these voltage terminals are actually assigned to multiple terminals of the chip MF, chip AD, and external connection terminal, so each is connected by the same terminal.
  • control signals include the row address strobe terminal bar RAS of the chip MF, the column address strobe terminal bar CAS L, the bar CASH, the bar CA SHL, the bar CASHH, the read Z write terminal RD / bar WR, and the chip select.
  • Tato pin CS 3 and clock pin CK are the chip AD row address strobe pin bar RAS, column address strobe pin bar CAS L, bar CASH, bar CASH L, bar CASHH, read / write terminal RD / bar WR, switch Connected to CS3 and clock terminal CK, respectively, and the same external connection terminal, rowless strobe terminal bar RAS, columnless strobe terminal bar CASL, bar CASH, bar CASH L, bar CA Connect to SHH, read / write terminal RD / NO terminal WR, chip select terminal / CS3, clock terminal CK Have been.
  • the serial data outputs SD O to SD 23 and the ASIC control signal terminals C 0 to C 27 which are signals specific only to the chip AD are actually provided.
  • external connection terminals connected to these independent connection terminals are also provided so as to be connectable to the outside.
  • the DRAM of the chip AD and the chip D is a synchronous DRAM, it is necessary to further synchronize the semiconductor integrated circuit device.
  • the clock terminal to which the clock signal is assigned is also connected to the same external connection terminal as a common connection terminal.
  • a semiconductor integrated circuit constituted by a combination of a chip MF and a chip MFA and one or more chips AD and chips D
  • the outline of the read, write, and refresh operations from the processor CU of the chip MF (chip MFA) to the DRAVI of the chip AD (chip D) will be described.
  • the processor C mouth ⁇ ⁇ address strobe signal RAS from PU and Karamuadore address strobe signal bar C 2 one synchronization signal is required c of AS.
  • RAS high
  • the RAS circuit is precharged, and no memory operation is performed inside the chip during this period.
  • the period when CAS is high is the period during which CAS circuits such as the data output buffer and the data input buffer are precharged. During this period, read / write operations with the outside of the chip AD are not performed.
  • the RAS circuitry When RAS goes low (L), the RAS circuitry is activated and memory operation begins. Subsequently, when the bar CAS becomes L, a read operation or a write operation starts, and data is exchanged with the chip MF outside the chip AD. As described above, in the DRAM of the chip AD, the precharge period and the active period are alternately repeated. Usually, the cycle time of RAS is the cycle time of chip AD.
  • the read operation is specified by setting the write enable signal WE to H before the falling edge of CAS and holding the signal until CAS rises. Once the data has been output, it is held until CAS rises.
  • RAS access time the time from the fall of RAS and CAS to the output of data to the data output terminal
  • CAS access time the time from when the column address is determined to when the data is output.
  • the relationship between the address signal and the RAS and CAS signals is the same as in the read operation, so the description is omitted here.
  • the timing specifications of RAS and CAS, such as cycle time, are the same as in the read operation.
  • bar WE to bar CAS Write operation is specified by setting L before the falling point of. During this cycle, the data output terminal is kept in the high impedance state.
  • the specification of the Read Modify Write operation in which the data once read to the chip VIF outside the chip AD is changed by the chip MF while the base RAS is kept at L, and then written to the same memory cell again There is also.
  • refresh operations There are two types of refresh operations: interrupt operations during random access operations such as read and write operations, and refresh operations that are performed only to retain information stored inside the chip AD during the battery backup period.
  • RAS refresh and CBR (bar CAS RAS) RAS refresh are standard.
  • CBR bar CAS RAS
  • self refresh is standard.
  • a RAS online refresh all memory cells in one row (word line) are simultaneously refreshed during one cycle of a RAS bar having the same timing standard as a read operation and a write operation.
  • the bar CAS must be set to H and a refresh address must be given from the chip MF outside the chip AD.
  • Distributed refresh is one in which one refresh operation is evenly distributed over the maximum refresh period. Actually, since distributed refresh is frequently used, one cycle of the refresh operation is the timing that interrupts the normal read / write operation cycle.
  • CBR refresh is internally determined to be a refresh operation by setting CAS low before RAS. An address is generated from an internal refresh address counter by this determination pulse, and a lead line is selected and refreshed. Therefore, it is not necessary to give an address from outside the chip AD.
  • self-refresh is performed after the end of a normal memory cycle. And set the pulse width of the RAS to, for example, 1 ⁇ m ⁇ s or more. Internally, when this time is exceeded, the refresh operation using the refresh address counter and refresh timer starts, and self-refresh continues as long as both RAS and CAS are low. The less frequently the chip is refreshed, the lower the power consumption of the chip AD, but this frequency is automatically adjusted by a timer that detects the temperature inside the chip AD. To shift from the self-refresh to the normal cycle, a RAS bar precharge period is required.
  • the read operation, write operation, and refresh operation from the processor CPU of the chip MF to the DRAM of the chip AD are performed.
  • the refresh self-refresh operation one feature of the present invention is described. ⁇ As a chip
  • the circuit configuration is such that the logic circuit inside the AD can execute the refresh operation / access operation.
  • the following describes in detail that the refresh operation and the Z access operation can be executed during the self-refresh operation.
  • FIG. 21 is a schematic configuration diagram schematically showing an example of internal functions of the chip AD shown in FIG.
  • This chip AD is composed of a dynamic random access memory DRAM, a memory built-in logic Logic, and a DRAM access control circuit DAC.
  • the DRAM, logic logic with built-in memory, and DRAM access control circuit DAC shown in FIG. 21 are respectively composed of a DRAM section formed by a plurality of DRAM banks Bank and a main amplifier MA shown in FIG. It supports the AS IC part by the transmission circuit DT and the digital signal processing circuit DSP, and the access control part by the row address buffer RAB and column address buffer CAB.
  • the input buffer IB and the output buffer OB are connected to a circuit I / O for performing data input / output between the main amplifier MA and the external connection terminals D0 to D32 shown in FIG. 11 and a digital signal processing circuit DSP.
  • Circuit IZ ⁇ for performing data input / output between the main amplifier MA and the external connection terminals D0 to D32 shown in FIG. 11 and a digital signal processing circuit DSP.
  • the chip select signal bar CS, the row address stop signal bar RAS, the column address stop signal bar CAS are the control signal terminals, and the address signal is the DRAM access control circuit via the address terminal.
  • Data is input to the DAC and data signals can be input / output via the data input / output terminals.
  • the DRAM and the DRAVI access control circuit DAC are connected by the address bus BUSA, and the DRAM, the logic logic inside the memory, and the data bus BUSD are connected between the logic Logic and the data input / output terminal.
  • the data bus BUS D of this part has a data width of 64 bits, which is wider than that of the data input / output terminal, which corresponds to, for example, 8 bits.
  • the logic with built-in memory and the DRAM access control circuit DAC are connected by an address bus and a control signal line, and the DRAM access control circuit DAC has a self-connection to the logic with built-in memory.
  • a refresh operation enable signal is output, and a read Z write signal R / W and an address signal are output from the logic L 0 gic in the memory to the DRAM access control circuit DAC.
  • the read / write signal RZW can be output separately for the read signal R and the write signal W.
  • a data input / output inhibit signal DIS is output from the DRAM access control circuit DAC to the input buffer IB and the output buffer OB.
  • FIG. 22 is a configuration diagram showing a detailed example of the DRAM access control circuit DAC.
  • the DRAM access control circuit DAC includes an internal control signal generation circuit CSG, a plurality of selector circuits SC, and the like.
  • the chip select signal bar CS and the row address strobe signal input to the internal control signal generation circuit CSG are provided. Based on the RAS and column address strobe signal CAS, it generates an address selection control signal, etc., and also generates a self-refresh operation enable signal to provide the logic Logic with built-in memory. Output.
  • the logic inside the memory that has received this permission signal can access the DRAM, and outputs a read Z write signal R / W to the DRAM access control circuit DAC to issue a read Z write request. And outputs an address signal to the DRAM access control circuit DAC to select an arbitrary memory cell. Data can be read and written between the stored memory cell and the built-in memory logic. Note that the read / write request can be made by outputting a read signal R when making a read request and by writing a write signal W when making a write request.
  • the address control signal generated by the internal control signal generation circuit CSG is used to access the chip MF outside the chip AD from the processor CPU, and to access the chip AD from a part of the memory AD logic memory. In response to this, one is selected via the selector circuit SC and used as an address control signal for selecting an arbitrary memory cell of the DRAM.
  • FIG. 23 is an explanatory diagram showing an example of a transition state of the operation mode by the internal control signal generation circuit CSG.
  • This operation mode can be divided into the normal DRAV1 access operation mode, the DRAM senoref refresh operation mode, and the access operation mode using the internal logic logic of the internal memory.
  • a transition to the operation mode is made without reading from the logic inside the built-in port logic Logic Read Z write signal RZw and no request for Z write, and the return to the normal DRAM access operation mode is performed by releasing the refresh.
  • transition from the self-refresh operation mode to the internal access operation mode is made when there is a read Z write request from the logic inside the memory, and the return to the self-refresh operation mode is performed by the completion of the read Z write. .
  • transition from the normal DRAM access operation mode to the internal access operation mode is performed when there is a read / write request from the logic inside the memory Logic, and to return to the normal DRAM access operation mode, release the refresh. It is performed by
  • FIG. 24 is an operation timing chart showing a control example of the DRAM access control circuit DAC including the internal control signal generation circuit CSG for the DRAM.
  • a normal DRAM access period in which a normal DRAM access can be executed, and the normal DRAM access period and the normal DRAM access period are compared.
  • the DRAM self-refresh period is a period during which normal access operation from the chip-VIF to the DRAM is not performed.
  • a self-refresh operation enable signal is output to the logic logic in the memory based on the address strobe signal RAS and the column address strobe signal CAS in synchronization with the clock signal CK.
  • the refresh operation is canceled only when an access operation for read / write by the control signal R / W to the DRAM is requested from the logic Logic of the memory, and the logic Logic of the DRAM (digital The access operation from the signal processing circuit (DSP) is enabled:
  • the execution of the refresh no-access operation during the self-refresh period can be performed, for example, as shown in FIG. 24 (b), by repeating the read operation in accordance with the read request by the control signal R, and at the same time
  • the refresh operation can be performed during the period between the two, and the read operation can be repeated in response to the write request by the control signal W.
  • the refresh operation can be performed during the period between the write and the write, and the read operation using the control signal R can be performed.
  • the access operation of reading and writing can be repeated according to the output request and the write request by the control signal W, and the refresh operation can be executed during the period between the access operations.
  • the logic A of the memory with the memory of the chip AD can access the DRAM and the logic of the memory with the memory L O the write request from g ics can write data to the DRAM, and may be reading data from the DRAM by the read request.
  • the access operation to the DRAM by the logic built into the memory of the chip AD during the self-refresh operation is the same when the other chip is connected to the chip AD.
  • the chip MFA or the CPU Similar effects can be expected for other semiconductor chips including.
  • the present invention can be applied to a semiconductor integrated circuit device having a package structure capable of performing an access operation to a DRAM of a portable AD and a self-refresh operation of the DRAM.
  • FIG. 25 is an overall perspective view of the package of the present embodiment
  • FIG. 26 is a sectional view of the package.
  • the first chip MF microcomputer with flash memory
  • a microphone port computer and a flash memory are formed is sealed in a first TCP (Tape Carrier Package) 1A.
  • the second chip AD DRAM on-chip mouthpiece
  • these two TCPs 1A and IB are vertically mounted. It has a stacked TCP structure that is superimposed and bonded together.
  • the first chip MF sealed in the first TCP 1A has its main surface (element formation surface) facing down in a device hole 3a opened in the center of the tape carrier 2a.
  • the tape carrier 2a is electrically connected to one end (inner lead portion) of a lead 5a formed on one surface of the tape carrier 2a via a bump electrode 4 formed on the periphery of the main surface.
  • the main surface of the chip MF is covered with a botting resin 6 for protecting the LSI (microphone computer with flash memory) formed on the main surface from the external environment.
  • the lead 5a formed on one surface of the tape carrier 2a has a pattern as shown in FIG.
  • the surfaces of these leads 5a are covered with the solder resist 7 except for one end (inner lead portion) protruding into the device hole 3a.
  • the other end of each lead 5a is electrically connected to a through hole 8a penetrating from one surface of the tape carrier 2a to the other surface.
  • These through holes 8a are arranged in two rows along the four sides of the tape carrier 2a, and the surface of each through hole 8a is printed with this laminated TCP as shown in Fig. 26.
  • Solder bumps 9 serving as external connection terminals when mounted on a wiring board are joined.
  • the second TCP 1 B is stacked on the first TCP 1 A. TCP 1 A and TCP 1 B are tightly joined by adhesive 10 applied to the mating surface of both Have been.
  • the second chip AD sealed in the TCP 1B is disposed with its main surface facing downward in a device hole 3b opened in the center of the tape carrier 2b. It is electrically connected to one end (inner lead portion) of a lead 5b formed on one surface of the tape carrier 2b via a bump electrode 4 formed on the periphery of the main surface.
  • the main surface of the chip AD is covered with a potting resin 6 for protecting the LSI (DRAM on-chip logic) formed on the main surface from the external environment.
  • the outer diameter of the tape carrier 2b of the TCP 1B is the same as the tape carrier 2a of the TCP 1A.
  • the dimensions of the device hole 3b of the tape carrier 2b are smaller than the device holes 3a of the tape carrier 2a, since the outer diameter of the chip AD is smaller than that of the chip MF.
  • the lead 4b formed on one surface of the tape carrier 2b has a pattern as shown in FIG.
  • the other end of each lead 5b is electrically connected to a through hole 8b penetrating from one surface of the tape carrier 2b to the other surface.
  • These through holes 8b are arranged in two rows along the four sides of the tape carrier 2b, like the through holes 8a of the tape carrier 2a.
  • the through holes 8a of the tape carrier 2a and the through holes 8b of the tape carrier 2b are formed with the same number and the same pitch, respectively, and the through holes facing each other when the tape carriers 2a and 2b are overlapped.
  • the holes 8a and 8b are arranged so as to overlap each other exactly.
  • connection terminals (pins) common to the two chips MF and AD that is, having the same function
  • pins are arranged at the same position on the tape carriers 2a and 2b. It is electrically connected through the through holes 8a and 8b, and is commonly drawn to the outside (printed circuit board) via the solder bumps 9 joined to one end of the through hole 8a.
  • FIG. 27 the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 200) of the through holes 8a formed on the tape carrier 2a are given.
  • FIG. 28 shows the connection terminal numbers (1 to 144) formed on the chip AD. And the number (1 to 200) of the through hole 8b formed in the tape carrier 2b. The same numbers are given to the through holes 8a and 8b arranged at the same position on the tape carriers 2a and 2b.
  • Table 1 shows an example of the assignment of the connection terminals for the chips MF and AD and the through holes 8a and 8b.
  • the numbers (1 to 144) in the MF pin # column correspond to the connection terminal numbers (1 to 144) of the chip MF shown in Fig. 27, and the numbers (1 to 144) in the AD pin # column. 144) correspond to the connection terminal numbers (1 to 144) of the chip AD shown in FIG.
  • the numbers in the Via # column are the numbers (1 to 200) of through holes 8a and 8b shown in FIGS. This is the number assigned to the terminal.
  • connection terminals common to the chips MF and AD are arranged at substantially the same positions on the chips MF and AD.
  • the leads 5a and 5b of the tape carriers 2a and 2b can be easily routed and the lead length can be reduced, so that the data transfer of the chips MF and AD can be speeded up.
  • the tape carrier 2a since the number of required through holes 8a and 8b can be minimized, the tape carrier 2a,
  • the package size can be reduced by reducing the outer diameter of 2b.
  • each member constituting the laminated TCP of the present embodiment is formed of the following materials and dimensions.
  • the tape carriers 2a and 2b are made of a polyimide resin film having a thickness of 75 m.
  • the leads 5a and 5b are made of 18 ⁇ thick Cu (copper) foil, and Au (gold) or Sn (tin) plating is on the surface of one end (inner lead). Is given.
  • the adhesive 10 is made of polyimide resin and has a thickness of 12 ⁇ m.
  • the solder resist 7 is made of an epoxy resin and has a thickness of 20 ⁇ m.
  • the solder bumps 9 serving as external connection terminals and the solders 11 in the through holes 8a and 8b are made of a lead (Pb) -tin (Sn) alloy.
  • the chip MF and the chip AD are made of single-crystal silicon with a thickness of 50 ⁇ m, and the botting resin 6 for protecting their main surfaces is made of epoxy resin.
  • the bump electrodes 4 formed on the main surfaces of the chip MF and the chip AD are made of Au, and their height is 20 ⁇ m. That is, in this laminated TCP, the total thickness of the chip MF and the bump electrode 4 is smaller than the thickness of the tape carrier 2a, and the total thickness of the chip AD and the bump electrode 4 is smaller than the thickness of the tape carrier 2b. Because it is thin, the thickness in the stacking direction except for the solder bumps 9 is 21.8 ⁇ , making it an ultra-thin package.
  • FIGS. 29A to FIG. 33A are cross-sectional views of TCP IB, and FIG. 29B is a cross-sectional view of TCP 1A.
  • tape carriers 2a and 2b made of polyimide resin film are prepared, punched out, and device holes are placed in tape carrier 2a.
  • tape carriers 2a and 2b are long films wound on reels, but the figure shows only a part of them (one TCP 1A and 1B each).
  • a Cu foil is laminated on one surface of each of the tape carriers 2a and 2b, and the Cu foil is wet-etched to form leads 5a on the tape carrier 2a. Then, leads 5b are formed on the tape carrier 2b. At the same time, a Cu foil hole 12a is formed at one end of the through hole 8a, and a Cu foil hole 12b is formed at one end of the through hole 8b.
  • a Cu foil hole 1 2 The diameter of a is smaller than the through hole 8a, and the diameter of the Cu foil hole 12b is smaller than the through hole 8b.
  • the Cu foil has a smaller thermal expansion coefficient and higher dimensional stability than the polyimide resin substrates 2a and 2b, the diameter of the Cu foil holes 12a and 12b is reduced. If the through holes 8a and 8b are smaller than the through holes 8a and 8b, the positioning when the tape carrier 2a and the tape carrier 2b are overlapped using the through holes 8a and 8b in a later process. It can be performed with high accuracy.
  • a solder resist 7 is applied to the lower surface of the tape carrier 2 a.
  • the adhesive 10 is applied to the lower surface of the tape carrier 2b.
  • the bump electrodes 4 formed on the connection terminals of the chip MF and the leads 5a of the tape carrier 2a are collectively connected by a gang bonding method.
  • the bump electrodes 4 formed on the connection terminals of the chip AD and the leads 5b of the tape carrier 2b are collectively connected by a gang bonding method.
  • the chip MF and chip AD are polished on the back surface in advance in the wafer state, and then thinned to 5 ⁇ by spin etching.
  • the bump electrode 4 is formed in the final step of the wafer process by using a stud bump bonding method.
  • Lead 5 Au or Sn plating is applied to the inner lead portions of a and 5b, so that the lead 5a and the bump electrode 4 and the lead 5b and the bump electrode 4 are Au-Au joint or Au-S
  • the bonding between the c- leads 5a and 5b and the bump electrode 4 to be bonded by n-eutectic bonding may be performed by a single point bonding method instead of the gang bonding method.
  • bottling resin 6 is applied to the main surface of chip MF and the gap between tape carrier 2a and device hole 3a using a resin bottling dispenser. I do.
  • potting resin 6 is applied to the main surface of chip AD and the gap between tape carrier 2b and device hole 3b.
  • the long tape carriers 2a and 2b are separated into individual pieces using a cutting die, and each of the tape carriers 2a and 2b is mounted on a socket and subjected to an aging inspection. Sort out. Aging of the tape carriers 2a and 2b is performed by applying socket pins to test pads formed on each part of the tape carriers 2a and 2b.
  • the tape carriers 2a and 2b are overlapped and heated and pressed together so that the positions of the opposed through holes 8a and 8b exactly match, and the adhesive 10 is used.
  • TCP 1A and 1B are made into one package.
  • the chip MF is thinner than the tape carrier 2a and the chip AD is thinner than the tape carrier 2b
  • TCP 1A and TCP 1B can be tightly joined.
  • the positioning of the through hole 8a and the through hole 8b uses the Cu foil holes 12a and 12b described above. Alternatively, test pads formed on a part of each of the tape carriers 2a and 2b may be used.
  • solder paste made of a lead (Pb) -tin (Sn) alloy is embedded in the through holes 8a and 8b by screen printing, and the paste Is reflowed to form solder 11 1.
  • solder bump 9 is formed at one end of the through hole 8a of the tape carrier 2a, whereby the stacked TCP shown in FIGS. 1 and 2 is completed.
  • Solder bumps 9 are placed beforehand with the solder bump forming surface of tape carrier 2a facing up.
  • the solder ball that has been formed is positioned on the through hole 8a, and then the solder ball is formed by reflow.
  • solder bumps arranged on the surface of the glass substrate may be transferred to the surface of the through hole 8a to form ⁇ solder bumps 9, which are formed by solder 11 filled inside the through holes 8a and 8b.
  • solder bumps arranged on the surface of the glass substrate may be transferred to the surface of the through hole 8a to form ⁇ solder bumps 9, which are formed by solder 11 filled inside the through holes 8a and 8b.
  • Pb low melting point lead
  • Sn low melting point lead
  • solder bumps 9 are positioned on the electrodes 15 of the printed wiring board: 14, and then, The solder bumps 9 need only be lifted.
  • heat generated from the chips MF and AD mainly escapes to the board through the solder bumps 9, so when stacking TCPs 1A and 1B, a chip having a larger amount of heat generation is required. Place it on the lower side (closer to the board).
  • the chip MF that forms the microcomputer with flash memory has a larger number of functional blocks and generates more heat than the chip AD that forms the DRAM on-chip logic.
  • Chip MF is arranged.
  • arranging a chip having a large number of connection terminals on the lower side (substrate side) facilitates routing of wiring connecting the chip connection terminals and external connection terminals.
  • a DRAM memory cell formed in the chip AD adopt a stacked-type capacitor (STC) structure.
  • STC stacked-type capacitor
  • a radiation fin 16 made of a metal having high thermal conductivity such as A1 may be attached to the upper part of the stacked TCP as shown in FIG.
  • a chip MF that generates a large amount of heat is arranged above the chip AD (on the side close to the radiation fins 16).
  • solder 11 is embedded in the through holes 8a and 8b facing each other (see Figs. 34 and 35). Force You can package TCP 1A and 1B in the following way.
  • TCP 1A and TCP 1B are individually formed according to the method described above.
  • a solder paste lip is buried inside the through hole 8a of the TCP 1A, and a solder paste 11p is buried inside the through horn 8b of the TCP 1B.
  • a stall printing method is used for the embedding of the solder paste 11p.
  • the tape carriers 2a and 2b are overlapped and heated and pressed, and the two are joined with an adhesive 10 and the solder paste 11p is reflowed to form a through hole 8.
  • Solder 11 is formed inside a, 8b. Subsequent steps are the same as the above-mentioned manufacturing method.
  • TCP 1 A and TCP 1 B are temporarily attached by the adhesive force of the solder paste lip, so that the stacked TCP 1 A and 1 B are transported to a heating furnace or the like and heated and pressed together.
  • the gap between the facing through holes 8a and 8b can be prevented.
  • tape carriers 2a and 2b are overlapped to form TCP 1A and 1B into one package, and then tape carriers 2a and 2b are drilled.
  • a conductive layer may be formed inside the hole by an electroless plating method.
  • the chips MF and AD can be sealed by a transfer molding method instead of the above-mentioned botting method.
  • the bump electrode 4 of the chip MF is electrically connected to the lead 5a of the tape carrier 2a in accordance with the method described above, and the bump electrode 4 of the chip AD and the tape carrier are electrically connected. 2b lead 5b is electrically connected.
  • the chips MF and AD are sealed with a mold resin 17.
  • the tape carriers 2a and 2b are each molded with a mold. Attach and seal multiple chips MF and AD in batches. Epoxy resin is used for the mold resin 17.
  • a structure in which the entire surface of the chips MF and AD is covered with the mold resin 17 and the back surface of the chips MF and AD is exposed from the mold resin 17 may be employed.
  • the resin processed into a sheet is applied to the upper surfaces of the tape carriers 2a and 2b and heated and pressed, so that the resin flows into the main and side surfaces of the chips MF and AD.
  • the thickness of the mold resin 17 for encapsulating the chips MF and AD is extremely thin, the case where the back surface of the chips MF and AD is exposed from the mold resin 17 or the case of the chips VIF and AD
  • the mold resin 17 has a low coefficient of thermal expansion, and it is necessary to select a material close to the coefficient of thermal expansion of the chips MF and AD.
  • the tape carriers 2a and 2b are separated into individual pieces using a cutting die, and the individual TCPs 1A and 1B are subjected to an aging test to select non-defective products.
  • the tape carriers 2a and 2b are overlapped and heated and pressed together so that the positions of the facing through holes 8a and 8b are exactly matched, and the two are joined with an adhesive 10.
  • the solder 11 is formed inside the through holes 8a and 8b according to the method described above, and the solder bump 9 is formed at one end of the through hole 8a of the tape carrier 2a.
  • TCP is completed.
  • the TCP 1A, 1 B may be stacked to form a single package.
  • the chip MF and the chip AD may be simultaneously and collectively sealed with the mold resin 17.
  • the bump electrode 4 of the chip MF and the lead 5a of the tape carrier 2a are electrically connected according to the method described above, and the bump electrode 4 of the chip AD and the tape carrier 2b.
  • the tape carriers 2a and 2b are overlapped and heated and pressed together, and the two are joined with an adhesive 10.
  • the chips MF and AD are simultaneously.
  • solder 11 is formed inside through holes 8a and 8b according to the method described above, and solder is attached to one end of through hole 8a of tape carrier 2a.
  • the bump 9 is formed.
  • the outer diameter dimension accuracy of the sealing portion is improved compared to the method of sealing the chips MF and AD with the botting resin 6.
  • the sealing time can be reduced. Can be shortened.
  • the thickness of the mold resin 17 is made the same as that of the tape carriers 2a and 2b, there is no gap between TCP 1A and TCP 1B, so that TCP 1A and TCP 1B It is possible to prevent problems such as accumulation of moisture during the process, and to manufacture a highly reliable stacked TCP.
  • the external connection terminals can be formed by the leads 5a and 5b.
  • a method of manufacturing the laminated TCP will be described with reference to FIGS.
  • a tape carrier 2a, 2b made of polyimide resin film is punched out to form a device hole 3a in the tape carrier 2a, and a device hole 3b in the tape carrier 2b. I do. These through holes 8a and 8b are not formed in these tape carriers 2a and 2b.
  • a lead 5a is formed on the tape carrier 2a according to the method described above, and a lead 5b is formed on the tape carrier 2b, and one end (inner lead portion) is formed.
  • a solder resist 7 is applied to one surface of the tape carrier 2a, and an adhesive 10 is applied to one surface of the tape carrier 2b.
  • the leads 5a and 5b are formed in such a length that their other ends (outer leads) can be used as external connection terminals.
  • the bump electrode 4 of the chip MF and the lead 5a of the tape carrier 2a are electrically connected according to the method described above, and the bump electrode 4 of the chip AD and the lead of the tape carrier 2b are connected.
  • the chips MF and AD are sealed with botting resin 6.
  • the tape carriers 2a and 2b are separated into individual pieces, and the individual TCPs 1A and 1B are subjected to an aging test to select non-defective products.
  • the TCPs 1A and 1B are made into one package by overlapping and joining the tape carriers 2a and 2b according to the method described above, and then, as shown in FIG.
  • the tape carriers 2a and 2b supporting the other ends (outer lead portions) of the leads 5a and 5b are cut and removed.
  • the other ends of the leads 5a and 5b Is formed into a gull wing shape using a lead molding die. Leads 5a and 5b are molded simultaneously using the same mold.
  • this laminated TCP electrically connects the common connection terminals of the two chips MF and AD through the leads 5a and 5b, and externally (printed wiring) through the leads 5a and 5b. Board).
  • the illustrated stacked TCP may be arranged such that the chip S MF, the force S arranged with the main surface of the AD facing upward, and the force S arranged downward.
  • the chips MF and AD are sealed with the potting resin 6, the chips MF and AD may be sealed with the mold resin 17 as shown in FIG.
  • the manufacturing process is simplified as compared with the above-mentioned laminated TC # in which the external connection terminals are constituted by the solder bumps 9. Therefore, the manufacturing cost of the stacked TCP can be reduced. Also, since it is not necessary to provide the through holes 5a and 5b in the tape carriers 2a and 2b, it is easy to route the leads 5a and 5b and reduce the manufacturing cost of the tape carriers 2a and 2b. You can also.
  • the time required for forming the external connection terminals can be reduced. Also, connect the other end (outer lead) of leads 5a and 5b.
  • the electrodes 15 on the printed wiring board 14 By overlapping and connecting the electrodes 15 on the printed wiring board 14, the area of the electrodes 15 occupying the surface of the printed wiring board 14 can be reduced, and the mounting of the stacked TCP (lead 5 a , 5b and the electrode 15) can be performed once.
  • the leads 5a and 5b which constitute the external connection terminals, may be individually molded using two dies. In this case as well, as shown in Fig. 56 (chip MF, AD sealed with bottling date 6) and Fig. 57 (chip MF, AD sealed with mold resin 17), 2
  • the leads 5a and 5b connected to the common connection terminal of the two chips MF and AD are connected to the same electrode 15 of the printed wiring board 14.
  • the external connection terminal is formed by forming the other end (outer lead) of the lead 5a formed on the lower TCP 1A into a gull-wing shape, and the TCP 1A and TCP 1A Electrical connection with B is made through solder 11 embedded in through holes 8a and 8b formed in tape carriers 2a and 2b.
  • the above structure, in which the external connection terminals are composed of gull-wing-shaped leads, is flexible in that the stress applied to the connection between the laminated TCP and the printed wiring board due to the difference in the coefficient of thermal expansion between them is flexible. Absorbing and mitigating due to the deformation of the leads, the connection reliability with the board is higher than the structure where the external connection terminals are composed of solder bumps.
  • the package of the present invention can be mounted on the printed wiring board 14 individually without forming the TCP 1A and the TCP 1B into one package.
  • the mounting density is lower than that of the stacked TCP in which TCPs 1A and 1B are packaged in one package, but the process of stacking TCPs 1A and 1B into one package is not required.
  • the manufacturing cost of the package can be reduced.
  • the stacked TCP of the present invention is used in a PGA (Pin Grid Array) type package, as shown in FIG. 60, instead of a method in which external connection terminals are formed by solder bumps 9 and leads 5a and 5b.
  • the external connection terminal can also be configured with pin 18.
  • the surface of the pin 18 is plated with Sn (tin) or the like, and is electrically connected to the leads 5a and Z or the lead 5b inside the through holes 8a and 8b.
  • the chip MF and the lead 5a and the chip AD and the lead 5b can be connected by using an anisotropic conductive film.
  • an anisotropic conductive film To manufacture a laminated TCP using an anisotropic conductive film, first, as shown in Fig. 61, the device hole 3a, the through hole 8a and the lead 5a are formed in the tape carrier 2a according to the method described above. After forming device holes 3b, through holes 8a and leads 5b on the tape carrier 2b, a solder resist 7 is applied to one side of the tape carrier 2a, and one side of the tape carrier 2b is formed. Adhesive 10 is applied to the substrate.
  • the anisotropic conductive film 19a which has been cut to the same size as the device hole 3a of the tape carrier 2a in advance, projects into the device hole 3a. Position on one end (inner lead) of lead 5a.
  • an anisotropic conductive film 19b previously cut to approximately the same size as the device hole 3b of the tape carrier 2b is used to project 19b from the lead 5b projecting into the inside of the device hole 3b. Position it on one end (inner lead).
  • the chip MF on which the bump electrodes 4 are formed is positioned on the anisotropic conductive film 19 a with the main surface facing down, and then the anisotropic conductive film 1 is positioned.
  • bump electrode 4 and lead 5a are electrically connected via conductive particles in anisotropic conductive film 19a.
  • the anisotropic conductive film 19 b is heated and pressed.
  • the bump electrode 4 and the lead 5b are electrically connected via conductive particles in the anisotropic conductive film 19b.
  • the tape carriers 2a and 2b are separated into individual pieces, and each TCP 1A and 1B is subjected to an aging test to select non-defective products.
  • the tape carriers 2a and 2b are superimposed according to the above-described method to form TCPs 1A and 1B into one package, and then, as shown in Fig. 65, Solder 11 is filled in 8a and 8b, and solder bump 9 is formed on one end of throughhorn 8a.
  • the various stacked TCPs of the present invention described above are applied not only to the case where the chip MF and the chip AD are combined, but also to the above-described configuration examples of the chip MFA + chip D, the chip MFA + chip AD, the chip MF + chip D, and the like. Of course, you can.
  • the stacked TCP of the present invention can also be applied to a case where three or more chips are stacked. it can.
  • the stacked TCP shown in Fig. 66 has a chip MF that forms a microcomputer and flash memory encapsulated in TCP 1A, and two chips D and D 2 that form only DRAM are connected to two TCP 1A. It has a laminated TCP structure in which it is sealed in CTCP1D, and these three TCP1A1C1Ds are vertically overlapped and joined together.
  • the chip MF sealed in the lowermost TCP 1A is placed in the device hole 3a of the tape carrier 2a with its main surface (element forming surface) facing upward, and the periphery of the main surface It is electrically connected to one end (inner-lead portion) of a lead 5a formed on one surface of the tape carrier 2a via a bump electrode 4 formed in the portion.
  • the chip MF is sealed with a mold tree 17.
  • the lead 5a formed on one surface of the tape carrier 2a has a pattern as shown in FIG.
  • chip D At the top of Ding CP 1 A, chip D, and sealed TC P 1 C is stacked, further TC P 1 D sealing the chip D 2 at its upper portion are stacked.
  • the chip D i sealed in the TCP 1 C is placed in a device hole 3 c opened in the center of the tape carrier 2 c with its main surface facing upward. It is electrically connected to one end (inner lead portion) of a lead 5c formed on one surface of the tape carrier 2c via the bump electrode 4 formed on the tape carrier 2c.
  • chip D 2 sealed in TCP 1 D is placed with its main surface facing upward in device hole 3 d opened in the center of tape carrier 2 d, and its main surface is It is electrically connected to one end (inner lead portion) of a lead 5d formed on one surface of the tape carrier 2d via a bump electrode 4 formed at the center of the tape carrier 2d.
  • chips D and D 2 are also sealed with the mold resin 17.
  • the lead 5c formed on one surface of the tape carrier 2c has a pattern as shown in FIG. 68, and the lead 5d formed on one surface of the tape carrier 2d is formed as shown in FIG. It has a pattern.
  • connection terminals (pins) common (that is, having the same function) of the three chips MF D and D 2 are arranged at the same positions on the tape carrier 2 a 2 c 2 d through holes 8. a 8 c 8 d
  • the structure is such that the lead 5a formed on the carrier 2a is commonly drawn to the outside (printed circuit board) through the other end (outer lead) of the lead 5a.
  • the external connection terminals can be constituted by the above-mentioned solder bumps and pins in addition to leads.
  • the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 144) of the through holes 8a formed on the tape carrier 2a are given.
  • FIG. 67 the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 144) of the through holes 8a formed on the tape carrier 2a are given.
  • FIG. 67 the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 144) of the through holes
  • Figure 69 is a number of connection terminals formed on the chip D 2 (1-46) and a tape carrier 2 d to form through holes 8 d number: are then (. 1 to L 44) Togazuke. The same numbers are given to the through holes 8a, 8c, 8d arranged at the same position on the tape carriers 2a, 2c, 2d.
  • the package of the present invention is not limited to the above-described structure, and various design changes can be made to its details.
  • a structure in which the chip MF sealed in the TCP 1 A and the lead 5 a formed in the tape carrier 2 a are electrically connected by the Au wire 20 can be adopted.
  • the chip MF and chip AD are not packaged in a single package, but are individually sealed in QFP (Quad Flat package) type packages. It can also be mounted on a wiring board 14.
  • the package of the present invention is a device or system such as a multimedia device or an information home appliance, for example, a car navigation system as shown in FIG. 73, a D-ROM (Compact Disk ROM) driving device as shown in FIG. It is used for a game device as shown, a PDA (Personal Digital Assistance) as shown in FIG. 76, a mobile communication device as shown in FIG. 77, and the like.
  • Fig. 73 is a functional block diagram showing an example of the internal configuration of the car navigation system. is there.
  • This car navigation system includes a control unit, a display unit connected to the control unit, a GPS and a CD-ROM.
  • the control unit consists of a main CP, program EPROM (4), work RAM (SRAM: 1M), I / O control circuit, ARTOP, image RAM (DRAM: 4VI), and ROM for CG (Computer Graphics). (Mask ROM: 4M), gate array, etc.
  • the display unit is composed of a computer with a slave microphone, TFT, etc.
  • the main CPU of the control unit controls according to a control program stored in a program EPROM.
  • the control unit compares the position information by GPS, which measures the position of the vehicle between the satellite and the ground station, and the map information stored on the CD-ROM via the IZO control circuit and the gate array. Input and store this information in work RAM.
  • the process of arranging the position of the car on the map based on the position information and the map information stored in the work RAM is performed by AR TOP, and the image information is obtained. Is stored for the image.
  • the image information stored in the image RAM is passed to the display unit, and the display unit displays the image information on a TFT screen based on the control of the computer with the slave microphone, so that the vehicle information is displayed. An image whose position is arranged on a map can be displayed.
  • the main CPU is constituted by a processor
  • the program EP ROM is constituted by a flash memory
  • the ARTOP is constituted by a logic circuit constituted by an ASIC.
  • the image RAM is composed of DRAM
  • the gate array is composed of a logic circuit composed of ASIC
  • the chip AD of this embodiment can be used for this block. It is also possible to simply use chip MF for the main CPU and program EPROM, and chip D for the image RAM.
  • FIG. 74 is a functional block diagram showing an example of the internal configuration of the CD-ROM drive device.
  • This CD-ROM drive has a microcomputer including a flash memory, a pre-servo circuit, a signal processing circuit, a ROM decoder, a host IZF, a bi-servo circuit, and a signal processing circuit that are bidirectionally connected to the microcomputer. It consists of pickups and SRAMs connected in different directions, DZA connected to a ROM decoder, and buffer RAM connected to a host IZF.
  • the signal processing circuit is connected to a motor ⁇ 4 for driving a CD-ROM, and the signal of CDR # is read by a pickup. The rotation of this motor is controlled by the signals of the pre-servo circuit and signal processing circuit. In addition, speed is connected to DZA.
  • the CD-ROM drive is connected to the host computer via the host IZF.
  • the signal of the CD-ROM is read by a pickup under the control of a microcomputer, the read information is processed by a signal processing circuit, and the processed information is stored in an SRAM. I do.
  • the information stored in the SRAM can be decoded by a ROM decoder and converted to analog signals via DZA, output from the speaker, and temporarily stored in the buffer RAM. After that, it can be output to the host computer via the host IZF.
  • the chip MFA of the present embodiment is used for a block portion of a microcomputer including a flash memory, a signal processing circuit, and the like, and a block portion of a buffer RAM and a host I / F.
  • the chip AD of the present embodiment can be used. It is also possible to simply use a chip MF for a microcomputer part including flash memory and a chip D for a buffer RAM part.
  • FIG. 75 is a functional block diagram showing an example of the internal configuration of the game device.
  • This game machine consists of a main unit control unit, a speaker connected to the main unit control unit, a CD-ROM, an R ⁇ M cassette, a display RAM (SDRAM: 4M) connected to a CRT, a buffer RAM (DRAM: 4M) and It consists of a keyboard and.
  • the main unit control section consists of a main CPU, system ROM (mask ROM: 16M), DRAM (SDRAM: 4M), RAM (SRAM: 256k), sound processor, graphics processor, image compression processor, and I / O control. It is composed of circuits and the like.
  • the main CPU of the main body control unit controls according to a control program stored in the system ROM.
  • CD—ROM, ROM cassette Image and sound information and instruction information from the keyboard are input via the IZO control circuit, and the information is stored in the DRA.VU RAM.
  • the information stored in the DRAM and RA is processed into audio and video signals using a sound processor and a graphic processor, respectively, and the audio signal is output as audio from a speaker, and the video signal is displayed. After temporarily storing it in RAM, it can be displayed as an image on the CRT screen. At this time, the video signal is used by being compressed in the amount of information by an image compression processor and stored in a buffer RAM.
  • the chip MFA of the present embodiment is used for blocks such as a main CPU, a system ROM, a sound processor, and a graphic processor, and the present embodiment is used for blocks such as a DRAM and an image compression processor.
  • a form of chip AD can be used. It is also possible to simply use the chip MF for the main CPU, the system R ⁇ M, and the chip D for the DRAM, RAM, and buffer RAM.
  • FIG. 76 is a functional block diagram showing an example of the internal configuration of the PDA.
  • This PDA consists of a microcomputer including a flash memory consisting of a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit; an LCD connected to the microcomputer's graphic control circuit; Digitizer via AZD connected to power circuit, system memory (mask ROM: 16M) connected to memory control circuit, IC card connected to security management circuit, IR-IF connected to communication control circuit It consists of RS-232C and PCMC IA card via PCMC IA control circuit.
  • This microcomputer is connected to PHS, GSM, ADC, etc. from the communication control circuit via a network.
  • the memory control circuit controls the PDA in accordance with the control program stored in the system memory, converts the information written using the digitizer into a digital signal using AZD, and stores it in the handwriting input circuit.
  • the information stored in the handwriting input circuit can be displayed on an LCD screen after signal processing using a graphic control circuit.
  • security Information such as security management information can be displayed on the LCD screen via the graphic control circuit.
  • communication with PHS, GSM, ADC, etc. can be performed by controlling a communication control circuit via a network, and a PCMCIA card via an IR-IF, RS-232C, PCMCIA control circuit. Information from such sources can also be imported into the micro-computer. The information on the IC card is used for security management by a security management circuit.
  • the chip MFA of the present embodiment is used for a block portion of a micro computer including a flash memory including a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit. Can be. It is also possible to simply use chip D for parts such as graphic control circuits and handwriting input circuits.
  • FIG. 77 is a functional block diagram showing an example of the internal configuration of the mobile communication device.
  • This mobile communication device consists of a CPU including flash memory, a CH codec, an LCD controller Z driver, and an IC card connected to the CPU, and an RF / IF connected to a CH codec via a modem. , Speech codec, L
  • It consists of a CD controller and an LCD connected to the Z driver.
  • An antenna is connected to the RFZIF, and a speaker and a microphone are connected to the speech codec.
  • control is performed by a program stored in the flash memory of the CPU.
  • a signal from an antenna is received via RFZ IF and modulated using a modem.
  • the modulated signal can be converted into an audio signal using a CH codec and a speech codec, and output as audio from a speaker.
  • the voice signal from the microphone is converted using a speech codec and a CH codec, demodulated using a modem, and then transmitted via R / IF. It can be transmitted from an antenna.
  • the chip MFA of the present embodiment is used for a block part such as a CPU and a CH codec, and an LCD controller Z driver and the like are used.
  • the chip AD of the present embodiment can be used. It is also possible to simply use a chip MF for the CPU.
  • the semiconductor integrated circuit device configured by combining the chip MF, the chip MFA, the chip AD, the chip D, and the like according to the present embodiment is a car navigation system, a CD-ROM drive device, a game device, a PDA It can be widely applied to multimedia devices such as mobile communication devices, devices and systems such as information home appliances, and the like.
  • a package structure in which two types of chips, a chip MF using a CPU and a flash memory and a chip D using a DRAM, are packaged reduces the number of external connection terminals. It is possible to reduce the mounting area by reducing the number of chips and by combining two types of chips into one package, and to reduce the cost of the semiconductor integrated circuit device. Further, it is possible to reduce the cost of equipment and systems using the semiconductor integrated circuit device.
  • chip MF and chip D each have a chip MFA or chip AD with a built-in logic circuit such as an AS IC, and if the DRAM is a synchronous DRAM, make the external connection terminals common. Therefore, the number of external connection terminals can be further reduced and cost can be reduced.
  • the access operation from the logic circuit to the DRAM can be performed during the DRAM self-refresh period, the speed of data transfer between the external device and the chip AD can be increased.
  • the CPU itself controls the time and realizes one clock cycle, it is not necessary to exchange wait signals, so that high-speed access can be performed. Further, the speed of processing in equipment and systems using the semiconductor integrated circuit device can be increased.
  • a chip AD on which DRAM and logic circuits are mounted
  • a chip MF on which CPU and flash memory are mounted
  • a chip MFA Even in a packaged package structure, the logic circuit can access the DRAM during the cell self-refreshing period of the DRAM as viewed from the CPU, so high-speed data transfer between the chip AD and chip MF and chip MFA is possible. Can be realized.
  • the timing of processing itself can be controlled from the CPU, that is, the timing of processing itself can be known in the CPU program. It is possible to easily create a program for the semiconductor integrated circuit device.
  • Using a general-purpose DRAM interface enables high-speed operation of chip AD with DRAM and logic circuits, chip MF and chip MFA with CPU and flash memory, etc. Can be directly connected.
  • the process load is reduced by dividing DRAM, logic, flash memory, etc. with different power levels into two or more chips, so that these are mixedly mounted on one chip. As a result, the manufacturing cost of the chip can be significantly reduced.
  • the chip mounting area is reduced by mounting two types of chips, a chip IF using a CPU and a flash memory, and a chip D using a DRAM, in an ultra-thin stacked package to form a single package. It can be significantly reduced.
  • the semiconductor integrated circuit device includes a microcomputer including a CPU, a flash memory, a first chip in which a logic circuit such as an AS IC is formed, a DRAM, and a DRAM.
  • a microcomputer including a CPU, a flash memory, a first chip in which a logic circuit such as an AS IC is formed, a DRAM, and a DRAM.
  • DRAM Data using the self-refresh period of It is useful for semiconductor integrated circuit devices that can achieve high-speed data transfer, and can be widely applied to multimedia devices, information home appliances, and other devices and systems that use these semiconductor integrated circuit devices. it can.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Cette invention concerne un dispositif comprenant un circuit intégré à semi-conducteur et permettant de transférer des données à grande vitesse. La commande d'attente est éliminée de manière à ce qu'un circuit logique puisse accéder à la mémoire DRAM lors de la période de régénération automatique de celle-ci. Ce circuit intégré comprend, d'une part, une puce qui comprend un micro-ordinateur incorporé à une UCT, des mémoires et des circuits périphériques ainsi qu'une mémoire flash et, d'autre part, une autre puce qui comprend des mémoires DRAM et un circuit logique tel qu'un circuit intégré à application spécifique (ASIC). La commande de la mémoire DRAM dépend du mode de celle-ci, à savoir si elle se trouve en période d'accès normal ou en période de régénération automatique. Lorsque la mémoire DRAM se trouve en période de régénération automatique, les opérations de régénération sont annulées de sorte que le circuit logique puisse accéder à ladite mémoire DRAM lorsqu'il en fait la requête en utilisant des signaux de lecture/écriture (R/W).
PCT/JP1996/003548 1996-12-04 1996-12-04 Dispositif comprenant un circuit integre a semi-conducteur WO1998025271A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP1996/003548 WO1998025271A1 (fr) 1996-12-04 1996-12-04 Dispositif comprenant un circuit integre a semi-conducteur
AU10402/97A AU1040297A (en) 1996-12-04 1996-12-04 Semiconductor integrated circuit device
TW086100683A TW329047B (en) 1996-12-04 1997-01-22 Semiconductor integrated circuit device providing DRAM semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/003548 WO1998025271A1 (fr) 1996-12-04 1996-12-04 Dispositif comprenant un circuit integre a semi-conducteur

Publications (1)

Publication Number Publication Date
WO1998025271A1 true WO1998025271A1 (fr) 1998-06-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/003548 WO1998025271A1 (fr) 1996-12-04 1996-12-04 Dispositif comprenant un circuit integre a semi-conducteur

Country Status (3)

Country Link
AU (1) AU1040297A (fr)
TW (1) TW329047B (fr)
WO (1) WO1998025271A1 (fr)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
JP2001202777A (ja) * 2000-01-20 2001-07-27 Casio Electronics Co Ltd Ｓｄｒａｍの制御装置
WO2004049168A1 (fr) * 2002-11-28 2004-06-10 Renesas Technology Corp. Module de memoire, systeme de memoire, et dispositif d'informations
KR101259697B1 (ko) * 2010-04-01 2013-05-02 인텔 코오퍼레이션 메모리 디바이스의 셀프-리프레시 상태로부터의 고속 탈출
US8484410B2 (en) 2010-04-12 2013-07-09 Intel Corporation Method to stagger self refreshes
JP5956708B1 (ja) * 2015-11-30 2016-07-27 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ ダイ及びパッケージ、並びに、ダイの製造方法及びパッケージの生成方法
CN115932530A (zh) * 2023-01-09 2023-04-07 东莞市兆恒机械有限公司 一种半导体检测设备标定的方法

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JPH08221313A (ja) * 1995-02-14 1996-08-30 Hitachi Ltd 半導体装置
JPH08241963A (ja) * 1995-02-10 1996-09-17 Internatl Business Mach Corp <Ibm> 半導体集積回路装置

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JPH08147966A (ja) * 1994-09-21 1996-06-07 Matsushita Electric Ind Co Ltd 半導体集積回路
JPH08167703A (ja) * 1994-10-11 1996-06-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法、ならびにメモリコアチップ及びメモリ周辺回路チップ
JPH08241963A (ja) * 1995-02-10 1996-09-17 Internatl Business Mach Corp <Ibm> 半導体集積回路装置
JPH08221313A (ja) * 1995-02-14 1996-08-30 Hitachi Ltd 半導体装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001202777A (ja) * 2000-01-20 2001-07-27 Casio Electronics Co Ltd Ｓｄｒａｍの制御装置
WO2004049168A1 (fr) * 2002-11-28 2004-06-10 Renesas Technology Corp. Module de memoire, systeme de memoire, et dispositif d'informations
KR100786603B1 (ko) * 2002-11-28 2007-12-21 가부시끼가이샤 르네사스 테크놀로지 메모리 모듈, 메모리시스템 및 정보기기
US7613880B2 (en) 2002-11-28 2009-11-03 Renesas Technology Corp. Memory module, memory system, and information device
US7991954B2 (en) 2002-11-28 2011-08-02 Renesas Electronics Corporation Memory module, memory system, and information device
US8185690B2 (en) 2002-11-28 2012-05-22 Renesas Electronics Corporation Memory module, memory system, and information device
KR101259697B1 (ko) * 2010-04-01 2013-05-02 인텔 코오퍼레이션 메모리 디바이스의 셀프-리프레시 상태로부터의 고속 탈출
US8909856B2 (en) 2010-04-01 2014-12-09 Intel Corporation Fast exit from self-refresh state of a memory device
US8484410B2 (en) 2010-04-12 2013-07-09 Intel Corporation Method to stagger self refreshes
JP5956708B1 (ja) * 2015-11-30 2016-07-27 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ ダイ及びパッケージ、並びに、ダイの製造方法及びパッケージの生成方法
CN115932530A (zh) * 2023-01-09 2023-04-07 东莞市兆恒机械有限公司 一种半导体检测设备标定的方法

Also Published As

Publication number Publication date
AU1040297A (en) 1998-06-29
TW329047B (en) 1998-04-01

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